KR100258606B1 - Pcb circuit board formation method and bga semiconductor package structure using it - Google Patents

Pcb circuit board formation method and bga semiconductor package structure using it Download PDF

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Publication number
KR100258606B1
KR100258606B1 KR1019950036141A KR19950036141A KR100258606B1 KR 100258606 B1 KR100258606 B1 KR 100258606B1 KR 1019950036141 A KR1019950036141 A KR 1019950036141A KR 19950036141 A KR19950036141 A KR 19950036141A KR 100258606 B1 KR100258606 B1 KR 100258606B1
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semiconductor package
heat sink
pcb
semiconductor chip
package structure
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KR1019950036141A
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Korean (ko)
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KR970023906A (en
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허용욱
이무응
배동주
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김규현
아남반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PURPOSE: A PCB circuit board formation method and BGA semiconductor package structure using the same are provided to bond a metal member of excellent conductivity on the PCB circuit board to effectively discharge the heat generated from a semiconductor chip, thereby maximizing the performance and function of the semiconductor chip. CONSTITUTION: A plurality of cavities for inserting a semiconductor chip(1) are formed on the PCB circuit board(4). A heat sink(2) formed of copper or aluminum having excellent thermal conductivity are attached on a bottom surface of the PCB circuit board(4). The semiconductor chip(1) mounted within the cavity of the PCB circuit board(4) is bonded on the heat sink(2) by epoxy(3) and the gold wires(8) of the chip(1) are bonded to the PCB circuit board(4). Further, solder masks(6) and solder balls(5) as I/O ports are attached on a top surface of the PCB circuit board(4).

Description

PCB 기판 형성방법 및 그를 이용한 BGA 반도체 패키지 구조PCB substrate formation method and BGA semiconductor package structure using the same

제1도는 종래의 일반적인 반도체 패키지의 구조를 보인 단면도.1 is a cross-sectional view showing the structure of a conventional general semiconductor package.

제2도는 종래의 BGA 반도체 패키지의 구조를 보인 단면도.2 is a cross-sectional view showing the structure of a conventional BGA semiconductor package.

제3도는 본 발명에 의한 BGA 반도체 패키지의 구조를 보인 단면도.3 is a cross-sectional view showing the structure of a BGA semiconductor package according to the present invention.

제4도는 본 발명에 따른 PCB기판의 공정상태를 나타낸 도면으로,4 is a view showing a process state of the PCB substrate according to the present invention,

a도는 PCB패널의 사시도.a is a perspective view of a PCB panel.

b도는 PCB패널에 다수의 구멍(Cavity)을 형성한 상태의 사시도.b is a perspective view of a state in which a plurality of holes are formed in the PCB panel.

c도는 다수의 구멍을 형성한 PCB패널의 일측면에 히트싱크를 부착하는 상태의 사시도.c is a perspective view of a heat sink attached to one side of a PCB panel having a plurality of holes formed therein;

d도는 다수의 구멍을 형성한 PCB패널의 일측면에 히트싱크가 부착된 사시도.Figure d is a perspective view of the heat sink is attached to one side of the PCB panel formed a plurality of holes.

e도는 PCB패널을 PCB기판 유니트로 사용하기 위하여 PCB패널을 필요한 크기로 절단한 상태의 사시도.Figure e is a perspective view of the PCB panel cut to the required size to use the PCB panel as a PCB substrate unit.

제5도는 PCB기판과 히트싱크와의 접착상태를 도시한 실시예.5 is a view showing an adhesive state between a PCB substrate and a heat sink.

제6도는 본 발명에 따른 PCB기판에 신호라인이 본딩된 상태의 단면도.6 is a cross-sectional view of a signal line bonded to a PCB substrate according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체 칩 2 : 히트싱크1 semiconductor chip 2 heat sink

3 : 에폭시 4 : PCB기판3: epoxy 4: PCB substrate

40 : PCB패널 401 : 구멍(Cavity)40: PCB panel 401: cavity

5 : 솔더볼 6 : 솔더 마스크5: solder ball 6: solder mask

본 발명은 PCB 기판 형성방법 및 그를 이용한 BGA 반도체 패키지 구조에 관한 것으로, 더욱 상세하게는 BGA 반도체 패키지 내의 반도체 칩이 부착되는 부분을 구리와 같은 금속재료를 만들고, 이 금속재료가 외부에 노출되도록 함으로서 반도체 칩에서 발생되는 열의 방출을 극대화 시키도록 하여 반도체 칩의 성능을 최대한 발휘할 수 있도록 한 PCB 기판 형성방법 및 그를 이용한 BGA 반도체 패키지구조에 관한 것이다.The present invention relates to a PCB substrate forming method and a BGA semiconductor package structure using the same, and more particularly, to a metal material such as copper in a portion to which a semiconductor chip is attached in a BGA semiconductor package, and to expose the metal material to the outside. The present invention relates to a PCB substrate forming method and a BGA semiconductor package structure using the same to maximize the discharge of heat generated from the semiconductor chip to maximize the performance of the semiconductor chip.

일반적으로 최근에 각광을 받고 있는 BGA(Ball Grid Array : 볼그리드 어레이) 반도체 패키지는 PCB기판을 패키지의 메인 프레임(Main Frame)으로 사용하고 있는 반면에, 구리합금 또는 니켈합금등을 메인 프레임으로 사용하고 있는 일반적인 패키지와는 그 재료로서 구분할 수 있다.In general, the BGA (Ball Grid Array) semiconductor package, which has recently been in the spotlight, uses PCB as the main frame of the package, whereas copper alloy or nickel alloy is used as the main frame. The material can be distinguished from the general package.

즉, 제1도에 도시된 바와같이 일반적인 패키지는 전도성 금속들인 구리 또는 니켈합금 등을 패키지의 리드프레임으로 사용하여 반도체 칩(1)에서 발생되는 열의 하부를 방출하도록 금속재료를 사용하고 있다.That is, as shown in FIG. 1, a general package uses a metal material to emit a lower portion of heat generated in the semiconductor chip 1 by using conductive metals such as copper or nickel alloy as a lead frame of the package.

그러나, 제2도에 도시된 BGA 반도체 패키지는 특성상 부도체 재료인 PCB기판(4)을 리드프레임으로 사용하고 있는 바, 정상적인 조건하에서 BGA 반도체 패키지 내에 있는 반도체 칩(1)이 동작중에 발생하는 열을 외부로 원활히 방출하지 못한다.However, the BGA semiconductor package shown in FIG. 2 uses a PCB substrate 4, which is a non-conductive material, as a lead frame. Therefore, under normal conditions, the BGA semiconductor package uses heat generated during operation of the semiconductor chip 1 in the BGA semiconductor package. It does not emit smoothly to the outside.

따라서, 이러한 단점을 보완하기 위하여 PCB기판(4)에 상,하부면을 관통하는 관통슬롯(7)을 형성하고, 이 관통슬롯(7) 내부에 구리(Cu) 도금하여 반도체 칩(1)에서 발생되는 열을 효율적으로 방출하도록 함으로서 일반 패키지 보다 우수한 열방출 효과를 얻을 수 있는 것이다.Therefore, in order to compensate for this disadvantage, a through slot 7 penetrating the upper and lower surfaces of the PCB substrate 4 is formed, and copper (Cu) is plated inside the through slot 7 to thereby provide a semiconductor chip 1. By dissipating the generated heat efficiently, it is possible to obtain a better heat dissipation effect than the general package.

그러나, 이러한 BGA 반도체 패키지는 핀(pin) 수가 대부분이 200개가 넘는 다핀으로서, 그 사용되어지는 장비로는 컴퓨터, 통신기기등에 주로 사용되어져 고속성능을 요구하기 때문에 반도체 칩 동작중에 많은 열이 발생될 수 밖에 없으며, 이러한 열을 효율적으로 방출하지 못하면 반도체 칩에서 발생된 열에 의해 반도체 칩의 성능 및 기능이 저하되는 문제점이 있는 것이다.However, this BGA semiconductor package is a multi-pin with more than 200 pins, most of which are used in computers and communication devices, and require high speed performance. Inevitably, if the heat cannot be efficiently discharged, there is a problem that the performance and function of the semiconductor chip are degraded by the heat generated from the semiconductor chip.

따라서, 본 발명은 이와같은 문제점을 해소하기 위하여 발명된 것으로, PCB기판에 전도성이 우수한 금속재를 접착하여 반도체 칩에서 발생되는 열을 보다 효율적으로 방출시킴으로서 반도체 칩의 성능 및 기능을 최대한 발휘할 수 있도록 한 반도체 패키지 구조를 제공함에 그 목적이 있다.Therefore, the present invention was invented to solve such a problem, and by releasing the heat generated from the semiconductor chip more efficiently by adhering a metal material having excellent conductivity to the PCB substrate, it is possible to maximize the performance and function of the semiconductor chip. The purpose is to provide a semiconductor package structure.

본 발명의 목적을 달성하기 위해서는 BGA 반도체 패키지를 구성함에 있어서, PCB기판의 상면에 솔더볼이 부착되고, 그 저면에 열 전도성이 우수한 히트싱크를 접착하되, 상기 PCB기판에는 히트싱크에 직접 반도체 칩이 접착되도록 하기 위하여 구멍(Cavity)을 형성하여 이 구멍을 통해 히트싱크에 직접 반도체 칩을 부착한 것을 특징으로 하는 BGA 반도체 패키지 구조에 의해 가능한 것이다.In order to achieve the object of the present invention in the construction of a BGA semiconductor package, a solder ball is attached to the upper surface of the PCB substrate, and a heat sink having excellent thermal conductivity is adhered to the bottom surface thereof, but the semiconductor chip is directly attached to the heat sink on the PCB substrate. It is possible by the BGA semiconductor package structure characterized by forming a cavity (Cavity) to be bonded and attaching the semiconductor chip directly to the heat sink through the hole.

이하, 본 발명을 첨부된 도면에 의해 상세히 설명하면 다음과 같다.Hereinafter, described in detail by the accompanying drawings of the present invention.

제3도는 본 발명의 반도체 패키지 구조를 도시하고 있는 바, PCB기판(4)에 반도체 칩(1)이 들어갈 수 있도록 구멍(401 : Cavity)이 형성되고, 상기 PCB기판(4)의 저면에는 열 전도성이 우수한 구리 또는 알루미늄으로 된 히트싱크(2)가 부착되며, 상기 PCB기판(4)의 구멍(401)에 반도체 칩(1)이 장착되어 상기 히트싱크(2)의 상면에 에폭시(3)에 의해 반도체 칩(1)의 부착되며 상기 반도체 칩(1)에는 골드와이어(8)로 PCB기판(4)에 본딩되어 있으며 상기 CPB기판(4)의 상면에 솔더마스크(6)와, 입.출력 단자인 솔더볼(5)이 부착되어 있다. 또한, 상기 반도체 칩(1)의 몰딩은 일반적으로 사용하는 몰드 컴파운드 대신에 액체 타입의 글로우브(Globe)를 사용한다.3 illustrates a semiconductor package structure of the present invention, in which a hole 401 is formed in the PCB substrate 4 to allow the semiconductor chip 1 to enter, and a heat is formed on the bottom surface of the PCB substrate 4. A heat sink 2 made of copper or aluminum having excellent conductivity is attached, and a semiconductor chip 1 is mounted in a hole 401 of the PCB board 4 so that an epoxy 3 is formed on an upper surface of the heat sink 2. Is attached to the semiconductor chip (1) and bonded to the PCB substrate (4) with gold wires (8) on the upper surface of the CPB substrate (4). The solder ball 5 which is an output terminal is attached. In addition, the molding of the semiconductor chip 1 uses a liquid type glove instead of a mold compound generally used.

이와같은 구조의 BGA 반도체 패키지는 반도체 칩(1)이 동작중에 발생되는 열을 PCB기판(4)의 저면에 부착된 히드싱크(2)에 의해 방출되므로서 열 방출의 효과를 극대화 시킬 수 있는 것이다.The BGA semiconductor package having such a structure can maximize the effect of heat dissipation by dissipating heat generated during operation of the semiconductor chip 1 by the heat sink 2 attached to the bottom surface of the PCB 4. .

또한, 제5도에서와 같이 다층을 갖는 PCB기판(4)의 열방출을 극대화 시키기 위하여 PCB기판(4)에 관통슬롯(7)을 형성하여 히트싱크(2)의 상면과 연결시키면 20%이상의 열 방출의 효과를 기대 할 수 있다.In addition, as shown in FIG. 5, in order to maximize heat dissipation of the PCB substrate 4 having a multilayer, a through slot 7 is formed on the PCB 4 to be connected to the top surface of the heat sink 2 to be 20% or more. The effect of heat dissipation can be expected.

제4a도∼제4e도는 본 발명에 따른 PCB기판(4)을 제조하기 위한 공정상태를 나타낸 도면으로서, 먼저 PCB패널(40)의 일면 또는 양면에 원하는 회로 패턴(Pattern)을 형성하고, 와이어 본딩이 요구되는 리드 핑거(Lead Finger) 부분을 제외한 PCB 패널(40)의 일면 또는 양면에 솔더마스크를 입혀 경화(Bake) 한후, 리드 핑거 부분에 니켈(Ni) 또는 금(Au) 도금을 입힌 다음, 반도체 칩(1)이 장착되는 부분에 각각 구멍(401 : Cavity)을 형성한다.(제4a도, 제4b도))4a to 4e are diagrams showing the process state for manufacturing the PCB board 4 according to the present invention, first forming a desired circuit pattern (Pattern) on one or both sides of the PCB panel 40, the wire bonding After hardening by soldering one side or both sides of the PCB panel 40 except for the required lead finger portion, the lead finger portion is coated with nickel (Ni) or gold (Au) plating, and then Holes 401 (Cavity) are formed in portions where the semiconductor chip 1 is mounted, respectively (FIGS. 4A and 4B).

이와같이 구멍(401)을 형성한 PCB패널(40)의 일측면에 열 전도성이 우수한 구리 또는 알루미늄으로 된 히트싱크(2)를 접착테이프(21)를 이용하여 접착시킨다.(제4a∼d도))In this way, the heat sink 2 made of copper or aluminum having excellent thermal conductivity is bonded to one side of the PCB panel 40 having the holes 401 by using the adhesive tape 21 (FIGS. 4A to D). )

상기와 같은 상태의 PCB패널(40)을 제조공정이 용이한 상태의 여러개의 유니트를 포함하는 스트립 타입(40A : Strip Type)이나, 또는 하나의 싱글 타입(40B : Single Type)으로 잘라 사용하게 된다.(제4e도)) 이때, 상기 PCB패널(40)은 펀치 공구, 레이져 또는 소잉(Sawing)장비 등을 이용하여 자르게 된다.The PCB panel 40 in the above state is cut into a strip type (40A: Strip Type) or a single type (40B: Single Type) including a plurality of units in an easy manufacturing process. At this time, the PCB panel 40 is cut using a punch tool, a laser or a sawing equipment.

상기 반도체 칩(1)이 부착되는 히트싱크(2)의 표면에는 PCB기판(4)과의 접착강도를 높이기 위하여 흑색 산화물(Black oxide)을 처리하고, 외부로 노출되는 히트싱크(2)의 표면에는 니켈 도금한다.The surface of the heat sink 2 to which the semiconductor chip 1 is attached is treated with black oxide in order to increase the adhesive strength with the PCB substrate 4, and the surface of the heat sink 2 exposed to the outside. Nickel plated.

또한, 제6도와 같이 PCB기판(4)의 구멍(401) 주변에 와이어(8)의 다운 본드(Down Bond)을 위해 그라운드(Ground) 및 파워 링(Power Ring)을 형성할 수 있다.In addition, as shown in FIG. 6, a ground and a power ring may be formed around the hole 401 of the PCB 4 to allow a down bond of the wire 8.

이와같이 구성되는 본 발명의 반도체 패키지는 PCB패널에서 미리 반도체 칩이 장착되는 부분에 구멍을 형성하고, 이 PCB패널의 일면에 히트싱크를 부착하여 스트립 타입이나, 싱글 타입의 PCB기판 유니트를 형성하여 제조함으로서 그 제조공정이 간단하고, 완성된 패키지 내의 반도체 칩에서 발생되는 열을 보다 효율적으로 방출시킴으로서 반도체 칩의 성능 및 기능을 최대한 발휘하여 패키지의 신뢰성을 향상시킬 수 있는 등의 효과가 있다.The semiconductor package of the present invention configured as described above is manufactured by forming a hole in a portion where the semiconductor chip is mounted in the PCB panel in advance, and attaching a heat sink to one surface of the PCB panel to form a strip type or a single type PCB substrate unit. By doing so, the manufacturing process is simple, and the heat generated from the semiconductor chip in the finished package can be more efficiently discharged, thereby maximizing the performance and function of the semiconductor chip and improving the reliability of the package.

Claims (9)

BGA 반도체 패키지를 구성함에 있어서, PCB기판의 상면에 솔더볼이 부착되고, 그 저면에 열 전도성이 우수한 히트싱크를 접착하되, 상기 PCB기판에는 히트싱크에 직접 반도체 칩이 접착되도록 하기 위하여 구멍(Cavity)을 형성하여 이 구멍을 통해 히트싱크에 직접 반도체 칩을 부착 한 것을 특징으로 하는 BGA 반도체 패키지 구조.In constructing a BGA semiconductor package, a solder ball is attached to an upper surface of a PCB substrate and a heat sink having excellent thermal conductivity is adhered to a lower surface thereof, and a cavity is attached to the PCB substrate so that the semiconductor chip is directly bonded to the heat sink. BGA semiconductor package structure, characterized in that by attaching a semiconductor chip directly to the heat sink through this hole. 제1항에 있어서, 상기 히트싱크는 구리 또는 알루미늄으로 된 것을 특징으로 하는 BGA 반도체 패키지 구조.The BGA semiconductor package structure of claim 1, wherein the heat sink is made of copper or aluminum. 제1항에 있어서, 상기 히트싱크는 반도체 칩이 부착되는 표면에는 PCB기판과의 접착강도를 높이기 위하여 흑색 산화물(Black oxide)을 처리하여서 된 것을 특징으로 하는 BGA 반도체 패키지 구조.The BGA semiconductor package structure of claim 1, wherein the heat sink is formed by treating black oxide on a surface to which the semiconductor chip is attached to increase adhesion strength with a PCB substrate. 제1항에 있어서, 상기 히트싱크는 외부로 노출되는 표면에 니켈(Ni)도금 하여서 된 것을 징으로 하는 BG 반도체 패키지 구조.The BG semiconductor package structure according to claim 1, wherein the heat sink is formed by plating nickel (Ni) on a surface exposed to the outside. 제1항에 있어서, 상기 PCB기판에 관통슬롯을 형성하여 히트싱크와 연결되도록 된 것을 특징으로 하는 BGA 반도체 패키지 구조.The BGA semiconductor package structure of claim 1, wherein a through slot is formed in the PCB to be connected to a heat sink. 제1항에 있어서, 상기 반도체 칩은 액체 타입의 글로우브(Globe)로 몰딩 된 것을 특징으로 하는 BGA 반도체 패키지 구조.The BGA semiconductor package structure of claim 1, wherein the semiconductor chip is molded with a liquid-type globe. 제1항에 있어서, 상기 PCB기판의 구멍 주변에 와이어의 다운본드(Down Bond)을 위해 그라운드(Ground) 및 파우어 링(Power Ring)이 형성된 것을 특징으로 하는 BGA 반도체 패키지 구조.The BGA semiconductor package structure of claim 1, wherein a ground and a power ring are formed around the hole of the PCB to form a down bond of the wire. 일면 또는 양면에 원하는 회로 패턴(Pattern)을 형성하고, 회로 패턴 상부에 니켈(Ni) 또는 금(Au)도금을 입힌 다음, 솔더 마스크를 일면 또는 양면에 입혀 PCB패널을 형성하는 단계와, 상기 PCB패널에 반도체 칩이 장착되는 부분에 구멍(Cavity)을 형성하는 단계와, 상기 구멍을 형성한 PCB패널의 일측면에 열 전도성이 우수한 히트싱크를 접착 테이프를 이용하여 접착시키는 단계와, 상기 단계를 거친 PCB패널을 제조공정이 용이하도록 스트립 타입(Strip Type) 또는, 싱글 타입(Single Type)으로 절단하는 단계로 이루어진 것을 특징으로 하는 PCB 기판 형성방법.Forming a desired circuit pattern on one side or both sides, applying nickel (Ni) or gold (Au) plating on the circuit pattern, and then forming a PCB panel by applying a solder mask on one side or both sides; Forming a cavity in a portion where the semiconductor chip is mounted on the panel, bonding a heat sink having excellent thermal conductivity to one side of the formed PCB panel using an adhesive tape, and PCB substrate forming method comprising the step of cutting the rough PCB panel in a strip type or a single type to facilitate the manufacturing process. 제8항에 있어서, 상기 PCB패널은 펀치 공구, 레이져 또는 소잉(Sawing)장비로 절단하는 것을 특징으로 하는 PCB 기판 형성방법.The method of claim 8, wherein the PCB panel is cut by a punch tool, a laser, or a sawing device.
KR1019950036141A 1995-10-19 1995-10-19 Pcb circuit board formation method and bga semiconductor package structure using it KR100258606B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030066996A (en) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 Ball grid array package with improved thermal emission property
KR20040032474A (en) * 2002-10-10 2004-04-17 (주)동양기연 A heat sink used in semiconductor package
KR100480834B1 (en) * 2002-11-27 2005-04-07 앰코 테크놀로지 코리아 주식회사 Permanent-tape structure for laser marking

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KR20010057046A (en) * 1999-12-17 2001-07-04 이형도 Package substrate having cavity
KR100443399B1 (en) * 2001-10-25 2004-08-09 삼성전자주식회사 Semiconductor package having thermal interface material(TIM) formed void
KR100471413B1 (en) * 2002-03-27 2005-02-21 주식회사 칩팩코리아 Tape ball grid array package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030066996A (en) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 Ball grid array package with improved thermal emission property
KR20040032474A (en) * 2002-10-10 2004-04-17 (주)동양기연 A heat sink used in semiconductor package
KR100480834B1 (en) * 2002-11-27 2005-04-07 앰코 테크놀로지 코리아 주식회사 Permanent-tape structure for laser marking

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