KR20030002319A - method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to improve capacitance by preventing a tetra ethyl ortho silicate(TEOS) layer from being over-etched, and to easily check a profile after an etch process by effectively eliminating a hard mask while using a gap-fill insulation layer. CONSTITUTION: An interlayer dielectric(33) is formed to expose a predetermined region of a substrate(31). A contact pad is so formed to be in contact with the exposed region of the substrate. The first and second insulation layers are sequentially formed on the interlayer dielectric. A hard mask having a predetermined pattern is formed on the second insulation layer. A contact hole is formed in the second and first insulation layers to expose the contact pad by using the hard mask. A gap-fill insulation layer(38) is formed on the entire surface to fill the contact hole. The gap-fill insulation layer is etched by using the hard mask as an etch stop layer. After the hard mask is removed by using the gap-fill insulation layer as a buffer layer, the gap-fill insulation layer is eliminated. A lower electrode of capacitor is formed on the second insulation layer including the contact hole. A dielectric layer and an upper electrode are formed on the lower electrode of capacitor.

Description

Method for fabricating capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a capacitor manufacturing method capable of increasing capacitance without increasing an area.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

Although not shown in the figure, a transistor having a source / drain and a gate is formed on the silicon substrate 11.

In FIG. 1A, an interlayer insulating film 13 is formed on an entire surface of a silicon substrate 11 including the transistor, and a contact hole is formed in the interlayer insulating film 13 so that the source is exposed. ) The pad 12a and the poly plug 12b are formed.

Thereafter, a silicon nitride film 14 (SiN) is deposited on the poly plug 12b and the interlayer insulating film 13, and a TEOS (Tetra Ethyl Ortho Silicate) film 15 is deposited thereon.

Then, a hard mask 16 is deposited on the TEOS film 15.

At this time, the hard mask 16 is formed of polysilicon, and is subsequently formed for etching the TEOS film 15 having a high thickness during the capacitor forming photo process.

Next, after the photosensitive film 17 is applied on the hard mask 16, the capacitor formation region is selectively removed later by using an exposure and development process.

In FIG. 1B, the hard mask 16 is etched to expose the TEOS film 15 using the removed photoresist film 17 as a mask.

Thereafter, using the photoresist film 17 and the hard mask 16 as a mask, the TEOS film 15 and the silicon nitride film 14 are sequentially etched to expose the poly plug 12b and the interlayer insulating film 13 to form contact holes. do.

In FIG. 1C, an amorphous silicon layer 18 is deposited on the entire surface including the contact hole, the TEOS layer 15, and the hard mask 16, and a thermal process is performed as shown in FIG. 1D. (18) A HSG (Hemi-Spherical Silicon Grain) film 19 is formed on the surface.

In FIG. 1E, an Undoped Silicate Glass (USG) film 20 is deposited on the entire product.

Subsequently, the neighboring amorphous pulses are removed by removing the HSG film 19, the amorphous pulse silicon layer 18, and the hard mask 16 using a chemical mechanical polishing (CMP) process to expose the TEOS film 15 as shown in FIG. 1F. The silicon layers 18 are separated from each other.

As a result, capacitor lower electrodes separated from each other are formed.

Since the CMP process must be performed until the hard mask 16 on the TEOS film 15 is removed in the separation process, the TEOS film may be damaged a lot and its height may be lowered.

In addition, when the hard mask is removed by a simple polysilicon etch back without performing the CMP process in which the USG film is formed, a problem may occur in which the amorphous silicon layer and the poly plug are etched together.

After the USG film 20 is removed by the wet etching process, the dielectric film 21 is formed on the lower electrode and the front surface, and the upper electrode 22 is formed on the lower electrode and the dielectric film 21.

In this case, adjacent upper electrodes 22 are separated from each other.

The capacitor manufacturing method of the conventional semiconductor device as described above has the following problems.

If the CMP process is performed while the hard mask is present on the TEOS film, the TEOS film is damaged and the height is lowered, thereby reducing the capacitance later.

Disclosure of Invention The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device suitable for effectively removing a hard mask to improve capacitance.

1A through 1F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

2A through 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

31: silicon substrate 32a: landing pad

32b: poly plug 33: interlayer insulating film

34 silicon nitride film 35 TEOS film

36: hard mask 37: photosensitive film

38 gap gap insulating film 39 amorphous silicon layer

40: HSG film 41: USG film

42: dielectric film 43: upper electrode

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method comprising: forming an interlayer insulating film to expose a region of a substrate, forming a contact pad to contact a exposed region of the substrate, and Sequentially forming a first insulating film and a second insulating film on the interlayer insulating film, forming a hard mask having a predetermined pattern on the second insulating film, and using the hard mask to expose the contact pads. Forming a contact hole in the insulating film and the first insulating film, forming a gap fill insulating film on the entire surface to fill the contact hole, etching the gap fill insulating film using the hard mask as an etch stop layer, and Removing the gap fill insulating layer after removing the hard mask using the gap fill insulating layer as a buffer layer, and including the contact hole. Characterized by the steps of forming a dielectric film and an upper electrode on the capacitor lower electrode to form a capacitor lower electrode on the second insulating film.

The present invention improves the problem that the capacitance decreases as the height of the TEOS film is lowered by polishing more than necessary when performing the CMP (Chemical Mechanical Polishing) process by removing the USG (Undoped Silicate Glass) film and the hard mask.

Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

Although not shown in the figure, a transistor having a source / drain and a gate is formed on the silicon substrate 31.

In FIG. 2A, an interlayer insulating film 33 is formed on the entire surface of the silicon substrate 31 including the transistor, and contact holes are formed in the interlayer insulating film 33 so that the source is exposed. ) The pad 32a and the poly plug 32b are formed.

Thereafter, a silicon nitride film 34 (SiN) is deposited on the poly plug 32b and the interlayer insulating film 33, and a TEOS (Tetra Ethyl Ortho Silicate) film 35 is deposited thereon.

Then, a hard mask 36 is deposited on the TEOS film 35.

At this time, the hard mask 36 is formed of polysilicon, and is subsequently formed for etching the TEOS film 35 having a high thickness during the photolithography process.

Next, after the photosensitive film 37 is applied on the hard mask 36, the capacitor formation region is selectively removed later using an exposure and development process.

In FIG. 2B, the hard mask 36 is etched to expose the TEOS film 35 using the removed photoresist 37 as a mask.

Thereafter, using the photoresist film 37 and the hard mask 36 as a mask, the TEOS film 35 and the silicon nitride film 34 are sequentially etched to expose the poly plug 32b and the interlayer insulating film 33 to form contact holes. do.

In addition, a gap fill insulating film 38 is deposited on the entire surface to fill the gap, that is, the contact hole.

At this time, the gap fill insulating film 38 is formed of a silicon oxide film (SiO 2) or an organic material (photoresist). The gap fill insulating film 38 is used to reduce the etching of another layer later. In particular, the loss of the TEOS film 35 is minimized. Buffering function.

In FIG. 2C, the gap fill insulating layer 38 is etched back (including F ions) so that the gap fill insulating layer 38 remains only in the contact hole.

When the gap fill insulating film 38 is formed of a silicon oxide film in the etch back process, the hard mask 36 formed of polysilicon has a lower selective etching force than the gap fill insulating film 38 so that the etching is stopped when the hard mask 36 is exposed. Be sure to

On the other hand, when the organic material is used as the gap fill insulating film 38, the etching force of the oxide film is slow during the etch back process.

In FIG. 2D, the hard mask 36 is removed to expose the TEOS film 35 by performing poly etch back. Proceed with etch-back Cl ions.

In the process of removing the hard mask 36, only the exposed hard mask 36 is removed by increasing the selective etching power of the hard mask 36 formed of polysilicon compared to the gap fill insulating layer 38 formed of the oxide film.

In FIG. 2E, the gap fill insulating film 38 remaining in the contact hole is removed.

In this case, when the gapfill insulating film 38 is a silicon oxide film, the gapfill insulating film 38 is removed using a material containing F, and in the case of an organic material, the gapfill insulating film 38 is removed using a material containing O or H 2 SO 4.

In FIG. 2F, an amorphous silicon layer 39 for capacitor lower electrodes is deposited on the entire surface including the contact hole and the TEOS film 35, and a thermal process is performed to HSG (HSG) on the surface of the Apolpulse silicon layer 39. A Hemi-Spherical Silicon Grain) film 40 is formed.

Subsequently, a USG (Undoped Silicate Glass) film 41 is deposited on the entire product, and the HSG film 40 and the amorphous pulse silicon layer 39 are separated from each other by using a chemical mechanical polishing (CMP) process.

As a result, capacitor lower electrodes separated from each other are formed.

In FIG. 2G, after the USG film 41 is removed by a wet etching process, a dielectric film 42 is formed on the separated lower electrode and the front surface, and an upper electrode 43 is formed on the lower electrode and the dielectric film 42. In this case, adjacent upper electrodes 43 are separated from each other.

The capacitor manufacturing method of the semiconductor device of the present invention as described above has the following effects.

To prevent excessive etching of the TEOS film can improve the capacitance in the future.

Since the hard mask may be effectively removed using the gap fill insulating layer, a problem in the conventional hard mask etching may be eliminated, and a profile after etching may be easily confirmed.

Claims (5)

Forming an interlayer insulating film to expose a region of the substrate; Forming a contact pad to contact the exposed area of the substrate; Sequentially forming a first insulating film and a second insulating film on the interlayer insulating film; Forming a hard mask having a predetermined pattern on the second insulating layer; Forming a contact hole in the second insulating layer and the first insulating layer to expose the contact pad using the hard mask; Forming a gapfill insulating film on the entire surface of the contact hole to fill the contact hole; Etching the gapfill insulating layer using the hard mask as an etch stop layer; Removing the gap fill insulating film after removing the hard mask using the gap fill insulating film as a buffer film; Forming a capacitor lower electrode on the second insulating layer including the contact hole; And forming a dielectric film and an upper electrode on the capacitor lower electrode. The method of claim 1, The hard mask may be formed by depositing a polysilicon layer on the second insulating layer; Forming a photoresist pattern on the polysilicon layer; And etching the polysilicon layer by using the photoresist pattern as a mask. The method of claim 1, The capacitor lower electrode may be formed by depositing an amorphous silicon layer on the entire surface including the contact hole; Heat-treating to form a Hemi Spherical Grain (HSG) in the amorphous pulse silicon layer; Forming a buffer insulating film on the second insulating film including the contact hole; And chemically and mechanically polishing the buffer insulating layer to expose the second insulating layer. The method of claim 1, And the second insulating layer is formed of TEOS. The method of claim 1, The gap fill insulating film is formed of a silicon oxide film or an organic material (photoresist) capacitor manufacturing method of a semiconductor device, characterized in that.