KR20030001798A - Image sensor and fabricating method of the same - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to prevent a cross-talk and to simplify manufacturing processes without forming a field insulating layer. CONSTITUTION: A channel stop region(P+) of the first conductive type is formed in a semiconductor layer(10) of the first conductive type so as to isolate. A gate electrode(14) including a gate oxide(14) and a gate spacer(16) is formed on the semiconductor layer(10). The first doping region(n-) for a photodiode is formed in the semiconductor layer(10) adjacent to the channel stop region(P+), wherein the depth of the first doping region(n-) is same to the depth of the channel stop region(P+). The second doping region(P0) for the photodiode is formed in the first doping region(n-).

Description

Image sensor and fabrication method {Image sensor and fabricating method of the same}

The present invention relates to a semiconductor device, and more particularly, to an image sensor, and more particularly, to an image sensor capable of securing a photodiode area and minimizing cross talk between pixels.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.

In manufacturing such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, and one of them is a light condensing technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data. To increase light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).

FIG. 1 is a unit pixel circuit diagram of a conventional CMOS image sensor, and a submicron CMOS Epi process is applied to increase sensitivity and reduce cross talk effects between unit pixels.

The unit pixel is composed of one low voltage buried photodiode and four NMOS transistors. Unlike the conventional photo gate structure, the low voltage buried photodiode has a polysilicon with a light sensing region. Not only is it covered, it has excellent light sensitivity for short wavelength blue light as well as increase the depth of depletion in the light sensing area, so the light sensitivity for long wavelength red or infrared light is also excellent. On the other hand, the low-voltage buried photodiode structure allows photogenerated charges in the photosensitive area to be completely transported to the Floating Sensing Node, which significantly increases the charge transfer efficiency. There are advantages to it.

In addition, the transfer gate (Tx), that is, the gate electrode and the reset gate (Rx), which transfer photocharges among the four transistors, is caused by a voltage drop due to a positive threshold voltage. In order to prevent the loss of charge transport efficiency, the NMOS transistor has a negative threshold voltage. In this case, the N-LDD ion implantation is omitted so that the overlap capacitance between the gate electrode and the reset gate and the floating sensing node is reduced. (Overlap Capacitance) can be lowered, so that the potential change of the floating sensing node can be amplified according to the amount of charge carried. (△ V-ΔQ / C)

Meanwhile, the drive gate (Sx) serving as a source follower is composed of a general submicron NMOS transistor. Such a structure was constructed with minimal changes to the submicron CMOS Epi process, and the thermal cycle was designed to be completely unchanged. On the other hand, a color filter array composed of red, green, blue, or yellow, magenta, cyan, and the like on a unit pixel array for implementing a color image. (Color Filter Array) The process of forming.

The operation principle of obtaining an output from such a unit pixel is as follows.

end. Turn off Tx, Rx, Sx. The low voltage buried photodiode is then fully depletion.

I. Photogenerated charge is collected in a low voltage buried photo diode.

All. After a proper integration time, the Rx is turned on to reset the floating sensing node first.

la. The unit pixel is turned on by turning on Sx.

hemp. Measure the output voltage (V1) of the source follower buffer. This value simply means the CD level shift of the Floating Sensing Node.

bar. Turn on Tx.

four. All photogenerated charges are transported to Floating Sensing Nodes.

Ah. Turn off Tx.

character. Measure the output voltage (V2) of the source follower buffer.

car. The output signals V1-V2 are the result of the photocharge transport resulting from the difference between V1 and V2 and are pure signal values without noise. This method is called CDS (Corelated Double Sampling).

Ka. Repeat the process of 'a' to 'tea'. However, the low voltage buried photodiode is fully depleted during the 'dead' process.

2A to 2C are cross-sectional views illustrating an image sensor manufacturing process according to the prior art.

First of all, the drive gate (Dx) serving as a source follower and the switching gate (addressing) can be addressed by switching. A step of forming a P-well (not shown) is carried out so as to contain (Select Gate, Sx).

Subsequently, as shown in FIG. 2A, a pad oxide film 11 / buffer polysilicon film (not shown) is used to distinguish a field oxide region from an active region. / Nitride (Nitride, 12), etc. are continuously applied, and then the photoresist film (PR) is coated, exposure and development are performed using an element isolation (ISO) mask to etch the portion to be the field insulating film region through dry etching.

Next, as shown in FIG. 2B, P + ion implantation is performed for the N channel field stop, and then the field insulating layer 13 is formed through a thermal process, and then the pad oxide layer 11 on the active region is formed. ) And the nitride film 12 are removed by etching.

In this case, the channel stop region P + is formed to have a width of 'A', thereby invading the photodiode region, and the depth is narrowed as 'B'.

Next, as shown in FIG. 2C, a polysilicon film and a tungsten silicide film are successively coated to form the gate electrodes of the four NMOS transistors in the unit pixel, and a photoresist film (not shown) is applied, followed by a mask for forming a gate electrode. Exposure and development are carried out using. At this time, since the doping profile of the low voltage buried photodiode on one side of the formed transfer gate (Tx) determines the charge transfer efficiency, the thickness of the gate electrode is sufficiently increased. By thickening, high energy N-type ion implantation and low energy P-type ion implantation to form a low voltage buried photodiode can be self-aligned on one side of the gate electrode (Thick Polycide process).

If the thickness of the gate electrode is not thick enough, dopant phosphorus (P31) penetrates through the gate electrode during high-energy N-type ion implantation, and high-energy P-type ion implantation and low-energy P-type ion implantation are performed on one side of the gate electrode. Self alignment is not possible at, resulting in low charge transfer efficiency.

Subsequently, a polyetch layer of portions other than the gate electrode is removed by dry etching to form the gate electrodes 14 and 15, and then a photoresist (not shown) is applied to form a low voltage buried photodiode. Energy N-type ion implantation is performed, wherein one side of the high energy N-type ion implantation mask is aligned at the center of the gate electrode and the other side is aligned at the interface between the field oxide film and the active region. Part of it must enter the active area. That is, the low voltage buried photodiode must include a region in which low energy P-type ion implantation is to be performed and high energy N-type ion implantation is not performed (Connection Window structure).

This is because the region formed by the low energy P-type ion implantation should not be electrically separated from the P-Epi layer by the region formed by the high energy N-type ion implantation. If the low-energy P-type region is not electrically connected to the P-epi layer, the voltage buried photodiode will not function normally and will act like a simple PN junction. Through this process, the first deep buried PN junction is formed on the low concentration P-epi layer, and then the photoresist film is removed.

Subsequently, after forming a photosensitive film (not shown) to form a low voltage buried photodiode, low energy P-type ion implantation is performed using a low energy P-type ion implantation mask. One side of the mask is aligned at the center of the gate electrode, and the other side is aligned at the interface between the field oxide film and the active region, and no part enters the active region. Therefore, the low-energy P-type ion implantation region is electrically connected to the low-concentration P-epi layer at the interface between the field insulating layer 13 and the active region where the high-energy N-type ion implantation is not performed, so that the low voltage buried photodiode is operated. It always has an equipotential. Through this process, a high energy N-type ion implantation layer and a second shallow PN junction are formed, and then the photoresist film (not shown) is removed.

On the other hand, the conventional photodiode as described above has the following problems.

That is, since the channel field stop P + has a width as wide as 'A' shown in FIG. 2C, the photodiode region is reduced by invading the photodiode region, and ion implantation by 'B' as compared to the n- region. The non-existent area exists, which causes cross talk of electrons between pixels, causing malfunction of the image sensor.

The present invention proposed to solve the problems of the prior art as described above, the process can be simplified by isolating the elements only by ion implantation for the channel stop without forming a field insulating film for device isolation, P + ions It is an object of the present invention to provide an image sensor and a method of manufacturing the same, which can secure a wide photodiode area and prevent cross talk by deeply implanting ion.

1 is a unit pixel circuit diagram of a conventional CMOS image sensor;

2A to 2C are cross-sectional views illustrating an image sensor manufacturing process according to the prior art;

3A to 3D are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

10: semiconductor layer

14, 15, and 16 gate electrodes

P +: Channel Stop Area

In order to achieve the above object, the present invention, the first conductive semiconductor layer; A channel stop region of a first conductivity type disposed within the semiconductor layer at a first depth to serve as isolation between devices; A gate electrode disposed on the semiconductor layer; A first impurity region of a second conductive type for photodiode disposed in the semiconductor layer at a second depth substantially the same as the channel stop region and in contact with the gate electrode and the channel stop region; And a second impurity region of the first conductivity type for photodiode disposed on the first impurity region and in contact with the surface of the semiconductor layer.

In addition, to achieve the above object, the present invention, the first step of forming a channel stop region of the first conductive type for inter-device separation at a first depth inside the semiconductor layer of the first conductive type through ion implantation; Forming a gate electrode on the semiconductor layer; Forming a second impurity region of a second conductivity type in contact with the channel stop region and the gate electrode at a second depth substantially equal to the channel stop region through ion implantation; And a fourth step of forming a second impurity region of a first conductivity type at an interface in contact with the semiconductor layer in the first impurity region.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3B is a cross-sectional view illustrating the image sensor of the present invention.

Referring to FIG. 3B, the image sensor of the present invention is a P-type semiconductor layer 10, having a width A ′ inside the semiconductor layer 10, and disposed inside the semiconductor layer 10 to a depth B ′. P-type channel stop region P + acting as a separation between the gate electrodes, gate electrodes 14, 15 and 16 disposed on the semiconductor layer 10, and a depth of 'C' substantially equal to the channel stop region P +. N-type impurity regions (n-) for photodiodes and upper portions of the impurity regions (n-), which are disposed in the furnace semiconductor layer (10) and are in contact with the gate electrodes (14, 15, 16) and the channel stop regions (P +). It is disposed in the semiconductor film 10, and is provided with a P-type impurity region (P0) for the photodiode in contact with the surface.

Hereinafter, an image sensor manufacturing process of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3B are cross-sectional views illustrating a manufacturing process of an image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, a pad oxide film 11 / buffer polysilicon film (not shown) is continuously applied to separate the isolation region and the active region between devices, and then a photoresist film (not shown) is applied. The coating layer is exposed and developed using the device isolation mask 20, and the part to be the isolation region between devices is etched through dry etching.

Subsequently, P + ion implantation is performed to form a deep channel stop region P + such as B '. The width thereof is as narrow as A' to prevent invasion into the photodiode region as much as possible. Use a ratio to form deeper. Subsequently, the pad oxide film 11 on the active region is removed.

In addition, since the channel stop region P + plays a role of isolation between devices, the channel stop region P + may take the role of a field insulating film, and thus the field insulating film forming process may be omitted.

Next, as shown in FIG. 3B, a polysilicon film and a tungsten silicide film are successively applied to form the gate electrodes of the four NMOS transistors in the unit pixel, and a photoresist film (not shown) is applied, followed by a mask for forming a gate electrode. Exposure and development are carried out using. At this time, since the doping profile of the low voltage buried photodiode on one side of the gate electrode formed later determines the charge transfer efficiency, the low voltage buried photodiode is made thick enough to make the gate electrode thick. High-energy N-type ion implantation and low-energy P-type ion implantation to form a self-alignment can be performed on one side of the gate electrode (Thick Polycide process).

If the thickness of the gate electrode is not thick enough, dopant phosphorus (P31) penetrates through the gate electrode during high-energy N-type ion implantation, and high-energy P-type ion implantation and low-energy P-type ion implantation are performed on one side of the gate electrode. Self alignment is not possible at, resulting in low charge transfer efficiency.

Subsequently, the polyelectrode layers other than the gate electrodes 14 and 15 are removed by dry etching to form the gate electrodes 14 and 15, and then a photoresist film (not shown) is used to form a low voltage buried photodiode. After applying the high energy N-type ion implantation, one side of the high energy N-type ion implantation mask is aligned at the center of the gate electrode and the other side of the field oxide film and the active region Align at the interface, part of which must be brought into the active area. That is, the low voltage buried photodiode must include a region in which low energy P-type ion implantation is to be performed and high energy N-type ion implantation is not performed (Connection Window structure).

This is because the region formed by the low energy P-type ion implantation should not be electrically separated from the P-Epi layer by the region formed by the high energy N-type ion implantation. If the low-energy P-type region is not electrically connected to the P-epi layer, the voltage buried photodiode will not function normally and will act like a simple PN junction. Through this process, the first deep buried PN junction is formed on the low concentration P-epi layer, and then the photoresist film is removed.

Subsequently, after forming a photosensitive film (not shown) to form a low voltage buried photodiode, low energy P-type ion implantation is performed using a low energy P-type ion implantation mask. One side of the mask is aligned at the center of the gate electrode, and the other side is aligned at the interface between the field oxide film and the active region, and no part enters the active region. Therefore, the low-energy P-type implantation region is electrically connected to the low-concentration P-epi layer at the interface between the device isolation region, that is, the P + region and the active region, where the high-energy N-type implantation is not performed. Always have an equivalent potential during diode operation. Through this process, a high energy N-type ion implantation layer and a second shallow PN junction are formed, and then the photoresist film (not shown) is removed.

According to the present invention as described above, the width of the channel stop region can be minimized to ensure the maximum photodiode region, and the depth thereof is substantially the same as the impurity region of the photodiode forming region, thereby reducing cross talk and dark current. It can be minimized to improve the operating characteristics of the image sensor, and the field insulating film forming process can be conceived through the embodiment that the process can be simplified.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the photodiode region can be maximized to improve light sensitivity, and by minimizing crosstalk and dark current of inter-pixel data, an excellent effect of ultimately improving the performance of an image sensor can be expected.

In addition, the present invention can omit the process of forming the field insulating film can simplify the process.

Claims (4)

CMOS image sensor, A first conductive semiconductor layer; A channel stop region of a first conductivity type disposed within the semiconductor layer at a first depth to serve as isolation between devices; A gate electrode disposed on the semiconductor layer; A first impurity region of a second conductive type for photodiode disposed in the semiconductor layer at a second depth substantially the same as the channel stop region and in contact with the gate electrode and the channel stop region; And A second impurity region of a first conductivity type for a photodiode disposed on the first impurity region and in contact with the surface of the semiconductor layer Image sensor comprising a. The method of claim 1, The first conductive type is a P-type, the second conductive type is an image sensor, characterized in that the N-type. In the image sensor manufacturing method, A first step of forming a channel stop region of a first conductive type for separating between devices at a first depth inside the semiconductor layer of the first conductive type through ion implantation; Forming a gate electrode on the semiconductor layer; Forming a second impurity region of a second conductivity type in contact with the channel stop region and the gate electrode at a second depth substantially equal to the channel stop region through ion implantation; And A fourth step of forming a second impurity region of a first conductivity type at an interface in contact with the semiconductor layer in the first impurity region Image sensor manufacturing method comprising a. The method of claim 3, wherein The first conductive type is a P-type, the second conductive type is an image sensor manufacturing method, characterized in that the N-type.