KR20030057677A - Image sensor with improved charge capacity and fabricating method of the same - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to be capable of increasing the charge capacity of a photodiode in a unit pixel. CONSTITUTION: The first impurity diffusion region(34) of the second conductive type is formed in a semiconductor layer(30) of the first conductive type. The second impurity diffusion region(36) of the first conductive type is formed between the first impurity diffusion region(34) and the surface of the semiconductor layer(30). An HSG(Hemispherical Silicon Grain) is formed on the second impurity diffusion region(36). Preferably, the first conductive type is a P-type and the second conductive type is an N-type.

Description

Image sensor with improved charge capacity and fabricating method of the same}

The present invention relates to an image sensor, and more particularly, to an image sensor and a method of manufacturing the same that can improve the charge capacity (charge capacity) of the photodiode.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. In a double charge coupled device (CCD), individual metal-oxide-silicon (MOS) capacitors are very different from each other. A device in which charge carriers are stored and transported in a capacitor while being located in close proximity, and CMOS (Complementary MOS) image sensor is a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. Is a device that employs a switching method that creates MOS transistors by the number of pixels and sequentially detects the output using them.

In manufacturing such various image sensors, efforts are being made to increase the photo sensitivity of the image sensor, and one of them is a light condensing technology. For example, a CMOS image sensor is composed of a photodiode for detecting light and a portion of a CMOS logic circuit for processing the detected light into an electrical signal to make data. To increase light sensitivity, the ratio of the photodiode to the total image sensor area is increased. Efforts have been made to increase (usually referred to as Fill Factor).

FIG. 1 is a unit pixel circuit diagram of a conventional CMOS image sensor, and a submicron CMOS Epi process is applied to increase sensitivity and reduce cross talk effects between unit pixels.

The unit pixel is composed of one low voltage buried photodiode and four NMOS transistors. Unlike the conventional photo gate structure, the low voltage buried photodiode has a polysilicon with a light sensing region. Not only is it covered, it has excellent light sensitivity for short wavelength blue light as well as increase the depth of depletion in the light sensing area, so the light sensitivity for long wavelength red or infrared light is also excellent. On the other hand, the low-voltage buried photodiode structure allows photogenerated charges in the photosensitive area to be completely transported to the Floating Sensing Node, which significantly increases the charge transfer efficiency. There are advantages to it.

In addition, the transfer gate (Tx), that is, the gate electrode and the reset gate (Rx), which transfer photocharges among the four transistors, is caused by a voltage drop due to a positive threshold voltage. In order to prevent the loss of charge transport efficiency, the NMOS transistor has a negative threshold voltage. In this case, the N-LDD ion implantation is omitted so that the overlap capacitance between the gate electrode and the reset gate and the floating sensing node is reduced. (Overlap Capacitance) can be lowered, so that the potential change of the floating sensing node can be amplified according to the amount of charge carried. (△ V-ΔQ / C)

Meanwhile, the drive gate (Sx) serving as a source follower is composed of a general submicron NMOS transistor. This structure was constructed with minimal changes to the submicron CMOS Epi process, and the thermal cycle was designed to be completely unchanged. On the other hand, a color filter array composed of red, green, blue, or yellow, magenta, cyan, and the like on a unit pixel array for implementing a color image. (Color Filter Array) The process of forming.

The operation principle of obtaining an output from such a unit pixel is as follows.

end. Turn off Tx, Rx, Sx. The low voltage buried photodiode is then fully depletion.

I. Photogenerated charge is collected in a low voltage buried photo diode.

All. After a proper integration time, the Rx is turned on to reset the floating sensing node first.

la. The unit pixel is turned on by turning on Sx.

hemp. Measure the output voltage (V1) of the source follower buffer. This value simply means the CD level shift of the Floating Sensing Node (FD).

bar. Turn on Tx.

four. All photogenerated charges are shipped in FD.

Ah. Turn off Tx.

character. Measure the output voltage (V2) of the source follower buffer.

car. The output signals V1-V2 are the result of the photocharge transport resulting from the difference between V1 and V2 and are pure signal values without noise. This method is called CDS (Corelated Double Sampling).

Ka. Repeat the process of 'a' to 'tea'. However, the low voltage buried photodiode is fully depleted during the 'dead' process.

2 is a cross-sectional view showing an image sensor according to the prior art.

Referring to FIG. 2, a P0 and an n- structure photodiode (hereinafter referred to as PD) are formed in the semiconductor layer 10 through a process such as ion implantation, and the data interference between neighboring PDs is prevented. A P-type channel stop region (hereinafter referred to as CST) is formed to prevent cross talk, and CST is typically formed under the field insulating film Fox through P-type impurity ion implantation. In addition, a transfer gate (hereinafter referred to as Tx) is formed on the semiconductor layer 10 in which one side is in contact with the PD, and an FD is formed in contact with the other side of the Tx.

Here, the semiconductor layer 10 includes a structure in which a high concentration of P ++ layer P-Epi layer is stacked or a P-well.

In other words, the photodiode of the image sensor described above plays a role of converting an external optical signal into an electrical signal, and the maximum charge capacity that can be accommodated in the photodiode itself is the size and junction of the photodiode itself. Related to ion implantation conditions. That is, since the semiconductor layer has a flat capacitor configuration, the area of the photodiode itself decreases proportionally as the size of the pixel decreases, so that the line width decreases, so that the basic dynamic area of the image sensor is reduced. There is a problem of reducing the range and deteriorating the saturation characteristic. In addition, there may be a method of tuning the ion implantation process for forming a photodiode to solve this problem, but it is different from other variables such as charge transfer efficiency and dark signal characteristics. Since the trade-off relationship, the limit is being revealed.

The present invention proposed to solve the above problems of the prior art, an object thereof is to provide an image sensor and a method of manufacturing the same that can increase the charge capacity of the photodiode in the unit pixel.

1 is a unit pixel circuit diagram of a conventional CMOS image sensor;

2 is a cross-sectional view showing an image sensor according to the prior art,

3A to 3C are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention;

Figure 4 is a schematic diagram showing the formation of hemispherical silicon grains of the present invention.

Explanation of symbols on the main parts of the drawings

30 semiconductor layer 31 field insulating film

32: gate insulating film 33: conductive electrode for gate electrode

34: n-region 35: spacer

36: P0 area 37: sensing diffusion area

39: Hemispherical Silicon Grain

In order to achieve the above object, the present invention, the first conductive semiconductor layer; A first impurity region for a photodiode of a second conductivity type formed in the semiconductor layer and extending from the surface of the semiconductor layer; A second impurity region for a photodiode of a first conductivity type formed on a surface of the semiconductor layer above the first impurity region; And a hemispherical silicon grain for photodiode formed on the second impurity region.

In addition, to achieve the above object, the present invention, forming a first impurity region for the photodiode of the second conductive type in the semiconductor layer of the first conductive type; Forming a second impurity region for a photodiode of a first conductivity type on a surface of the semiconductor layer above the first impurity region; And forming a hemispherical silicon grain on the surface of the semiconductor layer on the second impurity region.

The present invention is to improve the light sensitivity and saturation characteristics of the image sensor by forming a surface of the photodiode by forming a metastable polysilicon (MPS) or Hemispherical Silicom Glass (HSG) (HSG) used in the DRAM (Dynamic Random Access Memory), etc. It is a technical feature.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 3A to 3C are cross-sectional views illustrating an image sensor manufacturing process according to an embodiment of the present invention, and FIG. 3C shows an image sensor of the present invention, which is finally completed, and FIG. 4 shows a hemispherical silicon grain formation of the present invention. It is a schematic diagram showing.

Referring to FIG. 3C, the image sensor of the present invention includes a P-type semiconductor layer 30 in which a high concentration P ++ substrate and a P epi layer are stacked, a field insulating film 31 formed locally on the semiconductor layer 30, and a field. A gate electrode formed on the semiconductor layer 30 separated from the insulating film 31, and including a gate insulating film 32, a conductive film 33 for the gate electrode, and a spacer 35 formed on the sidewall thereof, for example, a transfer gate, and a gate. N-type impurity region 34 (hereinafter referred to as n-region) for a photodiode formed under the semiconductor layer 30 between the electrode and the field insulating film 31 and P formed on the surface of the semiconductor layer 30 above the n-region. Type impurity region 36 (hereinafter referred to as P0 region), hemispherical silicon grain 39 formed on P0 region 36, and a sensing diffusion region (hereinafter referred to as n + region) which is a high concentration N-type impurity region. It is configured by.

As described above, the present invention can increase the surface area of the photodiode to increase the charge capacity of the photodiode by forming the above-mentioned hemispherical silicon grain 39 on the photodiode upper surface.

Hereinafter, the manufacturing process of the above-described image sensor will be described later.

First, as shown in FIG. 3A, a field insulating film 31 having a shallow trench isolation (STI) or a LOCal oxide of silicon (LOCOS) structure is formed in a P-type semiconductor layer 30, where the semiconductor layer 30 is formed. Since the high concentration of the P + + layer and the P- epi layer is used as a stack, it is omitted for the sake of simplicity of the drawings.

Subsequently, a gate electrode including the gate insulating film 32 and the gate conductive film 33 is formed on the semiconductor layer 30, and then an ion implantation mask is formed. Subsequently, an n-region 34 for photodiode aligned with the gate electrode and in contact with the field insulating film 31 is formed using an ion implantation mask.

Subsequently, after removing the ion implantation mask (not shown), the ion implantation mask 38 for forming the P0 region is formed, and then the ion implantation mask 38 is used to implant n- by high concentration and low energy ion implantation. The P0 region 35 is formed in contact with the semiconductor layer 30 on the region 34.

Next, as shown in FIG. 3B, a hemispherical silicon grain 39 is formed on the surface of the semiconductor layer 30 on the exposed P0 region 36 using the P0 ion implantation mask 38.

Specifically, the hemispherical silicon grain 39, ie, MPS, is an attempt to secure a storage capacity by giving an unevenness to the surface of the charge storage to increase the effective area. When silicon is deposited in the system near 580 ° C, the polysilicon surface is deposited as hemispherical, commonly referred to as HSG. The temperature of 580 ° C. corresponds to a transition zone where the structure of the deposited silicon changes from amorphous to polycrystalline, which is a function of deposition parameters such as temperature and pressure and the flow rate of SiH ₄ . When the surface of the electrode is made of irregularities to increase the surface area, the electrode capacity can be increased by about twice that of the planarized electrode structure in DRAM or the like.

Referring to FIG. 4, as shown in FIG. 4A, nucleation of the silicon surface is performed. Subsequently, as shown in FIG. 4B, atoms having high mobility are atomized. (Nucleus) is raised to the surface, and then the nucleus is expanded to form grains as shown in (c) of FIG.

Next, as shown in FIG. 3C, the ion implantation mask 38 is removed, and a high concentration of the N-type sensing diffusion regions 37 and n + is formed.

The present invention described above has been found through the embodiment that the hemispherical silicon grains are formed on the PD to increase the surface area of the photodiode, thereby increasing the charge capacity of the photodiode and improving the light sensitivity and dynamic region.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can improve the light sensitivity and dynamic range of the photodiode by widening the surface area of the photodiode occupied in the unit pixel, and ultimately, an excellent effect of greatly improving the performance of the image sensor can be expected.

Claims (6)

In the image sensor, A first conductive semiconductor layer; A first impurity region for a photodiode of a second conductivity type formed in the semiconductor layer and extending from the surface of the semiconductor layer; A second impurity region for a photodiode of a first conductivity type formed on a surface of the semiconductor layer above the first impurity region; And Hemispherical silicon grain for photodiode formed on the second impurity region Image sensor comprising a. The method of claim 1, The semiconductor layer, A first conductive substrate; And Epi layer of the first conductivity type on the substrate Image sensor comprising a. The method according to claim 1 or 2, The first conductive type is a P-type, the second conductive type is an image sensor manufacturing method, characterized in that the N-type. Forming a first impurity region for a photodiode of the second conductivity type in the semiconductor layer of the first conductivity type; Forming a second impurity region for a photodiode of a first conductivity type on a surface of the semiconductor layer above the first impurity region; And Forming hemispherical silicon grain on the surface of the semiconductor layer on the second impurity region Image sensor manufacturing method comprising a. The method of claim 4, wherein And forming an ion implantation mask for forming the second impurity in the forming of the hemispherical silicon grains. The method of claim 4, wherein The first conductive type is a P-type, the second conductive type is an image sensor manufacturing method, characterized in that the N-type.