KR20030001752A - method for passvation of semiconductor device - Google Patents
method for passvation of semiconductor device Download PDFInfo
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- KR20030001752A KR20030001752A KR1020010037104A KR20010037104A KR20030001752A KR 20030001752 A KR20030001752 A KR 20030001752A KR 1020010037104 A KR1020010037104 A KR 1020010037104A KR 20010037104 A KR20010037104 A KR 20010037104A KR 20030001752 A KR20030001752 A KR 20030001752A
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- Prior art keywords
- insulating film
- film
- pad oxide
- cmp
- insulating
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 33
- 239000010410 layer Substances 0.000 description 12
- 238000000059 patterning Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 미세 패터닝이 가능하도록 하는데 적당한 반도체 소자의 평탄화 방법에 환한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a planarization method of a semiconductor device suitable for enabling fine patterning.
일반적으로 반도체 소자를 제조함에 있어 디자인 룰(design rule)이 감소함에 따라 미세 패터닝(patterning)이 요구되고 있다.In general, fine patterning is required as a design rule decreases in manufacturing a semiconductor device.
특히, 반도체 소자의 제조 공정에서 층(layer) 적층시 마다 발생하는 단차는패터닝을 어렵게 만들고 있으며 따라서 미세 패터닝을 가능하게 하기 위해서는 단차를 줄여야 한다.In particular, a step generated in each layer stacking in the manufacturing process of a semiconductor device makes patterning difficult, and thus, the step must be reduced in order to enable fine patterning.
종래의 반도체 소자의 평탄화 방법은 층간 절연을 위해 절연막을 증착 한 후 평탄화를 위해 화학적 기계적 연마 방식은 CMP(Chemical Mechanical Polishing) 공정을 진행하였다.In the conventional method of planarization of a semiconductor device, an insulating film is deposited for interlayer insulation, and then a chemical mechanical polishing (CMP) process is performed for planarization.
그 결과 절연막 증착후 발생한 활성 영역(action region)과 비활성 영역(field region) 사이의 단차를 줄일 수는 있지만 완전한 평탄화는 불가능하였다.As a result, the level difference between the active region and the inactive field region generated after the deposition of the insulating layer can be reduced, but the perfect planarization is impossible.
그러나 상기와 같은 종래의 반도체 소자의 평탄화 방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional planarization method of the semiconductor device as described above, there are the following problems.
즉, CMP 공정 후 여전히 존재하는 활성영역과 비활성영역 사이의 단차에 의해 포토(photo) 작업시 디포커스(defocus) 발생으로 인하여 미세 패터닝이 불완전하게 형성된다.That is, fine patterning is incompletely formed due to defocus during photo operation due to the step between the active and inactive regions still present after the CMP process.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 CMP로 제거되는 양이 서로 다른 두 절연막을 이용하여 활성영역과 비활성영역 사이의 단차를 제거함으로서 미세 패터닝이 가능하도록 한 반도체 소자의 평탄화 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The planarization of a semiconductor device enables fine patterning by removing a step between an active region and an inactive region by using two insulating films having different amounts of CMP. The purpose is to provide a method.
도 1a 내지 도 1f는 본 발명에 의한 반도체 소자의 평탄화 방법을 나타낸 공정단면도1A to 1F are process cross-sectional views showing a planarization method of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 패드 산화막21 semiconductor substrate 22 pad oxide film
23 : 질화막 24 : 트랜치23 nitride layer 24 trench
25 : 제 1 절연막 26 : 제 2 절연막25: first insulating film 26: second insulating film
27 : 제 3 절연막27: third insulating film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 평탄화 방법은 반도체 기판상에 패드 산화막과 질화막을 차례로 형성하고 포토 및 식각공정으로 선택적으로 제거하여 활성영역과 비활성영역을 정의하는 단계와, 상기 질화막 및 패드 산화막을 마스크로 이용하여 상기 노출된 반도체 기판을 선택적으로 제거하여 소정깊이를 갖는 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 반도체 기판의 전면에 CMP시 시간당 제거되는 양이 적은 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막상에 CMP시 시간당 제거되는 양이 많은 제 2 절연막과 시간당 제거되는 양이 적은 제 3 절연막을 차례로 형성하는 단계와, 상기 질화막의 표면이 노출되도록 전면에 CMP 공정을 실시하여 제 3, 제 2, 제 1 절연막을 선택적으로 제거하여 평탄화시키는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method of planarizing a semiconductor device, the method comprising: forming a pad oxide film and a nitride film sequentially on a semiconductor substrate and selectively removing the pad oxide film and the nitride film by photo and etching processes to define an active region and an inactive region; Selectively removing the exposed semiconductor substrate by using the nitride film and the pad oxide film as a mask to form a trench having a predetermined depth, and a first amount of the amount removed per hour during CMP on the entire surface of the semiconductor substrate including the trench; Forming an insulating film, sequentially forming a second insulating film having a large amount removed per hour upon CMP and a third insulating film having a small amount removed per hour on the first insulating film, and exposing a surface of the nitride film to the entire surface thereof; Performing a CMP process to selectively remove the third, second and first insulating films to planarize It is characterized by including the formation.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 평탄화 방법을 상세히 설명하면 다음과 같다.Hereinafter, a planarization method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명에 의한 반도체 소자의 평탄화 방법을 나타낸 공정단면도이다.1A to 1F are process cross-sectional views showing a planarization method of a semiconductor device according to the present invention.
도 1a에 도시한 바와 같이, 반도체 기판(21)상에 패드 산화막(22)과 질화막(23)을 차례로 형성한다.As shown in FIG. 1A, a pad oxide film 22 and a nitride film 23 are sequentially formed on the semiconductor substrate 21.
이어, 포토 및 식각 공정을 통해 활성영역과 비활성영역을 분리하기 위해 상기 질화막(23)과 패드 산화막(22)을 선택적으로 제거한다.Next, the nitride layer 23 and the pad oxide layer 22 are selectively removed to separate the active and inactive regions through photo and etching processes.
여기서 상기 패드 산화막(22) 및 질화막(23)이 잔존하는 영역이 활성영역이고, 상기 패드 산화막(22)과 질화막(23)이 제거되어 상기 반도체 기판(21)의 표면이 노출된 영역이 비활성영역이 된다.The area where the pad oxide film 22 and the nitride film 23 remain is an active region, and the area where the surface of the semiconductor substrate 21 is exposed by removing the pad oxide film 22 and the nitride film 23 is an inactive region. Becomes
그리고 상기 질화막(23) 및 패드 산화막(22)을 마스크로 이용하여 상기 노출된 반도체 기판(21)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(24)를 형성한다.The exposed semiconductor substrate 21 is selectively removed by using the nitride film 23 and the pad oxide film 22 as a mask to form a trench 24 having a predetermined depth.
도 1b에 도시한 바와 같이, 상기 트랜치(24)를 포함한 반도체 기판(21)의 전면에 매립 특성이 좋고 CMP시 시간당 제거되는 양이 적은 제 1 절연막(25)을 증착한다.As illustrated in FIG. 1B, a first insulating layer 25 having a good buried property and a small amount removed per hour during CMP is deposited on the entire surface of the semiconductor substrate 21 including the trench 24.
도 1c에 도시한 바와 같이, 상기 제 1 절연막(25)상에 CMP시 시간당 제거되는 양이 많은 제 2 절연막(26)과 시간당 제거되는 양이 적은 제 3 절연막(27)을 차례로 증착한다.As illustrated in FIG. 1C, a second insulating film 26 having a large amount removed per hour during CMP and a third insulating layer 27 having a small amount removed per hour are sequentially deposited on the first insulating layer 25.
여기서 상기 제 1 절연막(25)과 제 3 절연막(27)은 동일한 절연막이다.Here, the first insulating film 25 and the third insulating film 27 are the same insulating film.
도 1d에 도시한 바와 같이, 상기 제 2 절연막(26)의 표면이 노출되도록 상기 제 3 절연막(27)의 전면에 CMP 공정을 실시하여 활성영역과 비활성영역 사이에 발생하는 단차를 제거한다.As shown in FIG. 1D, a CMP process is performed on the entire surface of the third insulating layer 27 so that the surface of the second insulating layer 26 is exposed to remove the step generated between the active region and the inactive region.
즉, 상기 CMP공정은 활성영역의 CMP시 시간당 제거되는 양이 많은 제 2 절연막(26)의 표면이 노출될 때까지 진행하면 활성영역과 비활성영역의 단차로 인해 CMP 패드가 활성영역에 미치는 압력이 비활성영역에 미치는 압력보다 크므로 활성영역과 비활성영역 사이의 단차가 줄어들게 된다.That is, the CMP process proceeds until the surface of the second insulating film 26, which is largely removed per hour during the CMP of the active region, is exposed. Therefore, the pressure applied by the CMP pad to the active region is increased due to the step difference between the active and inactive regions. Since the pressure on the inactive zone is greater, the step between the active zone and the inactive zone is reduced.
도 1e에 도시한 바와 같이, 상기 CMP 공정을 계속 진행하면 활성영역에는 CMP시 시간당 제거되는 양이 많은 제 2 절연막(26)이 제거되는 동안 비활성영역에는 CMP시 시간당 제거되는 양이 적은 제 3, 제 1 절연막(27, 25)이 서서히 제거되어 활성영역과 비활성영역이 완전히 평탄화된다.As shown in FIG. 1E, when the CMP process is continued, the second insulating layer 26 having a large amount removed per hour during CMP is removed in the active region, and the third, The first insulating layers 27 and 25 are gradually removed to completely planarize the active region and the inactive region.
도 1f에 도시한 바와 같이, 상기 질화막(23)의 표면이 노출될 때까지 CMP 공정을 진행한다.As shown in FIG. 1F, the CMP process is performed until the surface of the nitride film 23 is exposed.
여기서 일단 평탄화가 되면 노출되는 박막은 CMP시 제거되는 양이 적은 박막 즉 제 1, 3 절연막(25,27)뿐으로 CMP 공정을 더 진행하더라도 비활성영역의 CMP시 제거되는 양이 많은 박막 즉, 제 2 절연막(26)이 완전히 제거될 때까지는 계속 평탄화가 유지된다.Here, once the planarization is performed, the exposed thin film is a thin film having a small amount removed during CMP, that is, a thin film having a large amount removed during CMP in the inactive region even if the CMP process is further performed. The planarization is continued until the insulating film 26 is completely removed.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 평탄화 방법은 다음과 같은 효과가 있다.As described above, the planarization method of the semiconductor device according to the present invention has the following effects.
즉, 활성영역과 비활성영역 사이의 층간 발생하는 단차를 완전히 제거함으로서 완전 평탄화가 진행된 상태에서 포토 작업을 하게 되어 포토 작업시 디포커스 발생율이 작아 미세 패터닝을 안정적으로 형성할 수 있다.That is, by completely removing the step difference between the active area and the inactive area, the photo work is performed in the state of complete planarization, so that the defocus occurrence rate during the photo work is small, so that fine patterning can be stably formed.
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| KR200449709Y1 (en) * | 2008-11-06 | 2010-08-03 | 주식회사 아이레보 | Door Lock Device for Preventing Wear of Deadbolt Moving Gear |
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| KR970003629A (en) * | 1995-06-28 | 1997-01-28 | 김주용 | Planarization method of semiconductor device |
| KR20000042482A (en) * | 1998-12-24 | 2000-07-15 | 김영환 | Method for planarizing semiconductor device |
| KR20000043236A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Method for flattening interlayer dielectrics |
| KR100373355B1 (en) * | 1999-06-28 | 2003-02-25 | 주식회사 하이닉스반도체 | Planarization of semiconductor device |
| JP3539483B2 (en) * | 1999-09-28 | 2004-07-07 | シャープ株式会社 | Method for manufacturing semiconductor device |
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