KR20030000957A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20030000957A KR20030000957A KR1020010037233A KR20010037233A KR20030000957A KR 20030000957 A KR20030000957 A KR 20030000957A KR 1020010037233 A KR1020010037233 A KR 1020010037233A KR 20010037233 A KR20010037233 A KR 20010037233A KR 20030000957 A KR20030000957 A KR 20030000957A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000000969 carrier Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 원칩상에 형성되는 트랜지스터의 스페이서 길이를 서로 다르게 하여 게이트의 크기를 동일하게 유지하면서 전류구동능력을 다르게 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having different current driving capabilities while maintaining the same gate size by different spacer lengths of transistors formed on one chip. will be.
FET(Field-Effect Transistor; 전계효과 트랜지스터)는 다수 캐리어가 반도체 표면을 따라서 드리프트 하는 것을 게이트 전계에 의해 제어하는 방식의 트랜지스터를 말하는 것으로서 소수캐리어의 주입이 없으므로 축적효과에 의한 응답 속도의 저하가 없고, 잡음이 적은 장점이 있다.FET (Field-Effect Transistor) refers to a transistor in which a majority of carriers drift along the semiconductor surface by a gate electric field. Since there is no injection of minority carriers, there is no degradation in response speed due to an accumulation effect. This has the advantage of low noise.
위와 같은 FET를 사용하는 반도체 소자의 경우, 소자 구동시 역할에 따라 구동전류가 달라질 수 있기 때문에 구동전류를 다르게 하려면 소자의 크기에 차이를 두거나 소자에 전압을 다르게 전달해야 한다. 그리고 또 하나의 방법은 게이트산화막의 두께를 다르게 만드는 방법이다.In the case of the semiconductor device using the FET as described above, the driving current may vary depending on the role of the device driving, so to change the driving current, the size of the device or the voltage must be transferred to the device. Another method is to make the thickness of the gate oxide film different.
예를 들어, 메모리셀 어레이와 제어회로가 원칩으로 형성된 MML(Merged Memory Logic) 소자는 크기가 같아도 각 부분에 따라 구동전류가 다르게 된다.For example, an MML device in which a memory cell array and a control circuit are formed in one chip has a different driving current according to each part even though the size is the same.
또한, SRAM의 데이터 안정성은 드라이버 트랜지스터의 전류 구동능력에 의해 좌우되며 충분한 안정성을 확보하기 위해서는 드라이버 트랜지스터의 전류 구동능력이 억세스 트랜지스터의 전류 구동능력에 비해 대략 2배이상 큰 것을 바람직한 것으로 보고 있다.In addition, the data stability of the SRAM depends on the current driving capability of the driver transistor, and in order to secure sufficient stability, it is considered that the current driving capability of the driver transistor is approximately two times larger than the current driving capability of the access transistor.
그래서 제어회로와 메모리셀 어레이를 원칩으로 제조할 때 이와 같은 조건들을 확보하기 위해서 소자의 크기를 바꾸는 방법으로 길이를 줄이는 방법을 사용하는데 이는 공정상 한계를 가지고 있으며, 폭을 늘이는 것을 셀의 면적이 커지는 문제점이 있다.Therefore, when manufacturing the control circuit and the memory cell array in one chip, in order to secure such conditions, the method of reducing the length is used by changing the size of the device, which has a limitation in the process. There is a growing problem.
따라서, 셀 면적을 유지하면서 전류구동 능력을 줄이는 방법은 콘택과 액티브 영역과의 오버랩이 있으나 절연 공간을 줄이기 때문에 공정 마진의 부족으로 높은 수율을 얻기 어려운 문제점이 있다.Therefore, the method of reducing the current driving capability while maintaining the cell area has an overlap between the contact and the active region, but there is a problem in that it is difficult to obtain a high yield due to the lack of process margin because the insulation space is reduced.
그리고, 롬코딩의 경우 대부분의 롬코딩 공정이 폴리게이트를 형성하기 전에 이루어지기 때문에 고객이 원하는 TAT를 맞추어 제공하기 어려운 문제점이 있다.And, in the case of romcoding, since most of the romcoding processes are performed before forming the polygate, it is difficult to provide the TAT desired by the customer.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 원칩상에 형성되는 트랜지스터의 스페이서 길이를 서로 다르게 하여 게이트의 크기를 동일하게 유지하면서 전류구동능력을 다르게 함으로써 데이터의 안정성을 확보할 수 있도록 한 반도체소자의 제조방법을 제공함에 있다.The present invention has been made to solve the above problems, and an object of the present invention is to ensure the stability of data by varying the current driving capability while maintaining the same gate size by different spacer lengths of transistors formed on one chip. To provide a method for manufacturing a semiconductor device to ensure the.
또한, 본 발명의 목적은 트랜지스터의 스페이서 길이에 의한 전류구동능력을 비교하여 롬코딩을 구현할 뿐만 아니라 롬코딩을 폴리게이트 형성이후로 옮겨 고객이 원하는 롬칩을 제공할 수 있도록 한 반도체소자의 제조방법을 제공함에 있다.In addition, an object of the present invention is to provide a method for manufacturing a semiconductor device by comparing the current driving ability of the transistors to the current driving capability to implement the rom coding as well as to transfer the rom coding after forming the polygate to provide the desired rom chip. In providing.
도 1내지 도 3은 본 발명에 의한 반도체소자의 제조방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 반도체 기판 20 : 소자격리막10 semiconductor substrate 20 device isolation film
30 : 게이트 35 : 게이트산화막30 gate 35 gate oxide film
40 : 제 1스페이서 50 : 감광막40: first spacer 50: photosensitive film
60 : 제 2스페이서 70 : 소오스/드레인 접합 영역60 second spacer 70 source / drain junction region
100 : 낮은 전류 구동능력을 원하는 트랜지스터 영역100: transistor area for low current driving capability
200 : 높은 전류 구동능력을 원하는 트랜지스터 영역200: transistor region for high current driving capability
상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판 상에 게이트를 형성한 후 LDD 이온주입 및 제 1스페이서를 형성하는 단계와, 제 1스페이서를 형성한 후 전면에 감광막을 도포한 후 높은 전류 구동능력을 원하는 트랜지스터 영역의 감광막을 제거하는 단계와, 감광막을 제거한 후 식각하여 높은 전류 구동능력을 원하는 트랜지스터 영역의 제 1스페이서를 제거하고 감광막을 제거하는 단계와, 감광막을 제거한 결과물 전면에 제 2스페이서 산화막을 증착하는 단계와, 제 2스페이서 산화막을 증착한 후 전면 식각하여 제 2스페이서를 형성하는 단게와, 제 2스페이서를 형성한 후 소오스/드레인 이온주입을 수행하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for realizing the above object is a step of forming a gate on a semiconductor substrate and then implanting the LDD ion implantation and the first spacer, and after forming the first spacer after applying a photosensitive film on the front, high current driving Removing the photoresist film of the transistor region for which the capability is desired, removing the photoresist, and etching the first spacer of the transistor region for high current driving capability and removing the photoresist, and removing the photoresist; And depositing an oxide film, forming a second spacer by etching the entire surface after depositing the second spacer oxide, and performing source / drain ion implantation after forming the second spacer. do.
위와 같은 방법에 의해 낮은 전류 구동능력을 원하는 트랜지스터 영역의 스페이서는 제 1스페이서와 제 2스페이서로 형성되고, 높은 전류 구동능력을 원하는 트랜지스터 영역의 스페이서는 제 2스페이서로만 형성된다.By the above method, the spacer of the transistor region which desires low current driving capability is formed of the first spacer and the second spacer, and the spacer of the transistor region which desires high current driving capability is formed of only the second spacer.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.
도 1내지 도 3은 본 발명에 의한 반도체소자의 제조방법을 설명하기 위한 단면도들이다.1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 1에 도시된 바와 같이 일반적인 방법에 의해 반도체 기판(10) 상에 소자격리막(20)을 형성하고, 게이트산화막(35)을 증착하고 게이트(30)를 패턴닝한 후 LDD 이온주입을 수행한 후 제 1스페이서 산화막(미도시)을 증착한 후 전면 식각하여 높은 전류 구동능력을 원하는 트랜지스터 영역(200)이나 낮은 전류 구동능력을 원하는 트랜지스터 영역(100)이나 모두 동일하게 제 1스페이서(40)를 형성한다.As shown in FIG. 1, the device isolation layer 20 is formed on the semiconductor substrate 10 by the general method, the gate oxide layer 35 is deposited, the gate 30 is patterned, and LDD ion implantation is performed. After the deposition of the first spacer oxide film (not shown), the entire surface is etched and then the first spacer 40 is identically formed in the transistor region 200 for high current driving capability or the transistor region 100 for low current driving capability. Form.
그런다음, 전면에 감광막(50)을 도포한 후 높은 전류 구동능력을 원하는 트랜지스터 영역(200)의 감광막(50)을 제거한다.Then, after the photosensitive film 50 is applied to the entire surface, the photosensitive film 50 of the transistor region 200 for which the high current driving capability is desired is removed.
그런다음 도 2에 도시된 바와 같이 감광막(40)을 마스크로 습식식각을 수행하여 높은 전류 구동능력을 원하는 트랜지스터 영역(200)의 제 1스페이서(40)를 제거한다.Then, as shown in FIG. 2, wet etching is performed using the photoresist film 40 as a mask to remove the first spacer 40 of the transistor region 200 that desires high current driving capability.
그런다음, 감광막(50)을 제거하고 결과물 전면에 제 2스페이서 산화막(미도시)을 증착한 후 전면 식각하여 높은 전류 구동능력을 원하는 트랜지스터 영역(200)과 낮은 전류 구동능력을 원하는 트랜지스터 영역(100) 모두에 제 2스페이서(60)를 형성한다.Thereafter, the photoresist film 50 is removed, and a second spacer oxide film (not shown) is deposited on the entire surface of the resultant, and then etched to the entire surface to form a transistor region 200 for high current driving capability and a transistor region 100 for low current driving capability. The second spacer 60 is formed in all of the lines.
그런다음 도 3에 도시된 바와 같이 제 2스페이서(60)를 형성한 후 소오스/드레인 접합 영역(70)을 형성하기 위한 고농도 이온주입공정을 실시한다.Then, as shown in FIG. 3, after forming the second spacer 60, a high concentration ion implantation process for forming the source / drain junction region 70 is performed.
따라서, 낮은 전류 구동능력을 원하는 트랜지스터 영역(100)에는 제 1스페이서(40)와 제 2스페이서(60)에 의해 스페이서의 길이가 길게 되고, 높은 전류 구동능력을 원하는 트랜지스터 영역(200)에는 제 2스페이서(60) 만이 형성되어 낮은 전류 구동능력을 원하는 트랜지스터 영역(100)의 스페이서 보다 상대적으로 스페이서의 길이가 짧게 형성된다.Accordingly, the length of the spacers is increased by the first spacer 40 and the second spacer 60 in the transistor region 100 that desires low current driving capability, and the second region of the transistor region 200 that desires high current driving capability. Only the spacer 60 is formed so that the length of the spacer is shorter than the spacer of the transistor region 100 for which low current driving capability is desired.
상기한 바와 같이 본 발명은 원칩상에 형성되는 트랜지스터의 스페이서 길이를 서로 다르게 하여 게이트의 크기를 동일하게 유지하면서 전류구동능력을 다르게함으로써 데이터의 안정성을 확보할 수 있는 이점이 있다.As described above, the present invention has an advantage of ensuring the stability of data by varying the current driving capability while maintaining the same gate size by different spacer lengths of transistors formed on one chip.
또한, 트랜지스터의 스페이서 길이에 의한 전류구동능력을 비교하여 롬코딩을 구현할 수 있어 1회의 마스크 공정과 1회의 식각공정의 최소공정으로 인해 경쟁력을 확보할 수 있는 이점이 있다.In addition, rom coding can be implemented by comparing the current driving capability of the transistors with the spacer length, and thus, there is an advantage of securing the competitiveness due to the minimum process of one mask process and one etching process.
또한, 롬코딩 단계를 게이트 형성 이후로 옮겨 고객이 원하는 롬칩을 빠른 시간 내에 제공할 수 있는 이점이 있다.In addition, there is an advantage that the ROM coding step can be moved after the gate formation to provide the ROM chip desired by the customer in a short time.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2009031860A3 (en) * | 2007-09-06 | 2009-04-30 | Microinfinity Inc | Control apparatus and method |
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2001
- 2001-06-27 KR KR1020010037233A patent/KR20030000957A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009031860A3 (en) * | 2007-09-06 | 2009-04-30 | Microinfinity Inc | Control apparatus and method |
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