KR20030000137A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20030000137A KR20030000137A KR1020010035797A KR20010035797A KR20030000137A KR 20030000137 A KR20030000137 A KR 20030000137A KR 1020010035797 A KR1020010035797 A KR 1020010035797A KR 20010035797 A KR20010035797 A KR 20010035797A KR 20030000137 A KR20030000137 A KR 20030000137A
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- Prior art keywords
- photoresist layer
- layer pattern
- photoresist pattern
- forming
- polymer solution
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000003999 initiator Substances 0.000 claims abstract description 13
- 229920003169 water-soluble polymer Polymers 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims description 18
- OZAIFHULBGXAKX-UHFFFAOYSA-N 2-(2-cyanopropan-2-yldiazenyl)-2-methylpropanenitrile Chemical group N#CC(C)(C)N=NC(C)(C)C#N OZAIFHULBGXAKX-UHFFFAOYSA-N 0.000 claims description 6
- OZAIFHULBGXAKX-VAWYXSNFSA-N AIBN Substances N#CC(C)(C)\N=N\C(C)(C)C#N OZAIFHULBGXAKX-VAWYXSNFSA-N 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 abstract description 8
- 230000009977 dual effect Effects 0.000 abstract description 6
- 239000010949 copper Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000000463 material Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 자기 정렬 듀얼 다마신 공정에서 감광막 패턴 상부에 라디칼 개시제(radical initiator)를 포함하는 고분자용액을 도포한 후 베이크(bake) 공정을 실시하여 식각 내성이 향상된 감광막패턴을 형성하는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, by applying a polymer solution containing a radical initiator on the photoresist pattern in a self-aligned dual damascene process and then performing a bake process. A method of manufacturing a semiconductor device for forming a photoresist pattern having improved resistance.
집적회로에서 소자와의 접촉, 소자간의 연결, 칩과 외부회로와의 연결기능을갖는 금속배선을 형성시키는 공정은 반도체소자의 동작 속도 및 신뢰성에 큰 영향을 미친다.In an integrated circuit, a process of forming a metal wiring having a function of contacting devices, connecting devices, and connecting a chip and an external circuit has a great influence on the operation speed and reliability of a semiconductor device.
최근 들어 반도체 제조 기술의 발전과 더불어 금속배선 공정에 있어서 미세화로 인하여 소자의 크기가 감소되고 있다. 그리고, 이에 대응하는 전기적 성능 및 신뢰성을 갖는 금속배선재료 및 공정 기술에 대한 요구가 증대하고 있다. 현재 금속배선재료로서 알루미늄을 주원료로 하는 합금 또는 구리가 사용되고 있거나 연구 중에 있다. 또한, 스텝 커버리지(step coverage) 특성이 우수한 MOCVD(metal organic chemical vapor deposition)법에 대한 연구가 활발히 이루어지고 있다.Recently, with the development of semiconductor manufacturing technology, the size of devices has been reduced due to miniaturization in the metallization process. In addition, there is an increasing demand for metallization materials and process technologies having corresponding electrical performance and reliability. Currently, alloys or copper based on aluminum are used or are being studied as metal wiring materials. In addition, research on the metal organic chemical vapor deposition (MOCVD) method having excellent step coverage characteristics has been actively conducted.
지금까지 반도체 회로의 금속배선 재료는 주로 알루미늄 소재를 사용해 왔다. 그러나, 상기 알루미늄은 기가 DRAM(giga DRAM) 이상에서 사용하기에는 저항이 높고 선폭(line width)을 줄이는데 한계가 있다. 이를 해결하기 위하여 기판 표면의 산소와 질소 성분의 함량을 낮추고, 플라즈마 전처리 공정을 실시하여 초전도성을 갖는 구리의 증착 속도를 크게 개선하였다.Until now, the metal wiring material of semiconductor circuits has mainly used aluminum. However, the aluminum is high in resistance to use over giga DRAMs and has a limitation in reducing line width. In order to solve this problem, the oxygen and nitrogen components on the surface of the substrate were lowered, and a plasma pretreatment process was performed to greatly improve the deposition rate of copper having superconductivity.
그러나, 상기 구리는 식각하기 어려운 단점이 있다. 이를 해결하기 위하여 구리배선으로 예정되는 부분의 층간절연막을 식각하여 트렌치(trench)를 형성하고, 구리막을 매립한 다음, 상기 구리막을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)방법으로 평탄화시켜 구리배선을 형성하는 다마신(damascene) 방법을 사용하였다.However, the copper has a disadvantage of being difficult to etch. In order to solve this problem, a trench is formed by etching the interlayer insulating film, which is supposed to be a copper wiring, and the copper film is embedded, and then the copper film is planarized by chemical mechanical polishing (hereinafter referred to as CMP). The damascene method of forming copper wiring was used.
또한, 초기의 다마신공정에서는 절연물질로 플루오르 실리카 유리물질 및SiLK 반도체 절연체 등의 SiO2막이 사용되었다.In the initial damascene process, SiO 2 films such as fluorine silica glass material and SiLK semiconductor insulator were used as the insulating material.
그러나, RC 지연(delay)으로 인한 반도체소자의 동작 속도를 향상시키기 위해 Cu막과 저유전 물질에 대한 연구가 활발히 진행되고 있다. 특히, R값의 감소를 위하여 구리막을 사용하고, C값을 감소시키기 위하여 저유전 물질을 사용하고 있다.However, in order to improve the operation speed of semiconductor devices due to RC delay, studies on Cu films and low dielectric materials have been actively conducted. In particular, a copper film is used to reduce the R value, and a low dielectric material is used to reduce the C value.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 리소그래피 측면에서 보면 이러한 듀얼 다마신공정의 경우 비아콘택홀과 금속배선 패턴을 모두 절연막 위에 형성한 후 구리막의 증착을 수행하기 때문에 중첩(overlay) 등의 문제가 비교적 쉬운 실정이다. 그러나, 비아콘택홀 패턴과 금속배선 패턴에서 어쩔 수 없이 발생하게 되는 미스얼라인먼트(misalignment)가 구리막 증착 공정 시 보이드(void) 발생의 원인으로 작용할 수밖에 없고, 이러한 보이드 발생은 비아콘택 저항 특성을 저하시키는 문제점이 있다. 이를 해결하기 위하여 질화막 등을 하드마스크로 이용한 자기 정렬 듀얼 다마신(self aligned dual damascene)공정이 사용되고 있지만, 이러한 자기 정렬 듀얼 다마신공정의 경우 공정이 복잡해지고, 유전 상수(dielectric constant)가 큰 질화막 등의 물질을 하드마스크로 사용하기 때문에 소자의 동작 속도를 감소시키는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the related art, in the dual damascene process, since the via contact hole and the metal wiring pattern are both formed on the insulating film and then the copper film is deposited, the overlay is performed. The problem is relatively easy. However, misalignment, which is inevitably generated in the via contact hole pattern and the metal wiring pattern, may cause voids in the copper film deposition process, and the void generation may lower the via contact resistance characteristics. There is a problem. In order to solve this problem, a self aligned dual damascene process using a nitride film or the like as a hard mask is used. Since the material of the hard mask is used, there is a problem of reducing the operation speed of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하부 금속배선을 형성하고, 전체표면 상부에 층간절연막을 형성한 다음, 상기 층간절연막 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막패턴을 형성한 후, 상기 제1감광막패턴을 라디칼 개시제(radical initiator)를 함유한 수용성 고분자 용액에 의해 가교시켜 경화시킨 후 그 상부에 상부 금속배선으로 예정되는 부분을 노출시키는 제2감광막패턴을 형성함으로써 상기 제1감광막패턴과 제2감광막패턴을 식각마스크로 사용하는 자기 정렬 듀얼 다마신 공정을 용이하게 할 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention provides a first photoresist pattern for forming a lower metal interconnection, forming an interlayer insulating film on the entire surface, and exposing a portion intended as a via contact on the interlayer insulating film. After forming the cross-linking of the first photoresist pattern with a water-soluble polymer solution containing a radical initiator (curable), by forming a second photoresist pattern for exposing a portion of the upper portion of the metal wiring to the upper portion An object of the present invention is to provide a method for fabricating a semiconductor device which can facilitate a self-aligned dual damascene process using the first photoresist pattern and the second photoresist pattern as an etching mask.
도 1 내지 도 8 은 본 발명에 따른 반도체소자의 제조방법을 도시하는 공정 단면도.1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 반도체기판 11 : 제1층간절연막10 semiconductor substrate 11: first interlayer insulating film
13 : 하부금속배선 15 : 제2층간절연막13: lower metal wiring 15: second interlayer insulating film
17 : 제1감광막패턴 19 : 고분자용액17: first photosensitive film pattern 19: polymer solution
20 : 경화된 제1차감광막패턴 21 : 제2감광막패턴20: cured first photosensitive film pattern 21: second photosensitive film pattern
23 : 비아콘택홀 25 : 트렌치23: via contact hole 25: trench
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,
반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate;
상기 제1층간절연막 상부에 하부 금속배선을 형성하는 공정과,Forming a lower metal wiring on the first interlayer insulating film;
전체표면 상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
상기 제2층간절연막 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막패턴을 형성하는 공정과,Forming a first photoresist pattern on the second interlayer insulating layer, the first photoresist layer pattern exposing a portion intended as a via contact;
전체표면 상부에 라디칼 개시제를 함유하는 수용성 고분자 용액을 도포하는 공정과,Applying a water-soluble polymer solution containing a radical initiator over the entire surface,
상기 수용성 고분자용액 내의 라디칼 개시제를 상기 제1감광막패턴으로 확산시키는 베이크공정과,A baking step of diffusing the radical initiator in the water-soluble polymer solution into the first photoresist film pattern;
상기 수용성 고분자용액을 제거하는 공정과,Removing the water-soluble polymer solution;
전체표면 상부에 상부 금속배선으로 예정되는 부분을 노출시키는 제2감광막패턴을 형성하는 공정과,Forming a second photoresist film pattern exposing a portion, which is intended as an upper metal wiring, over the entire surface;
상기 제1감광막패턴과 제2감광막패턴을 식각마스크로 상기 제2층간절연막을 식각하여 비아콘택홀을 형성하는 공정과,Forming a via contact hole by etching the second interlayer insulating layer using the first photoresist pattern and the second photoresist pattern as an etching mask;
상기 제2감광막패턴을 식각마스크로 상기 제1감광막패턴을 식각하는 공정과,Etching the first photoresist pattern using the second photoresist pattern as an etching mask;
상기 제2감광막패턴을 제거하는 공정과,Removing the second photoresist pattern;
상기 제1감광막패턴을 식각마스크로 상기 제2층간절연막을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the second interlayer dielectric layer using the first photoresist pattern as an etch mask;
상기 제1감광막패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the first photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 8 는 본 발명에 따른 반도체소자의 제조방법을 도시하는 공정 단면도이다.1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(10) 상부에 제1층간절연막(11)을 형성한다.First, a first interlayer insulating film 11 is formed on the semiconductor substrate 10.
다음, 상기 제1층간절연막(11) 상부에 하부금속배선(13)을 형성한다.Next, a lower metal wiring 13 is formed on the first interlayer insulating film 11.
그 다음, 전체표면 상부에 제2층간절연막(15)을 형성한다.Next, a second interlayer insulating film 15 is formed over the entire surface.
다음, 상기 제2층간절연막(15) 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막패턴(17)을 형성한다. (도 1 참조)Next, a first photoresist pattern 17 is formed on the second interlayer insulating layer 15 to expose a portion of the via contact. (See Figure 1)
그 다음, 전체표면 상부에 라디칼 개시제가 함유되어 있는 고분자 용액(19)을 도포한다. 이때, 상기 고분자용액(19)은 사진식각공정에서 일반적으로 사용되는 탑 ARC(top anti reflecting coating)막과 비슷한 수용성(water soluble) 고분자용액이고, 용매는 물이다. 그리고, 상기 라디칼 개시제로 사용되는 물질은 AIBN(2,2'-Azobisisobutyronitrile)이다. (도 2 참조)Next, a polymer solution 19 containing a radical initiator is applied over the entire surface. In this case, the polymer solution 19 is a water soluble polymer solution similar to the top anti reflecting coating (ARC) film commonly used in the photolithography process, and the solvent is water. In addition, the material used as the radical initiator is AIBN (2,2'-Azobisisobutyronitrile). (See Figure 2)
그 다음, 상기 구조를 베이크한다. 상기 베이크공정으로 생성된 라디칼을 상기 제1감광막패턴(17)으로 확산시켜 경화시킨다. 이때, 상기 베이크공정은 오븐 또는 핫 플레이트 가열방식으로 실시되고, 상기 오븐 또는 핫 플레이트의 온도는 50 - 250℃이다.The structure is then baked. Radicals generated by the baking process are diffused into the first photoresist layer pattern 17 to be cured. At this time, the baking process is carried out by the oven or hot plate heating method, the temperature of the oven or hot plate is 50-250 ℃.
상기 베이크공정으로 경화된 제1감광막패턴(20)은 후속공정으로 형성되는 제2감광막패턴에 대하여 저항력을 갖는다.The first photoresist pattern 20 cured by the baking process has a resistance to the second photoresist pattern formed by a subsequent process.
다음, 상기 고분자용액(19)을 제거한다. (도 3 참조)Next, the polymer solution 19 is removed. (See Figure 3)
그 다음, 전체표면 상부에 상부금속배선으로 예정되는 부분을 노출시키는 제2감광막패턴(21)을 형성한다. 이때, 상기 제2감광막패턴(21)은 실리콘을 함유하고 있다. (도 4 참조)Next, a second photoresist pattern 21 is formed on the entire surface to expose a portion of the upper metal wiring. In this case, the second photoresist pattern 21 contains silicon. (See Figure 4)
다음, 상기 경화된 제1감광막패턴(20)과 제2감광막패턴(21)을 식각마스크로 상기 제2층간절연막(15)을 식각하여 비아콘택홀(23)을 형성한다. 이때, 상기 식각공정 시 상기 제2감광막패턴(21)이 일부 제거되면서 플라즈마 에천트로 인해 표면이 실리콘 산화막으로 변하게 된다. 이후 O2플라즈마를 이용한 식각공정을 거치면 실리콘을 함유하지 않는 상기 경화된 제1감광막패턴(20)이 제거된다. (도 5, 도 6 참조)Next, the via contact hole 23 is formed by etching the second interlayer insulating layer 15 using the cured first photoresist pattern 20 and the second photoresist pattern 21 as an etching mask. In this case, a portion of the second photoresist layer pattern 21 is removed during the etching process, thereby changing the surface into a silicon oxide layer due to plasma etchant. After the etching process using O 2 plasma, the cured first photoresist pattern 20 containing no silicon is removed. (See Figs. 5 and 6)
그 다음, 상기 제2감광막패턴(21)을 식각마스크로 상기 제2층간절연막(15)을 식각하여 트렌치(25)를 형성한다. 상기 식각공정 후 상기 제2감광막패턴(21)이 손실되고, 경화된 제1감광막패턴(20)만 남게 된다. 된다. (도 7 참조)Next, the second interlayer insulating layer 15 is etched using the second photoresist pattern 21 as an etch mask to form a trench 25. After the etching process, the second photoresist pattern 21 is lost and only the hardened first photoresist pattern 20 remains. do. (See Figure 7)
다음, 상기 경화된 제1감광막패턴(20)을 제거한다. (도 8 참조)Next, the cured first photoresist pattern 20 is removed. (See Figure 8)
그 후, 후속공정을 실시하여 상기 트렌치(25) 및 비아콘택홀(23)을 통하여 상기 하부금속배선(13)에 접속되는 비아콘택플러그 및 상부금속배선을 형성한다.Subsequently, a subsequent process is performed to form a via contact plug and an upper metal wiring connected to the lower metal wiring 13 through the trench 25 and the via contact hole 23.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 구리배선 제조방법은, 자기 정렬 듀얼 다마신(self aligned dual damascene)공정을 진행하는 경우, 반도체기판 상부에 하부금속배선을 형성하고, 전체표면 상부에 층간절연막을 형성한 다음, 상기 층간절연막 상부에 비아콘택으로 예정되는 부분을 노출시키는 제1감광막패턴을 형성하고, 전체표면 상부에 라디칼 개시제(radical initiator)를 함유하는 고분자용액을 도포한 후 베이크공정을 실시하여 상기 고분자용액 내의 라디칼을 생성시켜 상기 제1감광막패턴에 확산시켜 경화시킴으로써 상기 제1감광막패턴이 후속공정으로 형성되는 상부금속배선으로 예정되는 부분을 노출시키는 제2감광막패턴에 대한 식각내성을 갖도록 하여 공정을 단순하게 하고 그로 인하여 안정적으로 공정을 조절하고 그에 따른 소자의 공정 수율 및 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a copper wiring of a semiconductor device according to the present invention, when a self aligned dual damascene process is performed, a lower metal wiring is formed on an upper surface of a semiconductor substrate, and an upper surface of the entire surface is formed. After forming the interlayer dielectric layer, a first photoresist layer pattern is formed on the interlayer dielectric layer to expose a predetermined portion as a via contact, and a polymer solution containing a radical initiator is applied on the entire surface, followed by baking. Etching to generate a radical in the polymer solution, diffuse the first photoresist pattern, and harden it by exposing the first photoresist pattern to a portion of the second photoresist pattern in which the first photoresist pattern is formed by a subsequent metal wiring. To simplify the process and thereby stably control the process and There is an advantage that can improve the process yield and reliability of the device.
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| US9502639B2 (en) | 2013-09-30 | 2016-11-22 | SK Hynix Inc. | Electronic device for improving characteristic of variable resistance element and method of fabricating the same |
| KR20170015790A (en) * | 2015-07-31 | 2017-02-09 | 삼성전자주식회사 | Methods of manufacturing interconnects for semiconductor devices |
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| US9865319B2 (en) | 2014-12-17 | 2018-01-09 | SK Hynix Inc. | Electronic device and method for fabricating the same |
| US10205089B2 (en) | 2014-02-28 | 2019-02-12 | SK Hynix Inc. | Electronic device and method for fabricating the same |
| US10367137B2 (en) | 2014-12-17 | 2019-07-30 | SK Hynix Inc. | Electronic device including a semiconductor memory having a variable resistance element including two free layers |
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2001
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| US9865806B2 (en) | 2013-06-05 | 2018-01-09 | SK Hynix Inc. | Electronic device and method for fabricating the same |
| US8959250B2 (en) | 2013-06-05 | 2015-02-17 | SK Hynix Inc. | Electronic device and method for fabricating the same |
| US10490741B2 (en) | 2013-06-05 | 2019-11-26 | SK Hynix Inc. | Electronic device and method for fabricating the same |
| US10777742B2 (en) | 2013-06-05 | 2020-09-15 | SK Hynix Inc. | Electronic device and method for fabricating the same |
| US9502639B2 (en) | 2013-09-30 | 2016-11-22 | SK Hynix Inc. | Electronic device for improving characteristic of variable resistance element and method of fabricating the same |
| US10205089B2 (en) | 2014-02-28 | 2019-02-12 | SK Hynix Inc. | Electronic device and method for fabricating the same |
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| US10367137B2 (en) | 2014-12-17 | 2019-07-30 | SK Hynix Inc. | Electronic device including a semiconductor memory having a variable resistance element including two free layers |
| US9859490B2 (en) | 2015-04-14 | 2018-01-02 | SK Hynix Inc. | Electronic device including a semiconductor memory having multi-layered structural free layer |
| KR20170015790A (en) * | 2015-07-31 | 2017-02-09 | 삼성전자주식회사 | Methods of manufacturing interconnects for semiconductor devices |
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