KR20030054175A - A method for manufacturing semiconductor device using dual damascene process - Google Patents

A method for manufacturing semiconductor device using dual damascene process Download PDF

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KR20030054175A
KR20030054175A KR1020010084299A KR20010084299A KR20030054175A KR 20030054175 A KR20030054175 A KR 20030054175A KR 1020010084299 A KR1020010084299 A KR 1020010084299A KR 20010084299 A KR20010084299 A KR 20010084299A KR 20030054175 A KR20030054175 A KR 20030054175A
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mask pattern
dual damascene
semiconductor device
damascene process
manufacturing
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KR1020010084299A
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Korean (ko)
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최재성
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device using dual damascene processing is provided to be capable of performing self-aligned dual damascene processing by cross-linking of a resist pattern. CONSTITUTION: An interlayer dielectric(12) is formed on a semiconductor substrate(11). The first mask pattern(13) is formed on the interlayer dielectric. A polymer substance(14) containing crosslink agents is formed on the first mask pattern(13). By baking the polymer substance(14), the crosslink agents are diffused into the first mask pattern. The developing is performed ant simultaneously removed the remaining polymer substance(14). The second mask pattern is formed on the first mask pattern(14). A via hole is formed and the second mask pattern is cured. After removing the exposed first mask pattern, a trench is formed using the second mask pattern as a mask. The remaining first and second mask pattern are removed.

Description

듀얼 다마신 공정을 이용한 반도체 소자의 제조방법{A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS}A method for manufacturing a semiconductor device using a dual damascene process {A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS}

본 발명은 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법에 관한 것으로, 특히 패터닝된 레지스트를 가교결합(crosslink)시킴으로써 셀프-얼라인 듀얼 다마신(self aligned dual damascene) 공정을 실시하는 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a dual damascene process, and in particular, a dual damascene process in which a self-aligned dual damascene process is performed by crosslinking a patterned resist. It relates to a method for manufacturing a semiconductor device using.

점차적으로 반도체 소자가 집적화되고 기술이 발전함에 따라 스피드(speed)나 저항 또는 금속간의 기생 캐패시터 문제점이 대두되면서 알루미늄 대신 구리 배선공정이 차세대 소자의 배선 공정으로 각광을 받고 있다.As semiconductor devices are gradually integrated and technology is advanced, problems of speed, resistance, or parasitic capacitors between metals have emerged, and copper wiring processes instead of aluminum have been spotlighted as wiring processes of next-generation devices.

그러나 구리 배선공정은 구리의 식각 특성이 매우 열악하여 듀얼 다마신 공정을 사용한다.However, the copper wiring process uses the dual damascene process because the etching property of copper is very poor.

한편, 듀얼 다마신 공정을 이용한 구리 배선공정시 비아 패턴과 금속배선 패턴에서 발생하게 되는 미스-얼라인(misalign)으로 인해 구리 증착 공정시 보이드(void) 발생한다. 따라서, 보이드 발생은 비아 저항에 치명적인 문제로 작용한다.Meanwhile, voids are generated during the copper deposition process due to misalignment occurring in the via pattern and the metal wiring pattern in the copper wiring process using the dual damascene process. Therefore, void generation poses a fatal problem for via resistance.

상기와 같은 문제점을 해결하기 위해 질화막 등의 하드 마스크(hard mask)를 이용한 셀프-얼라인 듀얼 다마신 공정을 실시한다.In order to solve the above problems, a self-aligned dual damascene process using a hard mask such as a nitride film is performed.

그러나 하드 마스크를 이용한 셀프-얼라인 듀얼 다마신 공정의 경우, 공정이 복잡하고, 절연막의 콘스탄트(dielectric constant)가 큰 질화막 등의 물질을 하드 마스크로 사용하므로 인터레이어 캐패시터(Interlayer Cap) 등의 문제점을 갖는다.However, in the case of a self-aligned dual damascene process using a hard mask, a process is complicated and a problem such as an interlayer capacitor is used since a material such as a nitride film having a large constant constant of an insulating film is used as a hard mask. Has

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 가교결합제(corsslinkable agent)를 함유한 수용성 고분자 용액을 이용하여 레지스트를 가교결합시켜 패턴을 형성하므로 공정을 단순화시킬 수 있는 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems by using a water-soluble polymer solution containing a cross-linking agent (corsslinkable agent) using a dual damascene process to form a pattern by cross-linking the resist to simplify the process Its purpose is to provide a method for manufacturing a semiconductor device.

도 1a 내지 도 1e는 본 발명의 일실시예에 따른 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device using a dual damascene process according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 : 반도체 기판 12 : 층간 절연막11 semiconductor substrate 12 interlayer insulating film

13, 13a : 제 1 포토레지스트 14 : 고분자 물질13, 13a: first photoresist 14: polymer material

15 : 제 2 포토레지스트 16 : 비아홀15: second photoresist 16: via hole

17 : 실리콘 산화막 18 : 트랜치17 silicon oxide film 18 trench

상기와 같은 문제점을 해결하기 위하여 안출한 것으로 듀얼 다마신 공정을이용한 반도체 소자의 제조방법은 반도체 기판상에 층간 절연막을 형성하는 단계와, 상기 층간 절연상에 제 1 마스크 패턴을 형성하는 단계와, 상기 제 1 마스크 패턴상에 가교결합제 함유한 고분자 물질을 증착한후, 베이킹 공정을 실시하여 제 1 마스크 패턴으로 확산시키는 단계와, 상기 결과물에 세정공정을 실시하여 잔존하는 고분자 물질을 제거하는 단계와, 상기 제 1 마스크 패턴상에 제 2 마스크 패턴을 형성하는 단계와, 상기 제 1 마스크 패턴을 이용한 식각공정으로 비아홀을 형성함과 동시에 제 2 마스크 패턴을 경화시키는 단계와, 상기 노출된 제 1 마스크 패턴을 제거한 후, 상기 제 2 마스크 패턴을 이용한 식각공정으로 트랜치를 형성하는 단계와, 상기 잔존하는 제 1, 제 2 마스크 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.In order to solve the above problems, a method of manufacturing a semiconductor device using a dual damascene process includes forming an interlayer insulating film on a semiconductor substrate, forming a first mask pattern on the interlayer insulating film, Depositing a polymer material containing a crosslinking agent on the first mask pattern, followed by baking to diffuse into the first mask pattern, and performing a cleaning process on the resultant to remove the remaining polymer material; Forming a second mask pattern on the first mask pattern, forming a via hole by an etching process using the first mask pattern, and curing the second mask pattern at the same time; After removing the pattern, forming a trench by an etching process using the second mask pattern, and the remaining first, Removing the second mask pattern.

또한, 상기 제 1 마스크 패턴으로 가교결합제를 확산시키는 방법은 오븐, 핫 플레이트 가열방법중 어느 하나를 사용하는 것이 바람직하다.In addition, it is preferable to use any one of an oven and a hot plate heating method to diffuse the crosslinking agent in the first mask pattern.

또한, 상기 오븐 온도 및 핫 플레이트 온도는 50∼250℃로 사용하는 것이 바람직하다.In addition, it is preferable to use the said oven temperature and hot plate temperature at 50-250 degreeC.

또한, 상기 가교결합제는 멀티 기능을 갖는 에테르 및 멀티 기능을 갖는 알킬기 헤일로 합성물 중 어느 하나를 사용하는 것이 바람직하다.In addition, it is preferable to use any one of the crosslinking agent ether having a multi-function and alkyl group halo composite having a multi-function.

또한, 상기 멀티 기능을 갖는 에테르는 메틸에테르 및 에틸에테르 중 어느 하나를 사용하는 것이 바람직하다.In addition, as the ether having a multi-function, it is preferable to use any one of methyl ether and ethyl ether.

또한, 상기 멀티 기능을 갖는 알킬기 헤일로 합성물은 알킬기 크롬 합성물, 알킬기 브롬 합성물 그리고 알킬기 요오드 합성물 중 어느 하나를 사용하는 것이바람직하다.In addition, it is preferable to use any one of an alkyl group halo compound having an alkyl group chromium compound, an alkyl group bromine compound, and an alkyl group iodine compound.

이하, 첨부된 도면을 참조하여 본 발명의 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법에 대하여 보다 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device using the dual damascene process of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1은 본 발명의 일실시예에 따른 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법을 나타낸 공정 단면도이다.1A through 1 are cross-sectional views illustrating a method of manufacturing a semiconductor device using a dual damascene process according to an exemplary embodiment of the present invention.

도 1a에 도시한 바와 같이 반도체 기판(11)상에 층간 절연막(12)을 형성하고, 상기 층간 절연막(12)상에 제 1 포토레지스트(13)를 증착한 후, 노광 및 현상공정을 이용하여 패터닝한다.As shown in FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 11, a first photoresist 13 is deposited on the interlayer insulating film 12, and then exposed and developed. Pattern.

도 1b에 도시한 바와 같이 상기 패터닝된 제 1 포토레지스트(13)상에 가교결합제를 함유한 고분자 물질(14)을 증착한 후, 베이킹 공정을 실시하여 상기 고분자 물질(14)을 상기 패터닝된 제 1 포토레지스트(13)로 확산시킨다. 이때, 상기 고분자 물질(14)은 탑 반사방지막(Top ARC)과 비슷한 물 가용성(water soluble) 고분자 용액이어야 하고, 그 용액의 용매는 물이다.As shown in FIG. 1B, a polymer material 14 containing a crosslinking agent is deposited on the patterned first photoresist 13, and then a baking process is performed to convert the polymer material 14 into the patterned agent. 1 is diffused into the photoresist 13. At this time, the polymer material 14 should be a water soluble polymer solution similar to Top ARC, and the solvent of the solution is water.

즉, 상기 고분자 물질(14)속에 있는 가교결합제가 열에 의해 패터닝된 제 1 포토레지스트(13) 내부로 확산된다. 상기 패터닝된 제 1 포토레지스트(13) 내부의 노브랙(Novolac) 혹은 스티렌(stylene) 폴리머의 -OH기들간의 가교결합이 이루어져 후속 공정에서 형성될 포토레지스트 형성시 혼합되지 않는다.That is, the crosslinking agent in the polymer material 14 diffuses into the first photoresist 13 patterned by heat. Crosslinking between —OH groups of a Novolac or styrene polymer in the patterned first photoresist 13 is performed and does not mix when forming a photoresist to be formed in a subsequent process.

여기서, 상기 베이킹 공정은 오븐, 핫 플레이트 가열방법중 어느 하나를 사용하고 그 온도는 50∼250℃이다.Here, the baking step uses any one of an oven and a hot plate heating method, the temperature is 50 ~ 250 ℃.

또한, 상기 가교결합제는 멀티 기능을 갖는 에테르(Multi-Functional Ether)이고, 상기 멀티 기능을 갖는 에테르는 메틸에테르(Methyl Ether) 및 에틸에테르(Ethyl Ether) 중 어느 하나를 사용한다.In addition, the crosslinking agent is a multi-functional ether, and the multi-functional ether uses any one of methyl ether and ethyl ether.

그리고 상기 가교결합제는 멀티 기능을 갖는 알킬기 헤일로 합성물(Multi-Functional Alkyl Halo Compound)이고, 상기 멀티 기능을 갖는 알킬기 헤일로 합성물은 알킬기 크롬 합성물(Alkyl Chloro Compound), 알킬기 브롬 합성물(Alkyl Bromo Compound) 그리고 알킬기 요오드 합성물(Alkyl Iodo Compound) 중 어느 하나를 사용한다.And the crosslinking agent is a multi-functional alkyl halo compound (Multi-Functional Alkyl Halo Compound), the multi-functional alkyl group halo compound is an alkyl chromium compound (Alkyl Chloro Compound), an alkyl group bromine compound (Alkyl Bromo Compound) and an alkyl group Any one of the Alkyl Iodo Compounds is used.

도 1c에 도시한 바와 같이 상기 결과물에 DI(0De Ionized) 현상공정을 실시하여 레지스트 코팅(Resist Coation) 저항력을 갖는 제 1 포토레지스트(13a)를 형성한다. 이때, 상기 고분자 물질(14)은 현상되어 없어진다.As shown in FIG. 1C, the resultant is subjected to a DI (0De Ionized) developing process to form a first photoresist 13a having a resist coating resistance. At this time, the polymer material 14 is developed and disappeared.

이어, 상기 결과물 상부에 제 2 포토레지스트(15)를 증착하고, 노광 및 현상공정을 이용하여 패터닝한다. 이때, 상기 제 2 포토레지스트(15)를 실리콘을 함유한 레지스트이다.Subsequently, a second photoresist 15 is deposited on the resultant, and patterned using an exposure and development process. At this time, the second photoresist 15 is a resist containing silicon.

도 1d에 도시한 바와 같이 상기 제 1 포토레지스트(13a)를 마스크로 이용한 식각공정을 통해 상기 층간 절연막(12)을 선택적으로 식각하여 비아홀(16)을 형성한다. 이때, 상기 제 2 포토레지스트(16) 표면의 일부가 손실(loss)되면서 플라즈마 식각물질로 인해 상기 제 2 포토레지스트(16) 표면이 실리콘 산화막(17)으로 변하게 된다.As illustrated in FIG. 1D, the interlayer insulating layer 12 is selectively etched through an etching process using the first photoresist 13a as a mask to form a via hole 16. At this time, a portion of the surface of the second photoresist 16 is lost and the surface of the second photoresist 16 is changed to the silicon oxide layer 17 due to the plasma etching material.

도 1e에 도시한 바와 같이 상기 노출된 제 1 포토레지스트(13a)는 O2식각공정 진행시 식각되고, 상기 잔존하는 제 1, 제 2 포토레지스트(13a)(15)를 마스크로이용한 식각공정으로 상기 층간 절연막(12)을 선택적으로 제거하여 트랜치(18)를 형성한다.As shown in FIG. 1E, the exposed first photoresist 13a is etched during the O 2 etching process, and the first and second photoresist 13a and 15 remaining as an etching process are used as a mask. The interlayer insulating layer 12 is selectively removed to form a trench 18.

이어, 상기 잔존하는 제 1, 제 2 포토레지스트(13a)(15)를 제거한다.Next, the remaining first and second photoresist 13a and 15 are removed.

이상에서 설명한 바와 같이 본 발명의 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법에 의하면, 단순한 레지스트 공정만으로 셀프 얼라인 듀얼 다마신 공정을 실시하므로 비용을 감소시킬 수 있는 효과가 있다.As described above, according to the method of manufacturing a semiconductor device using the dual damascene process of the present invention, since the self-aligned dual damascene process is performed by a simple resist process, the cost can be reduced.

또한, 공정을 단순화하여 생산 수율을 향상시킬 수 있다.In addition, the production yield can be improved by simplifying the process.

Claims (6)

반도체 기판상에 층간 절연막을 형성하는 단계와;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간 절연상에 제 1 마스크 패턴을 형성하는 단계와;Forming a first mask pattern on the interlayer insulation; 상기 제 1 마스크 패턴상에 가교결합제 함유한 고분자 물질을 증착한후, 베이킹 공정을 실시하여 제 1 마스크 패턴으로 확산시키는 단계와;Depositing a polymer material containing a crosslinking agent on the first mask pattern, and then performing a baking process to diffuse the first material into the first mask pattern; 상기 결과물에 현상공정을 실시함과 동시에 잔존하는 고분자 물질을 제거하는 단계와;Performing a developing process on the resultant and removing the remaining polymer material; 상기 제 1 마스크 패턴상에 제 2 마스크 패턴을 형성하는 단계와;Forming a second mask pattern on the first mask pattern; 상기 제 1 마스크 패턴을 이용한 식각공정으로 비아홀을 형성함과 동시에 제 2 마스크 패턴을 경화시키는 단계와;Forming a via hole by an etching process using the first mask pattern and simultaneously curing the second mask pattern; 상기 노출된 제 1 마스크 패턴을 제거한 후, 상기 제 2 마스크 패턴을 이용한 식각공정으로 트랜치를 형성하는 단계와;Removing the exposed first mask pattern and forming a trench by an etching process using the second mask pattern; 상기 잔존하는 제 1, 제 2 마스크 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법.And removing the remaining first and second mask patterns. 제 1 항에 있어서,The method of claim 1, 상기 제 1 마스크 패턴으로 가교결합제를 확산시키는 방법은 오븐, 핫 플레이트 가열방법중 어느 하나를 사용하는 것을 특징으로 하느 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법.The method of diffusing the crosslinking agent into the first mask pattern is a method of manufacturing a semiconductor device using a dual damascene process, characterized in that any one of an oven, hot plate heating method. 제 2 항에 있어서,The method of claim 2, 상기 오븐 온도 및 핫 플레이트 온도는 50∼250℃로 사용하는 것을 특징으로 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법.The oven temperature and the hot plate temperature is 50 to 250 ℃ characterized in that the semiconductor device manufacturing method using a dual damascene process. 제 1 항에 있어서,The method of claim 1, 상기 가교결합제는 멀티 기능을 갖는 에테르 및 멀티 기능을 갖는 알킬기 헤일로 합성물 중 어느 하나를 사용하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법.The crosslinking agent is a method for manufacturing a semiconductor device using a dual damascene process, characterized in that any one of a multi-functional ether and a multi-functional alkyl halo composite. 제 4 항에 있어서,The method of claim 4, wherein 상기 멀티 기능을 갖는 에테르는 메틸에테르 및 에틸에테르 중 어느 하나를 사용하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법.The multi-functional ether is a method of manufacturing a semiconductor device using a dual damascene process, characterized in that using any one of methyl ether and ethyl ether. 제 4 항에 있어서,The method of claim 4, wherein 상기 멀티 기능을 갖는 알킬기 헤일로 합성물은 알킬기 크롬 합성물, 알킬기 브롬 합성물 그리고 알킬기 요오드 합성물 중 어느 하나를 사용하는 것을 특징으로 하는 듀얼 다마신 공정을 이용한 반도체 소자의 제조방법.The multi-functional alkyl group halo composite may be any one of an alkyl chromium composite, an alkyl bromine composite, and an alkyl iodine composite.
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KR100746481B1 (en) * 2006-08-29 2007-08-03 동부일렉트로닉스 주식회사 A method of fabricating semiconductor device
US10305030B2 (en) 2013-06-05 2019-05-28 SK Hynix Inc. Electronic device and method for fabricating the same
US9786840B2 (en) 2013-06-05 2017-10-10 SK Hynix Inc. Electronic device and method for fabricating the same
US9865806B2 (en) 2013-06-05 2018-01-09 SK Hynix Inc. Electronic device and method for fabricating the same
US8959250B2 (en) 2013-06-05 2015-02-17 SK Hynix Inc. Electronic device and method for fabricating the same
US10490741B2 (en) 2013-06-05 2019-11-26 SK Hynix Inc. Electronic device and method for fabricating the same
US10777742B2 (en) 2013-06-05 2020-09-15 SK Hynix Inc. Electronic device and method for fabricating the same
US9502639B2 (en) 2013-09-30 2016-11-22 SK Hynix Inc. Electronic device for improving characteristic of variable resistance element and method of fabricating the same
US10205089B2 (en) 2014-02-28 2019-02-12 SK Hynix Inc. Electronic device and method for fabricating the same
US9865319B2 (en) 2014-12-17 2018-01-09 SK Hynix Inc. Electronic device and method for fabricating the same
US10134458B2 (en) 2014-12-17 2018-11-20 SK Hynix Inc. Electronic device and method for fabricating the same
US10367137B2 (en) 2014-12-17 2019-07-30 SK Hynix Inc. Electronic device including a semiconductor memory having a variable resistance element including two free layers
US9859490B2 (en) 2015-04-14 2018-01-02 SK Hynix Inc. Electronic device including a semiconductor memory having multi-layered structural free layer

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