KR20020091440A - Method for forming a metal line - Google Patents

Method for forming a metal line Download PDF

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Publication number
KR20020091440A
KR20020091440A KR1020010030116A KR20010030116A KR20020091440A KR 20020091440 A KR20020091440 A KR 20020091440A KR 1020010030116 A KR1020010030116 A KR 1020010030116A KR 20010030116 A KR20010030116 A KR 20010030116A KR 20020091440 A KR20020091440 A KR 20020091440A
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South Korea
Prior art keywords
film
photoresist
forming
layer
photoresist film
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KR1020010030116A
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Korean (ko)
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최재성
신대웅
전호열
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주식회사 하이닉스반도체
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Priority to KR1020010030116A priority Critical patent/KR20020091440A/en
Publication of KR20020091440A publication Critical patent/KR20020091440A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for forming a metal interconnection is provided to simplify self-aligned dual damascene processes by using a baked photoresist layer and a silicon-contained photoresist layer without using a hard mask. CONSTITUTION: After forming an interlayer dielectric(33) on a semiconductor substrate(31), a first photoresist layer(35) is coated on the interlayer dielectric(33). The first photoresist layer(35) is selectively developed and baked. A silicon-contained second photoresist layer(37) is coated on the resultant structure. The interlayer dielectric(33) is then selectively etched by using the baked first photoresist layer(35) and the silicon-contained second photoresist layer(37) as a mask, thereby forming a contact hole. After developing the exposed first photoresist layer(35), the exposed interlayer dielectric is then etched, thereby forming a groove while removing the second photoresist layer changed to a silicon oxide. A metal interconnection is formed by filling a metal film into the contact hole and the groove.

Description

금속배선 형성 방법{Method for forming a metal line}Method for forming a metal line

본 발명은 금속배선 형성 방법에 관한 것으로, 특히 두 층의 감광막을 사용하여 셀프 얼라인드 듀얼 다마신(Self aligned dual damascene) 공정을 진행하므로소자의 수율 및 신뢰성을 향상시키는 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for forming metal wiring, and more particularly, to a method for forming metal wiring to improve the yield and reliability of a device by performing a self aligned dual damascene process using two photosensitive films. .

반도체 소자가 집적화되고 기술이 발전함에 따라, 속도나 저항 혹은 금속간의 기생 캐패시터 등의 문제점이 대두되면서 알루미늄(Al) 배선 대신 구리(Cu) 배선 공정이 차세대 소자의 배선 공정으로 사용되고 있다.As semiconductor devices have been integrated and technology has developed, problems such as speed, resistance, or parasitic capacitors between metals have emerged, and copper (Cu) wiring processes are being used as wiring processes of next generation devices instead of aluminum (Al) wiring.

상기 구리 배선 공정은 구리의 식각 공정이 어려워 듀얼 다마신 공정을 사용하고 있다.The copper wiring process uses a dual damascene process because the copper etching process is difficult.

종래의 금속배선 형성 방법은 도 1a에서와 같이, 반도체 기판(11) 상에 제 1 층간 산화막(13), 질화막(15) 및 제 2 층간 산화막(17)을 순차적으로 형성한다.In the conventional metal wiring forming method, as shown in FIG. 1A, the first interlayer oxide film 13, the nitride film 15, and the second interlayer oxide film 17 are sequentially formed on the semiconductor substrate 11.

도 1b에서와 같이, 상기 제 2 층간 산화막(17) 상에 제 1 감광막(19)을 도포하고, 상기 제 1 감광막(19)을 콘택홀이 형성될 부위에만 제거되도록 선택 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 1 감광막(19)을 마스크로 상기 제 2 층간 산화막(17), 질화막(15) 및 제 1 층간 산화막(13)을 선택 식각하여 콘택홀을 형성한다.As shown in FIG. 1B, after the first photoresist film 19 is applied onto the second interlayer oxide film 17, the first photoresist film 19 is selectively exposed and developed to be removed only at a portion where a contact hole is to be formed. The second interlayer oxide film 17, the nitride film 15, and the first interlayer oxide film 13 are selectively etched using the selectively exposed and developed first photosensitive film 19 as a mask to form a contact hole.

도 1c에서와 같이, 상기 제 1 감광막(19)을 제거한 다음, 상기 콘택홀을 포함한 제 2 층간 산화막(17) 상에 제 2 감광막(21)을 도포한다.As shown in FIG. 1C, the first photosensitive film 19 is removed, and then the second photosensitive film 21 is coated on the second interlayer oxide film 17 including the contact hole.

그리고, 상기 제 2 감광막(21)을 상기 콘택홀을 포함한 부위에 콘택홀보다 큰 면적의 홈이 형성될 부위에만 제거되도록 선택 노광 및 현상한 후, 상기 선택적으로 노광 및 현상된 제 2 감광막(21)을 마스크로 상기 제 2 층간 산화막을 선택 식각하여 홈을 형성한 다음, 상기 제 2 감광막(21)을 제거한다.The second photosensitive film 21 is selectively exposed and developed to be removed only at a portion where a groove having a larger area than the contact hole is formed in the portion including the contact hole, and then the selectively exposed and developed second photosensitive film 21. The second interlayer oxide layer is selectively etched using a mask to form a groove, and then the second photoresist layer 21 is removed.

이어, 차후 공정으로 상기 콘택홀과 홈을 금속층으로 매립하여 금속배선층을형성한다.Subsequently, the contact hole and the groove are filled with a metal layer in a subsequent process to form a metal wiring layer.

그러나, 종래의 금속배선 형성 방법은 질화막과 같은 하드 마스크(Hard mask) 셀프 얼라인드 듀얼 다마신 공정을 사용하여 금속배선층을 형성하기 때문에 제 1 층간 절연막, 하드 마스크층, 제 2 층간 절연막 형성 공정 등의 공정이 복잡하고 유전 상수가 큰 하드 마스크층의 사용으로 층간 캐패시터가 커 소자의 수율 및 신뢰성이 저하되는 문제점이 있었다.However, since the metallization layer is formed by using a hard mask self-aligned dual damascene process such as a nitride film, a conventional metallization method is used to form a first interlayer insulating film, a hard mask layer, and a second interlayer insulating film. Due to the complexity of the process and the use of a hard mask layer having a large dielectric constant, the interlayer capacitor is large, resulting in a decrease in yield and reliability of the device.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 셀프 얼라인드 듀얼 다마신 공정을 사용하여 금속배선층을 형성하는 공정에 있어서, 콘택홀 형성 시 사용할 제 1 감광막을 감광막의 도포 공정에 저항력을 갖도록 경화시킨 후 그 상측에 실리콘 함유 제 2 감광막을 도포한 다음 상기 제 1, 제 2 감광막에 의해 셀프 얼라인드 듀얼 다마신 공정을 진행하여 듀얼 다마신 공정이 단순화하고 하드 마스크층을 사용하지 않아 층간 캐패시터의 발생을 방지하는 금속배선 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, in the step of forming a metal wiring layer using a self-aligned dual damascene process, curing the first photosensitive film to be used for forming the contact hole to resist the coating process of the photosensitive film After applying a silicon-containing second photoresist film on the upper side, the self-aligned dual damascene process is performed by the first and second photoresist to simplify the dual damascene process and does not use a hard mask layer. It is an object of the present invention to provide a method for forming metal wiring to prevent the occurrence.

도 1a내지 도 1c는 종래 기술에 따른 금속배선 형성 방법을 나타낸 공정 단면도.1A to 1C are cross-sectional views illustrating a method for forming metal wirings according to the prior art.

도 2a내지 도 2f는 본 발명의 제 1 실시 예에 따른 금속배선 형성 방법을 나타낸 공정 단면도.2A to 2F are cross-sectional views illustrating a method of forming metal wirings according to a first embodiment of the present invention.

도 3a내지 도 3h는 본 발명의 제 2 실시 예에 따른 금속배선 형성 방법을 나타낸 공정 단면도.3A to 3H are cross-sectional views illustrating a method for forming metal wirings according to a second embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11, 31 : 반도체 기판 13 : 제 1 층간산화막11, 31: semiconductor substrate 13: first interlayer oxide film

33 : 층간 산화막 15 : 질화막33: interlayer oxide film 15: nitride film

17 : 제 2 층간 산화막 19, 35 : 제 1 감광막17: second interlayer oxide film 19, 35: first photosensitive film

21, 37 : 제 2 감광막 41 : 고분자 용액21, 37: second photosensitive film 41: polymer solution

본 발명의 금속배선 형성 방법은 기판 상에 층간 산화막과 제 1 감광막을 순차적으로 형성하는 단계, 상기 콘택홀이 형성될 부위의 제 1 감광막을 선택 현상하고, 상기 제 1 감광막을 경화시키는 단계, 상기 구조물 상에 실리콘이 함유된 제 2 감광막을 도포하는 단계, 상기 제 1 감광막의 식각 부위를 포함하여 제 1 감광막의 식각 부위보다 큰 면적의 홈이 형성될 부위의 제 2 감광막을 선택 현상하는 단계,상기 제 1, 제 2 감광막을 마스크로 상기 층간 산화막을 선택 식각하여 상기 제 2 감광막이 실리콘 산화막으로 변화되면서 콘택홀을 형성하는 단계, 상기 제 2 감광막으로부터 노출된 제 1 감광막을 현상하는 단계, 상기 제 1 감광막의 현상으로 노출된 층간 산화막을 식각하되, 상기 실리콘 산화막으로 변화된 제 2 감광막이 제거되면서 홈을 형성하는 단계 및 상기 제 1 감광막을 제거하고 상기 콘택홀과 홈을 금속층으로 매립하여 금속배선층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.In the metal wire forming method of the present invention, the step of sequentially forming the interlayer oxide film and the first photosensitive film on the substrate, the step of selectively developing the first photosensitive film of the region where the contact hole is to be formed, and curing the first photosensitive film, Applying a second photoresist film containing silicon on the structure, selectively developing and developing a second photoresist film at a portion where a groove having a larger area than that of the first photoresist film is to be formed, including an etching portion of the first photoresist film, Selectively etching the interlayer oxide layer using the first and second photoresist layers as a mask to form a contact hole while the second photoresist layer is changed to a silicon oxide layer, and developing a first photoresist layer exposed from the second photoresist layer, wherein Etching the interlayer oxide film exposed by the phenomenon of the first photoresist film, and forming a groove while removing the second photoresist film changed into the silicon oxide film. And removing the first photoresist film and filling the contact hole and the groove with a metal layer to form a metal wiring layer.

상기와 같은 본 발명에 따른 금속배선 형성 방법의 바람직한 실시 예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the metal wiring forming method according to the present invention as follows.

도 2a내지 도 2f는 본 발명의 제 1 실시 예에 따른 금속배선 형성 방법을 나타낸 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method for forming metal wirings according to a first embodiment of the present invention.

본 발명의 제 1 실시 예에 따른 금속배선 형성 방법은 도 2a에서와 같이, 반도체 기판(31) 상에 층간 산화막(33)과 제 1 감광막(35)을 순차적으로 형성한다.In the method for forming metal wirings according to the first embodiment of the present invention, as shown in FIG. 2A, the interlayer oxide layer 33 and the first photosensitive layer 35 are sequentially formed on the semiconductor substrate 31.

그리고, 상기 제 1 감광막(35)을 콘택홀이 형성될 부위에만 제거되도록 선택 노광 및 현상한다.Then, the first photoresist layer 35 is selectively exposed and developed to be removed only at a portion where a contact hole is to be formed.

그리고, 상기 제 1 감광막(35)을 UV 베이크(Ultraviolet bake) 공정으로 경화한다.In addition, the first photosensitive layer 35 is cured by a UV bake process.

도 2b에서와 같이, 상기 경화된 제 1 감광막(35)을 포함한 층간 산화막(33) 상에 실리콘이 함유된 제 2 감광막(37)을 도포한다.As shown in FIG. 2B, a second photosensitive film 37 containing silicon is coated on the interlayer oxide film 33 including the cured first photosensitive film 35.

그리고, 상기 제 2 감광막(37)을 상기 제 1 감광막(35)의 현상 부위를 포함하여 제 1 감광막(35)의 현상 부위보다 큰 면적의 홈이 형성될 부위에만 제거되도록 선택 노광 및 현상한다.Then, the second photosensitive film 37 is selectively exposed and developed so as to be removed only at a portion where a groove having a larger area than that of the first photosensitive film 35 is formed, including the developing portion of the first photosensitive film 35.

도 2c에서와 같이, 상기 선택 노광 및 현상된 제 1, 제 2 감광막(35,37)을 마스크로 상기 층간 산화막(33)을 선택 식각하여 콘택홀을 형성한다.As illustrated in FIG. 2C, contact holes are formed by selectively etching the interlayer oxide layer 33 using the first and second photosensitive layers 35 and 37 that have been subjected to the selective exposure and development.

여기서, 상기 층간 산화막(33)의 식각 공정 시, 상기 제 2 감광막(37)의 표면이 손상되면서 플라즈마 에천트(Plasma etchant)로 인해 상기 제 2 감광막(37)의 표면이 실리콘 산화막으로 변하게 된다.In the etching process of the interlayer oxide layer 33, the surface of the second photoresist layer 37 is damaged and the surface of the second photoresist layer 37 is changed to a silicon oxide layer due to a plasma etchant.

도 2d에서와 같이, 상기 노출된 제 1 감광막(35)을 산소(O2)식각 공정으로 제거한다.As shown in FIG. 2D, the exposed first photoresist layer 35 is removed by an oxygen (O 2 ) etching process.

도 2e에서와 같이, 상기 노출된 층간 산화막(33)을 선택 식각하여 홈을 형성한다.As shown in FIG. 2E, the exposed interlayer oxide layer 33 is selectively etched to form grooves.

이때, 상기 홈을 형성하기 위한 층간 산화막(33) 식각 공정 시, 상기 그 표면이 실리콘 산화막화된 제 2 감광막(37)도 제거된다.At this time, during the etching process of the interlayer oxide film 33 for forming the groove, the second photosensitive film 37 having the silicon oxide film formed on the surface thereof is also removed.

도 2f에서와 같이, 상기 제 1 감광막(35)을 제거한다.As shown in FIG. 2F, the first photosensitive film 35 is removed.

그리고, 차후 공정으로 상기 콘택홀과 홈을 금속층으로 매립하여 금속배선층을 형성한다.Subsequently, the contact hole and the groove are filled with a metal layer in a subsequent process to form a metal wiring layer.

도 3a내지 도 3h는 본 발명의 제 2 실시 예에 따른 금속배선 형성 방법을 나타낸 공정 단면도이다.3A to 3H are cross-sectional views illustrating a method of forming metal wirings according to a second embodiment of the present invention.

본 발명의 제 2 실시 예에 따른 금속배선 형성 방법은 도 3a에서와 같이, 반도체 기판(31) 상에 층간 산화막(33)과 제 1 감광막(35)을 순차적으로 형성한다.In the method for forming metal wirings according to the second embodiment of the present invention, as shown in FIG. 3A, the interlayer oxide layer 33 and the first photosensitive layer 35 are sequentially formed on the semiconductor substrate 31.

그리고, 상기 제 1 감광막(35)을 콘택홀이 형성될 부위에만 제거되도록 선택 노광 및 현상한다.Then, the first photoresist layer 35 is selectively exposed and developed to be removed only at a portion where a contact hole is to be formed.

도 3b에서와 같이, 상기 선택적으로 노광 및 현상된 제 1 감광막(35)을 포함한 층간 산화막(33) 상에 가교제(Crosslinkable agent)를 함유한 고분자 용액(41)을 도포한다.As shown in FIG. 3B, a polymer solution 41 containing a crosslinkable agent is coated on the interlayer oxide film 33 including the selectively exposed and developed first photosensitive film 35.

여기서, 상기 고분자 용액(41)을 탑(Top) 에이알시(Anti Reflective Coating: ARC)와 같은 수용성 고분자 용액이고 용액의 용매는 물이다.Here, the polymer solution 41 is a water-soluble polymer solution such as Top Anti Reflective Coating (ARC), and the solvent of the solution is water.

상기 가교제로 메틸에테르(Methyl Ether)와 에틸(Ethyl)에테르와 같은 다중 작용기(Multi-functional)를 갖는 에테르 또는 알킬 클로로(Alkyl Chloro) 화합물, 알킬 브로모(Bromo) 화합물 및 알킬 요오드(Iodo) 화화물 등과 같은 다중 작용기를 갖는 알킬(Alkyl) 할로우(Halo) 화합물을 사용한다.Ether or alkyl chloro (Alkyl Chloro) compound, alkyl bromo (Bromo) compound and alkyl iodo (method) having a multi-functional such as methyl ether and ethyl ether as the crosslinking agent Alkyl halo compounds having multiple functional groups, such as cargoes, are used.

그리고, 상기 고분자 용액(41)을 베이킹하여 상기 제 1 감광막(35)으로 가교제를 확산시킨다.The polymer solution 41 is baked to diffuse the crosslinking agent into the first photosensitive layer 35.

이때, 상기 제 1 감광막(35)에 가교제의 확산으로 상기 제 1 감광막(35) 내부의 노볼락(Novolac) 폴리머(Polymer) 또는 스틸렌(Stylene) 폴리머의 (-)OH기들간의 가교가 이루어진다.In this case, the crosslinking between the (-) OH groups of the Novolac (Polymer) or styrene (Stylene) polymer in the first photosensitive layer 35 is achieved by diffusion of a crosslinking agent into the first photosensitive layer 35.

그리고, 상기 가교제의 확산 방법은 50 ∼ 250℃ 온도의 오븐(Oven)이나 핫 플레이트(Hot plate) 가열 방식을 사용한다.In addition, the diffusion method of the crosslinking agent uses an oven or a hot plate heating method at a temperature of 50 to 250 ° C.

도 3c에서와 같이, 상기 고분자 용액(41)을 증류수에 의해 현상하여 제거한다.As shown in FIG. 3c, the polymer solution 41 is developed and removed by distilled water.

도 3d에서와 같이, 상기 제 1 감광막(35)을 포함한 층간 산화막(33) 상에 실리콘이 함유된 제 2 감광막(37)을 도포한다.As shown in FIG. 3D, a second photosensitive film 37 containing silicon is coated on the interlayer oxide film 33 including the first photosensitive film 35.

여기서 상기 제 2 감광막(37)의 도포 시, 상기 노볼락 폴리머 또는 스틸렌 폴리머의 (-)OH기들간의 가교가 이루어진 제 1 감광막(35)은 인터믹싱 (Intermixing)이 배제될 수 있어 상기 제 2 감광막(37)의 도포 저항력을 갖는다.Here, when the second photoresist layer 37 is applied, the first photoresist layer 35 in which crosslinking is performed between the (-) OH groups of the novolac polymer or the styrene polymer may be excluded from intermixing. It has a coating resistance of (37).

그리고, 상기 제 2 감광막(37)을 상기 제 1 감광막(35)의 현상 부위를 포함하여 제 1 감광막(35)의 현상 부위보다 큰 면적의 홈이 형성될 부위에만 제거되도록 선택 노광 및 현상한다.Then, the second photosensitive film 37 is selectively exposed and developed so as to be removed only at a portion where a groove having a larger area than that of the first photosensitive film 35 is formed, including the developing portion of the first photosensitive film 35.

도 3e에서와 같이, 상기 선택 노광 및 현상된 제 1, 제 2 감광막(35,37)을 마스크로 상기 층간 산화막(33)을 선택 식각하여 콘택홀을 형성한다.As shown in FIG. 3E, the interlayer oxide layer 33 is selectively etched using the selective exposure and developed first and second photoresist layers 35 and 37 as a mask to form a contact hole.

여기서, 상기 층간 산화막(33)의 식각 공정 시, 상기 제 2 감광막(37)의 표면이 손상되면서 플라즈마 에천트(Plasma etchant)로 인해 상기 제 2 감광막(37)의 표면이 실리콘 산화막으로 변하게 된다.In the etching process of the interlayer oxide layer 33, the surface of the second photoresist layer 37 is damaged and the surface of the second photoresist layer 37 is changed to a silicon oxide layer due to a plasma etchant.

도 3f에서와 같이, 상기 노출된 제 1 감광막(35)을 산소(O2)식각 공정으로 제거한다.As shown in FIG. 3F, the exposed first photosensitive layer 35 is removed by an oxygen (O 2 ) etching process.

도 3g에서와 같이, 상기 노출된 층간 산화막(33)을 선택 식각하여 홈을 형성한다.As shown in FIG. 3G, the exposed interlayer oxide layer 33 is selectively etched to form grooves.

이때, 상기 홈을 형성하기 위한 층간 산화막(33) 식각 공정 시, 상기 그 표면이 실리콘 산화막화된 제 2 감광막(37)도 제거된다.At this time, during the etching process of the interlayer oxide film 33 for forming the groove, the second photosensitive film 37 having the silicon oxide film formed on the surface thereof is also removed.

도 3h에서와 같이, 상기 제 1 감광막(35)을 제거한다.As shown in FIG. 3H, the first photosensitive film 35 is removed.

그리고, 차후 공정으로 상기 콘택홀과 홈을 금속층으로 매립하여 금속배선층을 형성한다.Subsequently, the contact hole and the groove are filled with a metal layer in a subsequent process to form a metal wiring layer.

본 발명의 금속배선 형성 방법은 셀프 얼라인드 듀얼 다마신 공정을 사용하여 금속배선층을 형성하는 공정에 있어서, 콘택홀 형성 시 사용할 제 1 감광막을 감광막의 도포 공정에 저항력을 갖도록 경화시킨 후 그 상측에 실리콘 함유 제 2 감광막을 도포한 다음 상기 제 1, 제 2 감광막에 의해 셀프 얼라인드 듀얼 다마신 공정을 진행하므로, 듀얼 다마신 공정이 단순화하여 비용이 절감되고 하드 마스크층을 사용하지 않아 층간 캐패시터의 발생을 방지하여 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.In the metal wiring forming method of the present invention, in the process of forming a metal wiring layer using a self-aligned dual damascene process, the first photosensitive film to be used for forming the contact hole is cured to have a resistance to the coating process of the photosensitive film, Since the self-aligned dual damascene process is performed by applying the silicon-containing second photoresist film and then the first and second photoresist films, the dual damascene process is simplified and the cost is reduced, and the hard mask layer is not used. There is an effect of preventing the occurrence of the device to improve the yield and reliability of the device.

Claims (8)

기판 상에 층간 산화막과 제 1 감광막을 순차적으로 형성하는 단계;Sequentially forming an interlayer oxide film and a first photosensitive film on the substrate; 상기 콘택홀이 형성될 부위의 제 1 감광막을 선택 현상하고, 상기 제 1 감광막을 경화시키는 단계;Selecting and developing a first photoresist film of a portion where the contact hole is to be formed and curing the first photoresist film; 상기 구조물 상에 실리콘이 함유된 제 2 감광막을 도포하는 단계;Applying a second photoresist film containing silicon on the structure; 상기 제 1 감광막의 식각 부위를 포함하여 제 1 감광막의 식각 부위보다 큰 면적의 홈이 형성될 부위의 제 2 감광막을 선택 현상하는 단계;Selectively developing a second photoresist film at a portion where a groove having a larger area than that of the first photoresist film is to be formed, including an etching part of the first photoresist film; 상기 제 1, 제 2 감광막을 마스크로 상기 층간 산화막을 선택 식각하여 상기 제 2 감광막이 실리콘 산화막으로 변화되면서 콘택홀을 형성하는 단계;Selectively etching the interlayer oxide layer using the first and second photoresist layers as a mask to form a contact hole while the second photoresist layer is changed into a silicon oxide layer; 상기 제 2 감광막으로부터 노출된 제 1 감광막을 현상하는 단계;Developing the first photoresist film exposed from the second photoresist film; 상기 제 1 감광막의 현상으로 노출된 층간 산화막을 식각하되, 상기 실리콘 산화막으로 변화된 제 2 감광막이 제거되면서 홈을 형성하는 단계;Etching the interlayer oxide film exposed by the phenomenon of the first photoresist film, and forming a groove while removing the second photoresist film changed into the silicon oxide film; 상기 제 1 감광막을 제거하고 상기 콘택홀과 홈을 금속층으로 매립하여 금속배선층을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 금속배선 형성 방법.Removing the first photoresist layer and filling the contact hole and the groove with a metal layer to form a metal wiring layer. 제 1 항에 있어서,The method of claim 1, 상기 제 1 감광막을 UV 베이크(Ultraviolet bake) 공정으로 경화함을 특징으로 하는 금속배선 형성 방법.The method of claim 1, wherein the first photoresist film is cured by a UV bake process. 제 1 항에 있어서,The method of claim 1, 상기 제 2 감광막의 도포 공정 시 도포 공정의 저항력을 갖기 위해 상기 제 1 감광막에 가교제를 확산시킴을 특징으로 하는 금속배선 형성 방법.Metal line forming method characterized in that the cross-linking agent is diffused to the first photosensitive film in order to have a resistance of the coating process during the coating process of the second photosensitive film. 제 3 항에 있어서,The method of claim 3, wherein 상기 제 1 감광막을 포함한 층간 산화막 상에 가교제를 함유한 고분자 용액을 도포한 후, 상기 고분자 용액을 베이킹하여 상기 제 1 감광막으로 가교제를 확산시킴을 특징으로 하는 금속배선 형성 방법.And applying a polymer solution containing a crosslinking agent onto the interlayer oxide film including the first photosensitive film, and then baking the polymer solution to diffuse the crosslinking agent into the first photosensitive film. 제 3 항에 있어서,The method of claim 3, wherein 상기 가교제로 메틸에테르(Methyl Ether)와 에틸(Ethyl)에테르와 같은 다중 작용기를 갖는 에테르 또는 알킬 클로로(Alkyl Chloro) 화합물, 알킬 브로모(Bromo) 화합물 및 알킬 요오드(Iodo) 화화물 등과 같은 다중 작용기를 갖는 알킬 할로우(Halo) 화합물을 사용함을 특징으로 하는 금속배선 형성 방법.The crosslinking agent is an ether having multiple functional groups such as methyl ether and ethyl ether, or multiple functional groups such as an alkyl chloro compound, an alkyl bromo compound and an alkyl iodo compound. Method for forming metal wiring, characterized in that using an alkyl halo (Halo) compound having. 제 3 항에 있어서,The method of claim 3, wherein 상기 가교제의 확산 방법은 50 ∼ 250℃ 온도의 오븐(Oven)이나 핫 플레이트(Hot plate) 가열 방식을 사용함을 특징으로 하는 금속배선 형성 방법.The diffusion method of the cross-linking agent is a metal wiring forming method using an oven (Oven) or hot plate (Hot plate) heating method of 50 ~ 250 ℃ temperature. 제 4 항에 있어서,The method of claim 4, wherein 상기 고분자 용액을 탑(Top) 에이알시(Anti Reflective Coating: ARC)와 같은 수용성 고분자 용액을 사용함을 특징으로 하는 금속배선 형성 방법.The method of forming a metal wiring, characterized in that the polymer solution using a water-soluble polymer solution, such as Top Anti Reflective Coating (ARC). 제 1 항에 있어서,The method of claim 1, 상기 노출된 제 1 감광막을 산소(O2)식각 공정으로 제거함을 특징으로 하는 금속배선 형성 방법.And removing the exposed first photoresist layer by an oxygen (O 2 ) etching process.
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