KR100437614B1 - Method for forming metal interconnection line of semiconductor device - Google Patents
Method for forming metal interconnection line of semiconductor device Download PDFInfo
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- KR100437614B1 KR100437614B1 KR10-2001-0083269A KR20010083269A KR100437614B1 KR 100437614 B1 KR100437614 B1 KR 100437614B1 KR 20010083269 A KR20010083269 A KR 20010083269A KR 100437614 B1 KR100437614 B1 KR 100437614B1
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- metal wiring
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- semiconductor device
- interlayer insulating
- polymer solution
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000002184 metal Substances 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229920000642 polymer Polymers 0.000 claims abstract description 19
- 230000002378 acidificating effect Effects 0.000 claims abstract description 14
- 239000003989 dielectric material Substances 0.000 claims abstract description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 238000011161 development Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000010949 copper Substances 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims description 5
- 238000004380 ashing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 230000008016 vaporization Effects 0.000 claims 1
- 238000009834 vaporization Methods 0.000 claims 1
- 230000009977 dual effect Effects 0.000 abstract description 9
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 19
- 239000000463 material Substances 0.000 description 10
- 229910021529 ammonia Inorganic materials 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 231100000572 poisoning Toxicity 0.000 description 4
- 230000000607 poisoning effect Effects 0.000 description 4
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 150000007522 mineralic acids Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 150000007524 organic acids Chemical class 0.000 description 2
- LSNNMFCWUKXFEE-UHFFFAOYSA-M Bisulfite Chemical compound OS([O-])=O LSNNMFCWUKXFEE-UHFFFAOYSA-M 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 150000001735 carboxylic acids Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 저유전물질을 이용한 듀얼 다마신 공정에서 발생하는 레지스트 포저닝 현상을 산성 고분자의 도포 및 베킹을 이용하여 제거시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. 이를 위한 본 발명에 의한 반도체 소자의 금속 배선 형성 방법은 반도체 기판 위에 저유전물질의 층간절연막을 형성하는 단계와, 상기 층간절연막을 제 1 마스크 패턴에 의해 소정 부분 식각하여 금속배선이 형성될 패턴을 형성하는 단계와, 상기 구조물 위에 산성 고분자 용액을 도포한 후 배킹(Baking)을 실시하는 단계와, 상기 산성 고분자 용액을 제거하는 단계와, 상기 구조물 위에 감광막을 도포한 후 노광 및 현상 공정으로 금속배선을 형성하기 위한 제 2 마스크 패턴으로 형성하는 단계를 포함하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein the formation of a metal wiring of a semiconductor device capable of removing resist focusing phenomenon generated in a dual damascene process using a low dielectric material by using an acidic polymer coating and backing. It is about a method. The metal wiring forming method of the semiconductor device according to the present invention is to form an interlayer insulating film of a low dielectric material on the semiconductor substrate, and by etching a predetermined portion of the interlayer insulating film by a first mask pattern to form a pattern for forming a metal wiring Forming, applying an acidic polymer solution on the structure and then performing a backing (Baking), removing the acidic polymer solution, applying a photosensitive film on the structure and then exposure and development metal wiring Forming a second mask pattern for forming a.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 저유전물질(Low-k Material)을 이용한 듀얼 다마신(Dual Damascene) 공정에서 발생하는 레지스트 포저닝(Resist Poisoning) 현상을 산성 고분자의 도포 및 베킹(baking)을이용하여 제거시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, an acidic polymer is applied to a resist poisoning phenomenon occurring in a dual damascene process using a low-k material. And a method for forming metal wirings of a semiconductor device which can be removed by using baking.
반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.
최근 반도체 기술이 발전하면서 0.13㎛ 이하의 반도체 소자 제조 과정에서 배선 공정의 속도를 높이기 위하여 저유전물질(Low-k Material)과 구리(Cu)를 이용한 듀얼 다마신(Dual Damascene) 공정을 도입하게 되었다. 이러한 듀얼 다마신 공정(Dual Damascene)은 저항을 줄일 수 있어 소자의 동작 속도를 높일 수 있는 큰 장점을 가지고 있지만, 공정 도중 사용하는 저유전(Low-k) 물질에 함유된 암모니아에 의해 레지스트 포저닝(Resist Poisoning) 현상이 발생하는 문제점이 있었다. 그러면, 첨부 도면을 참조하여 종래의 문제점에 대해 상세히 설명하기로 한다.Recent advances in semiconductor technology have resulted in the introduction of a dual damascene process using low-k materials and copper (Cu) to speed up the wiring process in the manufacturing of semiconductor devices with 0.13㎛ or less. . The dual damascene process has the great advantage of reducing the resistance and speeding up the operation of the device, but resist resisting by ammonia contained in the low-k material used during the process. (Resist Poisoning) There was a problem that occurs. Then, the conventional problem will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 반도체 소자의 금속 배선 형성 방법에 따른 문제점을 설명하기 위한 제조공정 단면도이다.1A to 1C are cross-sectional views of a manufacturing process for explaining a problem according to a metal wiring forming method of a conventional semiconductor device.
먼저, 도 1a에 도시된 공정은, 반도체 기판(1) 위에 저유전(Low-k) 물질(2)을 증착한 후 상기 저유전(Low-k) 물질층(2)을 비아 식각(Via Etch)하여 트렌치(3)를 형성한 단계이다.First, in the process illustrated in FIG. 1A, a low-k material 2 is deposited on a semiconductor substrate 1, and then the etching of the low-k material layer 2 is via-etched. ) To form the trench 3.
이어서, 도 1b에 도시된 공정은, 도 1a의 구조물 위에 트렌치 현상(Photo)용 레지스터(4)를 도포한 단계이다.Subsequently, the process illustrated in FIG. 1B is a step of applying a trench 4 photo resist on the structure of FIG. 1A.
이어서, 도 1c에 도시된 공정은, 상기 트렌치 현상용 레지스터(4)을 노광 및 현상 공정을 실시한 단계이다.Subsequently, the process shown in Fig. 1C is a step in which the trench development register 4 is exposed and developed.
이때, 트렌치 현상 공정시 레지스트 포저닝 현상이 발생한다. 이러한 레지스트 포저닝 현상은 듀얼 다마신 공정에서 처음 발생된 현상으로, 레지스트의 현상 애시드 발생기(Photo Acid Generator: PAG)로부터 생성된 수소(H+)가 저유전(Low-k) 물질(2)에 흡착되어 있는 암모니아(NH3)와 산, 염기 반응을 통해 약산(NH4)으로 변하여 적절한 레지스트 반응을 하지 못하게 함으로써 발생한다. 이러한 레지스트 포저닝 현상에 의해, 현상 공정시 레지스트가 현상되지 못하고 남아있게 된다(A 부분). 여기서, 저유전물질(2)에 흡착된 암모니아(NH3)는 증착단계 또는 비아 식각 후 애싱(Ashing) 과정에서 흡착된 것이다.At this time, a resist focusing phenomenon occurs during the trench development process. This resist focusing phenomenon was first generated in the dual damascene process, and hydrogen (H +) generated from the resist photo acid generator (PAG) of the resist was adsorbed onto the low-k material (2). This is caused by changing to weak acid (NH4) through the reaction of ammonia (NH3), acid and base, which prevents proper resist reaction. By this resist focusing phenomenon, the resist remains undeveloped during the development process (part A). Here, ammonia (NH 3) adsorbed on the low dielectric material 2 is adsorbed in the ashing process after the deposition step or via etching.
도 2는 종래의 금속 배선 형성 방법에 의한 공정에서 레지스트 포저닝 현상에 의해 레지스트가 현상되지 않은 것을 나타낸 사진도이다. 사진에서도 볼 수 있듯이, 듀얼 다마신 공정의 레지스트 현상 공정에서 저유전물질에 함유된 암모니아(NH3)가 레지스터와 반응하여 포저닝됨으로써, 레지스트가 현상되지 않고 남아있는 것을 볼 수 있다(A 부분).2 is a photograph showing that a resist is not developed by a resist focusing phenomenon in a process by a conventional metal wiring forming method. As can be seen from the photograph, in the resist development process of the dual damascene process, ammonia (NH 3) contained in the low dielectric material is reacted with the resistor and deposited so that the resist remains undeveloped (part A).
그러나, 종래의 반도체 소자의 금속 배선 형성 방법에서는 이러한 레지스트 포저닝 현상을 제거하기 위해서 특수한 레지스트(Resist)를 사용하거나 듀얼 다마신 공정용 장치를 변경하는 등의 노력을 하고 있으나, 궁극적인 해결책은 되지 못하는 실정이다.However, in the conventional method of forming metal wirings of semiconductor devices, although efforts have been made to use a special resist or to change a device for a dual damascene process to remove such resist focusing, the ultimate solution is not an ultimate solution. I can't.
따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명은 산성 고분자 도포 및 베킹(Baking)을 통해 저유전물질(Low-k Material)을 처리함으로써 저유전물질 중에 존재하는 암모니아(NH3)를 근원적으로 제거하여 레지스트 포저닝(Resist Poisoning) 현상을 방지한 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the present invention is to treat ammonia (NH3) present in the low-k material by treating the low-k material through acidic polymer coating and baking (Baking). An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which is fundamentally removed to prevent resist poisoning.
도 1a 내지 도 1c는 종래기술에 따른 금속 배선 형성 방법의 문제점을 설명하기 위한 제조공정 단면도1a to 1c is a cross-sectional view of the manufacturing process for explaining the problem of the metal wiring forming method according to the prior art
도 2는 종래의 금속 배선 형성 방법에 의한 공정에서 레지스트 포저닝 현상에 의해 레지스트가 현상되지 않은 것을 나타낸 사진도Figure 2 is a photograph showing that the resist is not developed by the resist positioning phenomenon in the process by the conventional metal wiring forming method
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 제조공정 단면도3A to 3E are cross-sectional views of a manufacturing process for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 저유전물질 또는 층간절연막11 semiconductor substrate 12 low dielectric material or interlayer insulating film
13 : 트렌치 또는 콘택홀 14 : 산성 고분자 용액13: trench or contact hole 14: acidic polymer solution
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은,Metal wiring forming method of a semiconductor device of the present invention for achieving the above object,
반도체 기판 위에 유전상수가 3∼2 사이인 저유전물질로 이루어진 층간절연막을 형성하는 단계와,Forming an interlayer insulating film made of a low dielectric material having a dielectric constant between 3 and 2 on the semiconductor substrate,
상기 층간절연막을 제 1 마스크 패턴에 의해 소정 부분 식각하여 금속배선이 형성될 패턴을 형성하는 단계와,Forming a pattern on which a metal wiring is to be formed by etching the interlayer insulating layer by a partial mask using a first mask pattern;
상기 구조물 위에 산성 고분자 용액을 도포한 후 배킹(Baking)을 실시하는 단계와,Applying a polymer solution on the structure and then performing a backing;
상기 산성 고분자 용액을 제거하는 단계와,Removing the acidic polymer solution;
상기 구조물 위에 감광막을 도포한 후 노광 및 현상 공정으로 금속배선을 형성하기 위한 제 2 마스크 패턴으로 형성하는 단계를 포함하는 것을 특징으로 한다.And applying a photoresist film on the structure to form a second mask pattern for forming a metal wiring by an exposure and development process.
상기 저유전물질의 층간절연막은 플라즈마 화학 기상 증착(Plasma Enhanced Chemical Vaporization Deposition)법으로 증착하는 것을 특징으로 한다.The interlayer dielectric layer of the low dielectric material may be deposited by a plasma enhanced chemical vapor deposition method.
상기 배킹 방법으로 핫 플레이트(Hot Plate)를 사용하는 것을 특징으로 한다.A hot plate is used as the backing method.
상기 핫 플레이트의 온도는 0∼200℃의 범위를 갖는 것을 특징으로 한다.The temperature of the hot plate is characterized by having a range of 0 to 200 ℃.
상기 저유전물질은 유전상수(k)가 3∼2 사이의 물질인 것을 특징으로 한다.The low dielectric material is characterized in that the dielectric constant (k) is a material of 3 to 2.
상기 산성 고분자 용액은 산소(O2) 애싱(Ashing) 공정을 통하여 제거하는 것을 특징으로 한다.The acidic polymer solution is removed by an oxygen (O2) ashing process.
상기 금속배선은 구리(Cu)를 사용하는 것을 특징으로 한다.The metal wiring is characterized in that using copper (Cu).
상기 구조물 위에 구리(Cu)를 증착한 후 화학적기계연마(CMP) 공정으로 평탄화하는 단계를 추가로 포함하는 것을 특징으로 한다.After depositing copper (Cu) on the structure is characterized in that it further comprises the step of planarization by chemical mechanical polishing (CMP) process.
상기 구리(Cu)는 도금 방법으로 증착하는 것을 특징으로 한다.The copper (Cu) is characterized in that deposited by the plating method.
이하, 본 발명의 실시예에 관하여 첨부도면을 참조하면서 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
또, 실시예를 설명하기 위한 모든 도면에서 동일한 기능을 갖는 것은 동일한 부호를 사용하고 그 반복적인 설명은 생략한다.In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 제조공정 단면도이다.3A to 3E are cross-sectional views of manufacturing steps for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
먼저, 도 3a에 도시된 공정은, 반도체 기판(11) 위에 저유전물질인 층간절연막(12)을 플라즈마 화학 기상 증착(Plasma Enhanced Chemical Vaporization Deposition)법으로 증착한다.First, the process illustrated in FIG. 3A deposits an interlayer insulating film 12, which is a low dielectric material, on the semiconductor substrate 11 by plasma enhanced chemical vapor deposition deposition.
다음, 상기 층간절연막(12) 위에 감광막을 도포하여 금속배선을 형성하기 위한 마스크 패턴(도시하지 않음)을 형성한 후 노광을 하여 상기 층간절연막을 식각하여 트렌치(13)를 형성한 단계이다.Next, after forming a mask pattern (not shown) for forming a metal wiring by applying a photosensitive film on the interlayer insulating film 12, the step of exposing and etching the interlayer insulating film to form a trench (13).
이어서, 도 3b에 도시된 공정은, 도 3a의 구조물 위에 산성 고분자 용액(13)을 도포한 후 핫 플레이트(Hot Plate)에서 배킹(Baking)을 실시하는 단계이다. 이때, 배킹 공정에 의해 이후의 트렌치 현상 공정에서 레지스트 부위로 확산되어질 암모니아(NH3)가 미리 확산되어 고분자 용액(13) 속의 산과 반응된다.여기서, 상기 산성 고분자 용액(13)에서, 산성 고분자 물질로는 일반적으로 사용되는 노보락(Novorak)계열 또는 폴리하이드로시스틸렌(polyhydorxystylene)계열의 고분자에 유기산 또는 무기산을 첨가한 물질을 이용한다. 이때, 유기산으로는 일반적으로 사용될 수 있는 카르복실산(carboxylic acid), 설폰산(sulfonic acid) 등을 들 수 있으며, 무기산으로는 황산, 인산 등을 들 수 있다.Subsequently, the process illustrated in FIG. 3B is a step of applying an acidic polymer solution 13 onto the structure of FIG. 3A and then performing a backing on a hot plate. At this time, the ammonia (NH 3) to be diffused to the resist site is previously diffused by the backing process to react with the acid in the polymer solution 13. Here, in the acidic polymer solution 13, the acidic polymer material is used. In general, a material in which an organic acid or an inorganic acid is added to a polymer of a novorak-based or polyhydroxystylene-based polymer is generally used. In this case, examples of the organic acid may include carboxylic acid, sulfonic acid, and the like, which may be generally used. Examples of the inorganic acid may include sulfuric acid and phosphoric acid.
이어서, 도 3c에 도시된 공정은, 산소(O2) 애싱(Ashing) 공정을 통하여 상기 고분자 용액(13)을 제거한 단계이다.Subsequently, the process illustrated in FIG. 3C is a step of removing the polymer solution 13 through an oxygen (O 2) ashing process.
이어서, 도 3d에 도시된 공정은, 도 3c의 구조물 위에 감광막(14)을 도포한 단계이다.Subsequently, the process shown in FIG. 3D is a step of applying the photosensitive film 14 on the structure of FIG. 3C.
끝으로, 도 3e에 도시된 공정은, 상기 감광막(14)을 노광 및 현상 공정으로 금속배선을 형성하기 위한 마스크 패턴(14)으로 형성한 단계이다. 이때, 레지스트의 현상 애시드 발생기(PAG)로부터 생성된 수소(H+)는 현상 공정시 상기 저유전물질(12)에 흡착되어 있는 암모니아(NH3)와 반응을 하지 않고 정상적으로 작용하여 레지스트 포저닝(Resist Poisoning) 현상을 발생시키지 않는다.Finally, the process shown in FIG. 3E is a step in which the photosensitive film 14 is formed of a mask pattern 14 for forming metal wirings by an exposure and development process. At this time, hydrogen (H +) generated from the developing acid generator (PAG) of the resist does not react with ammonia (NH 3) adsorbed to the low dielectric material 12 during the developing process, thereby acting normally. ) Does not cause a phenomenon.
이후, 도 3e의 구조물 위에 구리(Cu)를 도금(Electroplating) 방법으로 증착한다. 다음, 상기 구리(Cu)를 화학적기계연마(Chemacal Mechanical Polishing: CMP) 공정으로 상기 층간절연막(12)이 드러날 때까지 연마하여 표면을 평탄화함으로써 구리배선을 완성한다.Thereafter, copper (Cu) is deposited on the structure of FIG. 3E by an electroplating method. Next, the copper (Cu) is polished by a chemical mechanical polishing (CMP) process until the interlayer insulating film 12 is exposed to planarize the surface to complete copper wiring.
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 금속 배선 형성 방법에 의하면, 저유전물질을 이용한 듀얼 다마신 공정에서 발생하는 레지스트 포저닝(Resist Poisoning) 현상을 산성 고분자의 도포 및 베킹(baking)을 이용하여 제거시킴으로써, 수율을 향상시키고 원가를 절감할 수 있는 효과가 있다.As described above, according to the method for forming a metal wiring of the semiconductor device according to the present invention, the resist poisoning phenomenon generated in the dual damascene process using a low dielectric material is coated and baked with an acidic polymer. By removing it, it is possible to improve the yield and reduce the cost.
또한, 듀얼 다마신 공정을 이용하는 0.18㎛급 이하의 트렌치를 이용한 소자개발 및 생산 시 포토리소그래피(Photolithography) 공정의 안정화로 수율 향상 및 원가 절감의 효과를 얻을 수 있다.In addition, the stabilization of the photolithography process in the development and production of devices using a trench of 0.18㎛ or less using a dual damascene process can improve yield and reduce costs.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07249572A (en) * | 1994-01-18 | 1995-09-26 | Matsushita Electric Ind Co Ltd | Formation of fine pattern |
| KR0172237B1 (en) * | 1995-06-26 | 1999-03-30 | 김주용 | Method of manufacturing micropattern of semiconductor device |
| KR19990060922A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing Method of Semiconductor Device |
| KR20000056081A (en) * | 1999-02-12 | 2000-09-15 | 윤종용 | METHOD OF MAKING A LOW-k INTERMETAL DIELECTRIC FOR SEMICONDUCTOR DEVICES |
| US6174816B1 (en) * | 1998-09-03 | 2001-01-16 | Micron Technology, Inc. | Treatment for film surface to reduce photo footing |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07249572A (en) * | 1994-01-18 | 1995-09-26 | Matsushita Electric Ind Co Ltd | Formation of fine pattern |
| KR0172237B1 (en) * | 1995-06-26 | 1999-03-30 | 김주용 | Method of manufacturing micropattern of semiconductor device |
| KR19990060922A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing Method of Semiconductor Device |
| US6174816B1 (en) * | 1998-09-03 | 2001-01-16 | Micron Technology, Inc. | Treatment for film surface to reduce photo footing |
| KR20000056081A (en) * | 1999-02-12 | 2000-09-15 | 윤종용 | METHOD OF MAKING A LOW-k INTERMETAL DIELECTRIC FOR SEMICONDUCTOR DEVICES |
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