KR200298537Y1 - Clock generator - Google Patents

Abstract

The present invention relates to a clock generator, comprising a flip-flop and inverting means for inverting the latch and the output signal of the latch. Data and an internal clock signal are input to the flip-flop to generate a second output signal that is a complementary signal between the first output signal and the first output signal. The second output signal is also fed back to the data input terminal. The latch consists of a first AND gate and a second AND gate. The first output signal is input to the first AND gate, and generates a first external clock signal. The inverted signal of the second output signal and the first external clock signal is input to the second AND gate to generate a second external clock signal, which is a complementary signal of the first external clock signal. The present invention connects a latch to the output terminal of the flip-flop, and inverts and delays the external clock signal and the external clock bar signal output from the latch for a predetermined time to feed back to the input terminal of the latch, thereby providing an external clock signal and an external clock bar. This has the effect of preventing a section in which the signals all have high level logic values.

Description

Clock generator

The present invention relates to a clock generator, and more particularly to a clock generator for generating an external clock signal having a frequency of 1/2 of the internal clock signal.

The clock signal is an essential signal in a digital system. This clock signal is used as a reference signal to match the operation of each component constituting the system or to determine the operation timing. In most cases, the main clock signal exists, and the frequency of the main clock signal is adjusted to generate and use a sub clock signal having a frequency necessary for operation of each component.

The degree of integration of semiconductor technology has been fully developed, and the data storage capacity of a memory has been greatly increased. Therefore, the amount of data to be processed in a microprocessor used as a central processing unit has also been greatly increased. Therefore, it is recognized that improving the operation speed of a digital system is important at present. In addition to the microprocessor for the central processing unit, in recent years, the use of the MPEG decoder (DSP) or digital signal processing (DSP), which processes digital video and audio signals, has been greatly increased. Often need to be processed in real time. In order to process digitalized video and audio signals in real time, it is necessary to drive a system with a clock signal of a very high frequency. In addition, a stable clock signal is also very important for achieving a stable operation speed.

1 is a circuit diagram illustrating a conventional clock generator, which is implemented by using a de-flop. As shown in Fig. 1, the de-flop 11 has a clock input terminal, a data input terminal, and a reset terminal. The internal clock signal CLK_IN is input to the clock signal input terminal, and the reset signal / RST of the active low is input to the reset terminal.

Also, the flip-flop 11 of FIG. 1 has two data output terminals Q (/ Q), and the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT, which are complementary signals, are provided at the two output terminals. Is output. The external clock bar signal / CLK_OUT is fed back to the data input terminal D of the flip-flop 11. Accordingly, it can be seen that the logic value of the external clock signal CLK_OUT is inverted at every rising edge of the internal clock signal CLK_IN. That is, the ratio of the frequency of the internal clock signal CLK_IN and the frequency of the external clock signal CLK_OUT is 2 Means: 1.

The operation characteristic of such a conventional clock generator is shown in FIG. In FIG. 2, reference numeral 1 denotes an internal clock signal CLK_IN, reference numeral 2 denotes a reset signal / RST, reference numeral 3 denotes an external clock signal CLK_OUT, and reference numeral 4 denotes an external clock bar signal / CLK_OUT. . As shown in FIG. 2, when the reset signal / RST is at a low level while the internal clock signal CLK_IN is input, the de- flip-flop is reset to have an initial value of logic value 0. At this time, when the internal clock signal CLK_IN transitions to a high level, the external clock signal CLK_OUT also transitions to a high level, and the external clock bar signal / CLK_OUT transitions to a low level. Since the low level external clock bar signal / CLK_OUT is input to the data input terminal, the external clock signal CLK_OUT output at the next rising edge of the internal clock signal CLK_IN is at a low level. / CLK_OUT) is high level.

However, in practice, the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT output from the flip-flop are not completely complementary. As shown in FIG. 2, some delay occurs when the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT transition. This delay is caused by a latch or the like constituting the internal circuit of the de-flop flop. For this reason, there is a section in which both the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT are low level or high bell. As such, when a section in which two signals to be complementary have the same logic value occurs, a serious error occurs in a system operating in synchronization with the two signals. In particular, in a section in which both signals are high level, a system operating by both signals is activated (or deactivated) and collisions between systems occur.

Therefore, the present invention connects the latch to the output terminal of the flip-flop and inverts and delays the external clock signal and the external clock bar signal output from the latch for a predetermined time and feeds it back to the input terminal of the latch, thereby providing an external clock signal and an external clock bar signal. The purpose of this is to ensure that no intervals with all high level logic values occur.

1 is a circuit diagram showing a conventional clock generator.

2 is a timing diagram showing the operation characteristics of the conventional clock generator shown in FIG.

3 is a circuit diagram showing a clock generator according to the present invention.

4 is a timing diagram showing the operation characteristics of the clock generator according to the present invention shown in FIG.

Explanation of symbols on the main parts of the drawings

11, 21: D flip-flop 22, 23: End gate

INV1, INV2: Inverter CLK_IN: Internal clock signal

CLK_OUT: external clock signal / CLK_OUT: external clock bar signal

/ RST: reset signal

The present invention for this purpose comprises a flip-flop and inverting means for inverting the latch and the output signal of the latch. Data and an internal clock signal are input to the flip-flop to generate a second output signal that is a complementary signal between the first output signal and the first output signal. The second output signal is also fed back to the data input terminal. The latch consists of a first AND gate and a second AND gate. The first output signal is input to the first AND gate, and generates a first external clock signal. The inverted signal of the second output signal and the first external clock signal is input to the second AND gate to generate a second external clock signal, which is a complementary signal of the first external clock signal.

Referring to Figures 3 and 4 a preferred embodiment of the present invention made as described above are as follows. 3 is a circuit diagram illustrating a clock generator according to the present invention, and FIG. 4 is a timing diagram illustrating an operation characteristic of the clock generator according to the present invention shown in FIG. 3.

As shown in Fig. 3, the de-flip flop 21 has a clock input terminal, a data input terminal and a reset terminal. The internal clock signal CLK_IN is input to the clock signal input terminal, and the reset signal / RST of the active low is input to the reset terminal.

The flip-flop 21 of FIG. 3 also has two data output terminals Q / Q. The complementary signal output through this output terminal is input to a latch composed of two end gates 22 and 23. First, the Q signal of the flip-flop is input to the AND gate 22, and the / Q signal is input to the other AND gate 23.

The output signals of the respective AND gates 22 and 23 are the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT. The external clock signal CLK_OUT output from the AND gate 22 is inverted by the inverter INV1 and fed back to another input terminal of the AND gate 23. The external clock bar signal / CLK_OUT output from the AND gate 23 is also inverted by the inverter INV2 and fed back to another input terminal of the AND gate 22.

At this time, the two inverters INV1 and INV2 generate a predetermined time delay as well as simply inverting the signal. That is, when the output signal of the AND gate 22 is inverted and fed back to the input of the AND gate 23, there is a delay time, and the output signal of the AND gate 23 is inverted to input the AND gate 22. There is also some delay when fed back. Therefore, the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT are affected by the time delay generated by these two inverters INV1 and INV2.

When the reset signal / RST becomes low level and the flip-flop is initialized, the Q signal is high level and the / Q signal is low level. At this time, the external clock signal CLK_OUT is at a high level and the external clock bar signal / CLK_OUT is at a low level. The low level external clock bar signal / CLK_OUT is input to the data input terminal D of the flip-flop 21 but does not affect the output until a transition of the internal clock signal CLK_IN occurs.

In this state, when the reset signal / RST becomes high level and the internal clock signal CLK_IN also transitions to high level, the external clock signal CLK_OUT becomes low level by the low level signal of the data input terminal D. The external clock bar signal / CLK_OUT goes high. Therefore, the external clock signal CLK_OUT, which is an output signal of the AND gate 22, is at a low level.

Since the AND gate 23 receives a high-level / Q signal, the logic value of the output signal is determined by the output signal of the inverter INV1, which is another input signal. At this time, since the output signal of the inverter INV1 is at the high level, the external clock bar signal / CLK_OUT which is the output signal of the AND gate 23 is at the high level.

The above description describes a simple logic change of the latch according to the output of the flip-flop, and the change of the output characteristic according to the delay action of the inverters INV1 and INV2 will be described in detail as follows.

First, when one of the inputs of the two-input and gate is delayed slightly by the predetermined delay means than the other input, the delay means is not affected by the delay means depending on the direction in which the level of the input signal transitions. That is, in the above case, when the input signal transitions to the high level, the AND gate is delayed by the delay time of the delay means and then the high level signal is output. On the contrary, when the input signal transitions to the low level, the low level signal is output simultaneously with the level change of the input signal without being affected by the delay means. However, the delay in the end gate is ignored.

Such characteristics are well illustrated in FIG. 4. In Fig. 4, reference numeral 1 denotes an internal clock signal CLK_IN, reference numeral 2 denotes a reset signal / RST, and reference numerals 3 and 4 denote Q and / Q signals, respectively. (5) is an output signal of the inverter INV1, and (6) is an output signal of the inverter INV2. (7) and (8) are the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT, respectively. The signals from (1) to (4) of FIG. 4 are identical to the output characteristics of the clock generator of FIG. 1, and there is a section in which the output signals Q (/ Q) are all at a high level.

However, referring to the external clock signal CLK_OUT and the external clock bar signal / CLK_OUT shown in FIGS. 7 and 8, the external clock signal CLK_OUT is formed at the second rising edge t2 of the internal clock signal CLK_IN. ) Transitions to the low level and the external clock bar signal / CLK_OUT transitions to the high level. At this time, the external clock signal CLK_OUT transitions to the low level normally (at the same time as the input) without being influenced by the delay means, but the external clock bar signal / CLK_OUT is sufficiently delayed by the delay effect and then transitions to the high level. It can be seen that the high level section of the clock signal CLK_OUT and the high level section of the external clock bar signal / CLK_OUT do not overlap.

The present invention connects a latch to the output terminal of the flip-flop, inverts and delays the external clock signal and the external clock bar signal output from the latch for a predetermined time, and feeds the external clock signal and the external clock bar signal back to the latch input terminal. All sections with logic values of high level should not occur.

Claims (5)

In a clock generator, A flip-flop for inputting data and an internal clock signal, generating a second output signal that is a complementary signal between the first output signal and the first output signal, and the second output signal being input to the data input terminal; A first AND gate receiving the first output signal and generating a first external clock signal; And a second AND gate configured to receive an inverted signal of the second output signal and the first external clock signal and to generate a second external clock signal that is a complementary signal of the first external clock signal. The clock generator of claim 1, wherein the second external clock signal is input to the first and gate. The clock generator as set forth in claim 1, wherein said first external clock signal is inverted by a first inverting means having a predetermined delay time. The clock generator as set forth in claim 1, wherein said second external clock signal is inverted by a second inverting means having a predetermined delay time. The clock generator of claim 1, wherein the de-flip-flop has an initial value of logic zero.