KR200234108Y1 - Estée class data transfer interface - Google Patents

Abstract

The present invention relates to an interface device that transmits data values of V5 positions of multiple T1 / E1 signals input to STS-1 frames to a processor unit, and generates a write address by encoding the input V5 windows into 5 bits. The present invention provides an STS-1 data transfer interface capable of minimizing a logic amount of the interface by storing data in RAM according to the write address.

The configuration of the present invention is an STS-1 composed of an 8-bit TUG-2 input in an interface for transmitting data values of the V5 positions of several T1 / E1 signals inputted at every STS-1 frame to the processor unit. A window generator 50 for interpreting V1 and V2 values from class data, finding a V5 position, and outputting a 28-bit window signal; A write address generator 60 which receives a signal output from the window generator 50 and generates and outputs a write address address corresponding to the value; Receives a write address signal output from the write address generator 70, receives and stores STS-1 data at a corresponding address, and stores data of a corresponding address according to a read address designated by the processor unit 80. It comprises a RAM 70 for outputting to the processor unit 80.

Description

Estée class data transfer interface

The present invention relates to an STS-1 data transfer interface. More specifically, the present invention relates to processing of data values of V5 positions of several T1 / E1 signals that are input in varying STS-1 frames. An interface for delivering to a unit, comprising: creating a write address using V5 windows and storing the data in accordance with the write address when storing data in a random access memory (RAM). The present invention relates to an STS-1 data transfer interface capable of minimizing the amount of logic.

In general, a shelf of a communication device includes a processor unit and a general unit that control a control function. The general units transmit performance data to the processor unit so that the processor unit always performs a performance check. Do it.

Known data transmission units are E1 and T1, and there are seven T1 data transmission units, TUG2, and four TUG2, STS-1. The STS-1 data transmission line When transmitting the data containing the performance from the general unit to the, it is necessary to determine which channel of the T1 level unit in the STS-1 class, and find the value and deliver the corresponding performance data value efficiently. Should be.

By the way, the position of the 28 channels in the above can be known as V5, which can be found through V1 and V2, which represent the pointer of V5.

Hereinafter, the STS-1 data transfer interface of the prior art will be described with reference to the accompanying drawings.

As shown in Figure 1, the configuration of the STS-1 data transfer interface of the prior art,

A window generator (10) for interpreting V1 and V2 values from STS-1 grade data composed of 8 bit TUG-2 inputs, finding the V5 position and outputting a 28-bit window signal;

A data latch unit 20 which receives STS-1 level data and a window signal output from the window generator 10 and latches data corresponding to a window position;

The data selector 30 which receives the signal output from the data latch unit 20, selects data corresponding to the read address signal input from the processor unit 40, and outputs the corresponding data to the processor unit 40. Characterized in that the made up.

The operation of the prior art STS-1 V5 data transfer interface is as follows.

The window SINSO 10 receives 8 bits of STS-1 level data composed of TUG-2, analyzes the V1 and V2 values, finds the V5 position, and outputs a 28-bit window signal.

The position of V5 is a value changed every multi-frame, and the number is 28.

The data latch unit 20 receives 8-bit STS-1 level data and a window signal output from the window generator 10 and latches data corresponding to the window position.

At this time, since there are 8 bits of data in 28 T1 channels, a total of 224 data are generated.

The data selector 30 receives a signal output from the data latch unit 20, selects the corresponding data DATA according to the read address signal RD_AD input from the processor unit 40, and then selects 8. Output to the processor unit 40 via a bit bus.

The prior art STS-1 data transfer interface is implemented using a Programmable Gate Array (FPGA), which is a chip for designing and inserting digital logic. It is a device that can modify internal logic at any time.

After designing the digital logic as described above, the paths of the logic must be connected to insert them into the FPGA, and each algorithm has a corresponding algorithm according to each FPGA type. This is called routing.

However, in the STS-1 data transfer interface of the related art operating as described above, when routing lines having 224 data values generated by the data latch unit 20, each routing passage should be used. In addition, since the number of multiplexers used to select 224 data in the data selector 30 increases, the overall circuit size increases and becomes complicated.

Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and in an interface for transmitting data values of V5 positions of several T1 / E1 signals that are input in varying STS-1 frames to a processor unit, The present invention provides an STS-1 data transfer interface capable of minimizing a logic amount of the interface by creating a write address using V5 windows and storing data according to the write address when storing data in RAM.

1 is a block diagram applying the STS-1 data transfer interface according to the prior art;

2 is a block diagram to which the STS-1 data transfer interface is applied according to an embodiment of the present invention;

3 is a detailed circuit diagram to which an address generator is applied in FIG. 2;

4 is a diagram illustrating a 28-bit signal value address output from the window generator in FIG. 2.

The present invention for achieving the above object generates a write address that receives the position signal of V5 output from the window generating means of the T1 / E1 signal and generates a write address address corresponding to the value and outputs it to the storage means. In the data interface apparatus provided with the means, the write address generating means receives the signal output from the window generating means and generates and outputs a first bit value which is the least significant bit of the write address address corresponding to the value. A first write address generator; A second write address generation unit which receives the signal output from the window generating means and generates and outputs a second bit value which is the next lower bit of the write address address corresponding to the value; A third write address generation unit which receives a signal output from the window generating means and generates and outputs a third bit value that is a difference lower bit of the write address address corresponding to the value; A fourth write address generation unit which receives a signal output from the window generating means and generates and outputs a fourth bit value that is a next higher bit of the write address address corresponding to the value; It provides an STS-1 data transfer interface including a fifth write address generator which receives a signal output from the window generating means and generates and outputs a fifth bit value that is the most significant bit of the write address address corresponding to the value. .

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

As shown in Figure 2, the configuration of the STS-1 data transfer interface according to an embodiment of the present invention is as follows.

The interface device for transferring the data values of the V5 positions of the several T1 / E1 signals inputted at every STS-1 frame to the processor unit

A window generator 50 for analyzing the V1 and V2 values from the input STS-1 data consisting of 8-bit TUG-2, finding the V5 position, and outputting a 28-bit window signal;

A write address generator 60 which receives a signal output from the window generator 50 and generates and outputs a write address address corresponding to the value;

Receives a write address signal output from the write address generator 70, receives and stores STS-1 data at a corresponding address, and stores data of a corresponding address according to a read address designated by the processor unit 80. It comprises a RAM 70 for outputting to the processor unit 80.

The configuration of the write address generator 70 is

A write address first generator 61 which receives the signal output from the window generator 50 and generates and outputs the lowest first bit value of the write address address corresponding to the value;

A write address second generator 62 which receives a signal output from the window generator 50 and generates and outputs a second bit value that is the next lower bit of the write address address corresponding to the value;

A write address third generator 63 which receives a signal output from the window generator 50 and generates and outputs a third bit value which is a difference lower bit of the write address address corresponding to the value;

A write address fourth generator 64 which receives a signal output from the window generator 50 and generates and outputs a fourth bit value that is the next higher bit of the write address address corresponding to the value;

And a write address fifth generator 65 which receives the signal output from the window generator 50 and generates and outputs a fifth bit value that is the most significant bit of the write address address corresponding to the value.

The first write address generating means includes a first bit signal, a third bit signal, a fifth bit signal, a seventh bit signal, a ninth bit signal, and a first signal among the signals output from the window generating means using an or gate. 11-bit signal, 13-bit signal, 15-bit signal, 17-bit signal, 19-bit signal, 21-bit signal, 23-bit signal, 25-bit signal, 27-bit signal is input as logical '1' Is configured to output a signal of logic value '1'.

The second write address generating means includes a second bit signal, a third bit signal, a sixth bit signal, a seventh bit signal, a tenth bit signal, and a first signal among the signals output from the window generating means using an or gate. 11-bit signal, 14-bit signal, 15-bit signal, 18-bit signal, 19-bit signal, 22-bit signal, 23-bit signal, 26-bit signal, 27-bit signal are input as logical '1'. Is configured to output a signal of logic value '1'.

The third write address generating means may include a fourth bit signal, a fifth bit signal, a sixth bit signal, a seventh bit signal, a twelfth bit signal, and a fourth signal among the signals output from the window generating means using an or gate. When the 13-bit signal, 14th bit signal, 15th bit signal, 20th bit signal, 21st bit signal, 22nd bit signal, 23rd bit signal, 28th bit signal is input as logical '1', the logic value ' And output a signal of 1 '.

The fourth write address generating means may include an eighth bit signal, a ninth bit signal, a tenth bit signal, an eleventh bit signal, a twelfth bit signal, and an eighth signal among the signals output from the window generating means using an or gate. When the 13-bit signal, the 14th bit signal, the 15th bit signal, the 24th bit signal, the 25th bit signal, the 26th bit signal, the 27th bit signal, and the 28th bit signal are input as logical '1', the logic value ' And output a signal of 1 '.

The fifth write address generating means is configured to generate a sixteenth bit signal, a seventeenth bit signal, an eighteenth bit signal, a nineteenth bit signal, a twentieth bit signal, and an eighth bit from among the signals output from the window generating means using an or gate. When the 21-bit signal, the 22nd bit signal, the 23rd bit signal, the 24th signal, the 25th bit signal, the 26th bit signal, the 27th bit signal, and the 28th bit signal are input as logical '1', the logic value ' And output a signal of 1 '.

The operation of the embodiment of the present invention made as described above is as follows.

The present invention transmits the data values of the V5 positions of the several T1 / E1 signals that are inputted varying for each STS-1 frame to the processor unit. The window generating unit 50 includes an STS- composed of 8-bit TUG-2 inputs. The V1 and V2 values are interpreted from the first-class data, the V5 position is detected, and a 28-bit window signal is output.

The write address generator 60 receives the signal output from the window generator 50 and generates and outputs a 5-bit write address address corresponding to the value, and the RAM 70 generates the write address. It receives the write address signal outputted from the unit 70, receives and stores the STS-1 level data at the corresponding address, and stores the data of the corresponding address according to the read address RD_AD designated by the processor unit 80. Output to the processor unit 80.

Hereinafter, the operation of the write address generator 60 will be described in detail with reference to FIGS. 3 and 4.

First, the address of the 28-bit window signal output from the window generator 50 is determined for each signal in the address generator 60, as shown in FIG.

For example, the write address generator 60 receives the address when the signal of 'V5_WIN_11', which is the signal D1 of the first bit, of the window signal outputted from the window generator 50 is input high. A value of 00001 'should be output. A process of outputting this value will be described with reference to FIG. 3.

3, the first write address generator 61, the second write address generator 62, the third write address generator 63, the fourth write address generator 64, and the fifth write address generator are shown. The unit 65 outputs values from the least significant bit to the most significant bit of the address using the or gates, respectively.

That is, when the signal of 'V5_WIN_11' which is the first bit signal D1 of the window signal is input as logical '1', the address '00001' is output, so the output signal of the first write address generator 61 is logical '1'. ', And the output values of the remaining write address generators 62, 653, 64, and 65 are logical' 0 '.

The input signal of the first write address generator 61 has a signal of 'V5_WIN_11', which is the signal D1 of the first bit of the window signal, and the inputs of the remaining write address generators 6162, 63, 64, and 65. Since there is no signal, the output value of the write address generator 60 by the window signal 'V5_WIN_11' becomes '00001'.

In the same manner as described above, the write address generator 60 generates and outputs respective address values for the corresponding window signals.

On the other hand, when the 28 window signals are not input, the output signal of the write address generator 60 becomes '00000'.

As described above, when the write address generation unit 60 generates and outputs each address value for each window signal, the RAM 70 outputs the 8-bit data. What is necessary is just to output the data corresponding to the said address.

In addition, since the current commercially available FPGAs often have a built-in RAM, the RAM 70 can be substituted, so that a separate RAM is not required.

In this way, the data values of the V5 positions of several T1 / E1 signals inputted by changing STS-1 frames can be transmitted to the processor unit, and only 8 data lines can be used to perform a desired function. Routing can be facilitated.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common knowledge in the technical field to which the present invention pertains that various substitutions, conversions, and changes can be made without departing from the technical idea of the present invention. It will be apparent to those who have

Accordingly, the present invention operating as described above, in the interface for transmitting the data value of the V5 position of the several T1 / E1 signals inputted at every STS-1 frame to the processor unit, using the V5 windows to write the write address By making the data and storing the data in the RAM according to the write address, the logic amount of the interface can be greatly reduced and the routing of the FPGA can be easily performed.

Claims (6)

A data interface apparatus comprising: a write address generating means for receiving a position signal of V5 outputted from a window generating means of a T1 / E1 signal, generating a write address address corresponding to the value, and outputting the write address address to the storage means; The recording address generating means is A first write address generator which receives the signal output from the window generating means and generates and outputs a first bit value which is the least significant bit of the write address address corresponding to the value; A second write address generation unit which receives a signal output from the window generating means and generates and outputs a second bit value which is the next lower bit of the write address address corresponding to the value; A third write address generation unit which receives a signal output from the window generating means and generates and outputs a third bit value, which is a difference lower bit of the write address address corresponding to the value; A fourth write address generation unit which receives the signal output from the window generating means and generates and outputs a fourth bit value which is the next higher bit of the write address address corresponding to the value; And a fifth write address generator configured to receive the signal output from the window generating means and generate and output a fifth bit value, which is the most significant bit of the write address address corresponding to the value, to output the STS-1 data. interface. The method of claim 1, wherein the first write address generator, A first bit signal, a third bit signal, a fifth bit signal, a seventh bit signal, a ninth bit signal, an eleventh bit signal, a thirteenth bit signal, a fifteenth bit signal, When the 17-bit signal, the 19-bit signal, the 21-bit signal, the 23-bit signal, the 25-bit signal, the 27-bit signal is input as a logical '1', the signal of the logical value '1' is outputted. STS-1 data passing interface. The method of claim 1, wherein the second write address generator, A second bit signal, a third bit signal, a sixth bit signal, a seventh bit signal, a tenth bit signal, an eleventh bit signal, a fourteenth bit signal, a fifteenth bit signal, and a fifth bit signal among the signals output from the window generating means. When the 18-bit signal, 19th bit signal, 22nd bit signal, 23rd bit signal, 26th bit signal, and 27th bit signal are input as logical '1', the signal of logical value '1' is output. STS-1 data passing interface. The method of claim 1, wherein the third write address generation unit, Fourth bit signal, fifth bit signal, sixth bit signal, seventh bit signal, twelfth bit signal, thirteenth bit signal, fourteenth bit signal, fifteenth bit signal, STS-1 data characterized by outputting a signal of logic value '1' when a 20-bit signal, a 21-bit signal, a 22nd bit signal, a 23rd bit signal, and a 28th bit signal are input as logical '1'. Forwarding interface. The method of claim 1, wherein the fourth write address generator, The eighth bit signal, the ninth bit signal, the tenth bit signal, the eleventh bit signal, the twelfth bit signal, the thirteenth bit signal, the fourteenth bit signal, the fifteenth bit signal, and the eighth bit signal among the signals output from the window generating means. STS-1 data characterized by outputting a signal of logic value '1' when a 24 bit signal, a 25th bit signal, a 26th bit signal, a 27th bit signal, or a 28th bit signal is input as logical '1' Forwarding interface. The method of claim 1, wherein the fifth write address generator is 16th bit signal, 17th bit signal, 18th bit signal, 19th bit signal, 20th bit signal, 21st bit signal, 22nd bit signal, 23rd bit signal, STS-1 data characterized by outputting a signal of logic value '1' when a 24 bit signal, a 25th bit signal, a 26th bit signal, a 27th bit signal, and a 28th bit signal are input as logical '1' Forwarding interface.