KR19990055985A - Elastic buffer circuit in synchronous transmission device - Google Patents

Abstract

The present invention can reduce the overall circuit size when processing several types of TU pointer as one elastic buffer and can be selected and operated according to the type of the TU so that the transmission delay can be set to the minimum size In order to implement an operation state according to a predetermined action, an input data terminal DAI and a write enable input terminal WE enabling recording of the input data are inputted by a write address W-ADDRESS. A buffer that writes data and is read and output by a read address (R-ADDRESS), a write address generator that generates a write address signal in response to an input of a PI payload terminal indicating an effective load portion of the input data, and output data For generating the write address signal in accordance with the input of the PG payload terminal 122 representing the effective load portion of the And a phase detector configured to detect a phase of the output of the write address generator and the lead address generator by adjusting a protection area according to a signal input to the protection size stage GS.

Description

Elastic buffer circuit in synchronous transmission device

The present invention relates to an elastic buffer for point processing of a synchronous transmission device. In particular, the present invention relates to an elastic buffer circuit in a synchronous transmission device that can control an active area of an elastic buffer when processing a plurality of dependent signals into one elastic buffer. It is about.

In general, a synchronous transmission device (hereinafter referred to as "SDH") uses Point Justification in order to prevent loss of data transfer between different clocks. Select the repetition frequency slightly higher than the frequency of the original signal, and put an invalid bit called a stuffer pulse that does not transmit information to the synchronization signal if necessary to stop reading of the asynchronous signal for one bit and correct the phase deviation. This method has been used to cope with the similar synchronization situation in the synchronous network. The pointer processing function of the SDH system includes the pointer interpreter, the elastic store, and the pointer generation. It consists of three elements. The present invention relates to the elastic buffer, which is similar to the example of FIG. The input data terminal DAI and the write enable input terminal WE enable recording of the input data to implement an operation state according to a predetermined action, and have a write address W-. A write address in accordance with the input of the buffer 101 which records the input data by ADDRESS and is read and output by the R-ADDRESS and the PI payload terminal 121 indicating the effective load portion of the input data. A write address generator 105 for generating a signal, a read address generator 105 for generating a write address signal in response to an input of a PG payload terminal 122 indicating an effective load portion of the output data, and the write address generator ( 103 and a phase detector 107 for detecting the phase of the output of the lead address generator 105. However, such a configuration is generally a single subordinate. The Guard area of the buffer 101 processing (TU: Tributary Unit or less) is allocated to two fixed bytes, and its active area is defined as the example in Table 1 below. It depends on the type.

AU type TU type active regionsize quard regionsize ES size (number of word) AU3 TU11 ≥ 3 byte ≥ 2 byte 10 TU12 ≥ 3 byte ≥ 2 byte 10 TU2 ≥ 4 byte ≥ 2 byte 10 AU4 TU11 ≥ 3 byte ≥ 2 byte 10 TU12 ≥ 3 byte ≥ 2 byte 10 TU2 ≥ 4 byte ≥ 2 byte 12 TU3 ≥ 8 byte ≥ 2 byte 20

In the above example, when one type of TU point is processed as one elastic buffer 101, the size of the buffer 101 may be set to a minimum size in consideration of the size of the circuit and the transmission delay. In the case of processing a TU of a kind, the largest size is generally selected. In this case, there is a problem of transmission delay because the active area becomes large.

Therefore, the object of the present invention is to reduce the overall circuit size when processing several types of TU pointer as one elastic buffer and to select the lowest value according to the type of the TU to set the transmission delay to the minimum size To provide a circuit that can be used.

1 is a circuit diagram showing an elastic buffer of a conventional synchronous transmission device

Figure 2 is an elastic buffering circuit diagram that can vary the protection area of the embodiment of the present invention

3 is a detailed circuit diagram of the phase detector of FIG.

4A to 4D are operation waveform diagrams of an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A detailed description of a preferred embodiment of the present invention will now be described with reference to the accompanying drawings. In the following, reference numerals are given to components of each drawing, even though the same components are shown in different drawings. Note that they have the same sign. In describing the present invention, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or a chip designer, and the definitions should be made based on the contents throughout the present specification.

Figure 2 is an elastic buffering circuit diagram that can vary the protection area used in the embodiment of the present invention,

The input data terminal DAI and the write enable input terminal WE enable recording of the input data in order to implement an operation state according to a predetermined action. The input data is input by the write address W-ADDRESS. A buffer 101 which is written and read by the read address R-ADDRESS, and

A write address generator 103 for generating a write address signal in response to an input of a PI payload terminal 121 representing an effective load portion of the input data;

A lead address generator 105 for generating a write address signal in response to an input of the PG payload stage 122 indicating an effective load portion of the output data;

A phase detector 107 for detecting the phases of the outputs of the light address generator 103 and the lead address generator 105 by adjusting the protection area according to a signal input to the protection size stage GS;

And a means (110, 111) for adding each of the outputs of the write address generator 103 and the read address generator 105 by one to provide the write address generator 103 and the read address generator 105 again.

3 is a detailed circuit diagram of the phase detector 107 of FIG.

A comparator 306 for comparing whether the values of the outputs of the write address generator 103 and the read address generator 105 are equal to each other (w / r-addr);

An adder 305 which inverts the output of the light address generator 103 in the inverter N2 and generates a difference by adding it from the output of the lead address generator 105;

An absolute value converter 303 which generates MSB bits as sign bits from the output of the adder 305 and takes other data from the 2'S complementer 313 and converts other bits into absolute values according to the state of the MSB;

A comparator 301 for comparing the input a of the protection size stage GS and the magnitude b of the absolute value converter 303,

And a just-position control signal generation circuit 302 for directly or inverting a sign bit of the absolute value converter 303 and generating a pointer just-position control signal according to the output of the comparator 301.

4 is a timing diagram referred to in an embodiment of the present invention.

4a is a write timing diagram of the buffer 101,

4b is a read timing diagram of the buffer 101,

4c is a write address generation timing diagram of the write address generator 103,

4d is a timing diagram of the lead address generation of the lead address generator 105.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS.

The buffer 101 is used as an elastic buffer, and the input data of the data input terminal DAI is written in accordance with the signal of the write enable stage WE, which is generated by the write address generator 103 in the area provided (4a). The write address generator 103 is started to generate by the signal of the PI payload terminal 121 indicating the effective load portion of the input data. The read of the data in the buffer 101 is performed by a phase detector ( The read address generator 105 is initialized by the ES-OFL signal generated at 107 and the read address generator 105 is generated by the signal of the PG payload stage 122 representing the effective load portion of the output data. The data of the area designated by the address is read as shown in (4b). The write address generator 103 is a repetitive counter so that the word size of the buffer 101 is matched as shown in (4c). The read address generator 105 is also a repetitive counter so that the word size of the buffer 101 is matched as shown in (4d), which is read / readed from the phase detector 107 by the write / read address generators 103 and 105. The phase detector 107 is initialized by a signal of the write / read address data of the write / read address generators 103 and 105. Is compared with the value of the externally provided protection size (GS), and if the result is less than or equal to the value n set as the protection range, the pjc-req and njc-req signals are generated. Is used to perform pointer just function in the pointer generator located at the rear end of the elastic buffer 101. The phase detector 107 is specifically a lead / light address of the write / read address generators 103 and 105. If the data values are the same, the comparator 306 generates an ES-OFL of the elastic buffer provided to the lead address generator 105. If the data values are the same, a high is generated to initialize the lead address generator 105. And the adder 305 subtracts the value of the write address data of the write address generator 105 from the value of the read address data of the lead address generator 103 through the inverter N1 to output the output of the adder 305. It is possible to know whether the value of the MSB is "high" or "low" from which the MSB is provided to the just adjustment control signal generation circuit 302 as a sign bit (Sign). Bits other than the MSB in the value converter 303 are selected as they are or in the multiplexer MUX by the 2 'complementer 313. If the MSB is "low" according to the state of the MSB, the 2' complement is selected. A value obtained by taking the group 313 is selected, and the input is replaced with an absolute value by outputting it as "high". When the output of the absolute value converter 303 is smaller than or equal to the input of the protection size stage GS, the signal is generated to be “high” to compare the input of the end gates AN1 and AN2 of the just-position control signal generation circuit 302. ), So that the sign bit (Sign) can generate the pjc-req, njc-req signal through the inverter N1 or directly through the AND gates AN1 and AN2. Consists of.

As described above, when processing several types of TU pointers as one elastic buffer, the overall circuit size can be reduced and the minimum value can be selected and operated according to the type of TU, so the transmission delay can be set to the minimum size. There is an advantage to that.

Claims (2)

In the buffer of a synchronous transmitter, The input data terminal DAI and the write enable input terminal WE enable recording of the input data in order to implement an operation state according to a predetermined action. The input data is input by the write address W-ADDRESS. A buffer 101 which is written and read by the read address R-ADDRESS, and A write address generator 103 for generating a write address signal in response to an input of a PI payload terminal 121 representing an effective load portion of the input data; A lead address generator 105 for generating a write address signal in response to an input of the PG payload stage 122 indicating an effective load portion of the output data; A phase detector 107 for detecting the phases of the outputs of the light address generator 103 and the lead address generator 105 by adjusting the protection area according to a signal input to the protection size stage GS; And a means (110, 111) for adding each of the outputs of the light address generator 103 and the lead address generator 105 by one to provide the light address generator 103 and the lead address generator 105 again. Elastic buffer circuit in a synchronous transmission device. The phase detector 107 of claim 1, further comprising: a comparator 306 for comparing a value (w / r-addr) of each of the outputs of the write address generator 103 and the read address generator 105 with the same; An adder 305 which inverts the output of the light address generator 103 in the inverter N2 and generates a difference by adding it from the output of the lead address generator 105; An absolute value converter 303 which generates MSB bits as sign bits from the output of the adder 305 and takes other data from the 2'S complementer 313 and converts other bits into absolute values according to the state of the MSB; A comparator 301 for comparing the input a of the protection size stage GS and the magnitude b of the absolute value converter 303, And a just-position control signal generation circuit 302 for directly or inverting a sign bit of the absolute value converter 303 and generating a pointer just-position control signal according to the output of the comparator 301. An elastic buffer circuit in a synchronous transmission device.