KR980011478A - Address alignment device of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address alignment system for a semiconductor memory device, and more particularly to an address alignment device for a semiconductor memory device capable of continuously accessing memory elements having a plurality of ordered lengths. The address aligning apparatus of the present invention divides m cells having an n-bit size into at least two blocks having a size of a by b by decoding an input address, A control unit for outputting data input / output selection signals according to an input address, and a control unit for simultaneously connecting cells of the same row to cells of a block by a data input / output selection signal of the control unit And a selecting and selecting means for selecting one of the cell selecting means at all times to rearrange the data in the order of addresses by the input / output selecting signal of the controlling means portion; And a " a " input / output port connected to the input / output selection unit of the "

Description

Address alignment device of semiconductor memory device

Since this is a trivial issue, I did not include the contents of the text.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address alignment system for a semiconductor memory device, and more particularly, to an address alignment system for a semiconductor memory device, which is capable of continuously accessing memory elements, . Generally, a semiconductor memory device requires a decoder for selecting a memory word designated by an input address together with a memory element. Hereinafter, a decoder of the semiconductor memory device according to the related art will be described with reference to the accompanying drawings. 1 is a block diagram of a decoder of a semiconductor memory device according to the prior art. The internal structure of the conventional decoder is as follows. A semiconductor memory device composed of m words having a size of n bits per word is composed of m x n binary memory elements 2 and an address decoder 1 assigned to select each word. Here, the binary storage element 2 is a basic design block of the semiconductor memory device. Two address inputs are connected to the address decoder 1 and the address decoder 1 operates by a memory enable signal. That is, if the memory enable signal input to the address decoder 1 is 1, one of four words is selected according to two address input values. At this time, if the read / write signal is 1, the stored values of the binary storage element 2 of the designated word pass through the three OR gates 3 and are output to the output terminal. Other binary memory elements 2 generate a zero and therefore do not affect the output. If the read / write signal is 0, the information that is being held at the data input terminal is stored in the binary storage element 2 of the designated word. In the conventional semiconductor memory device, when an address is inputted to the address decoder 1, memory elements of several bytes of the corresponding row are simultaneously accessed.

In the conventional semiconductor memory device, when an address is input to an address decoder, only the memory elements arranged in the corresponding row can be accessed, and there is no continuity in address input. Therefore, in case of storing data having a length and an address spanning two rows, the operation speed is very slow because the operation is divided for each solution. In order to solve the problem of the conventional semiconductor memory device as described above, the present invention provides an address of a semiconductor memory device capable of continuously accessing memory elements having a plurality of byte lengths, And an object of the present invention is to provide an alignment device.

FIG. 1 is a block diagram of a decoder of a semiconductor memory device according to the prior art. FIG.

FIG. 2 is a block diagram of a configuration of an address alignment apparatus according to the present invention; FIG.

FIG. 3 is a table of truth values according to the operation of the address sorting apparatus.

DESCRIPTION OF THE REFERENCE NUMERALS

20: control circuit section 21, 22, 23, 24: 2 input demultiplexer

25, 26, 27, 28: 4 input demultiplexer 29: first address decoder

30: second address decoder 31: first memory sal block

32: second memory cell block 33, 34, 35, 36: input / output port

The address aligning apparatus of the semiconductor memory device of the present invention is capable of continuously accessing memory elements having a plurality of byte lengths arranged in order when an address is inputted. The address aligning apparatus decodes an input address to generate m cells Address decoders for dividing a plurality of blocks into at least two blocks each having a size of a × b and accessing cells corresponding to the corresponding blocks, a control unit for outputting data input / output selection signals according to an input address, A cell selecting means for selecting cells in a block by a data input / output selection signal of the control means portion at the same time in a cell of the same row; A " selection < / RTI > selection < RTI ID = 0.0 > And, it characterized in that the configuration including a single input and output ports coupled to the respective input and output selector. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an address alignment apparatus for a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram of an address alignment apparatus according to the present invention, and FIG. 3 is a truth table according to an operation of the address alignment apparatus. FIG. 3 is a truth value table according to the operation of the address sorting apparatus. FIG. In the semiconductor memory device of the present invention, the memory element for storing data is divided into two blocks, and each block has a 4-byte input / output structure. A first address decoder 929 for decoding an address input to the semiconductor memory device, a second address decoder 30, and a first memory cell block for receiving an address decoded by the first address decoder 29 31), a second memory cell block (32) receiving an address decoded by the second address decoder (30), and a data input / output selection signal S ), (S1), (S2), (S3), (S And a control circuit section 20 for outputting an input / output selection signal S Multiplexer 21 connected to the first memory cell block 31 and the second memory cell block 32 to select data input and output by the first and second memory cell blocks 31 and 32, A 2-input second D / MUX 22 connected to the first memory cell block 31 and the second memory cell block 32 by a selection signal S1 to select a data input / output, Multiplexer 23 connected to the first memory cell block 31 and the second memory cell block 32 by a data input / output selection signal S2 of the second memory cell block 31 to select data input / output, The data input / output selection signal (SU ) Inputting and outputting cell data by means of data input / output selection signals (), () by the first memory cell block 31 and the second memory cell block 32 by (SU1) Multiplexers 25, 26, 27 and 28 and the 4-input first, second, third and fourth D / MUXs 25, 26, 27 and 28, Output ports 33, 34, 35 and 36 for inputting and outputting 1, 2, 3, and 4, respectively. Since each of the 1, 2, 3, and 4 input / output ports 33, 34, 35, and 36 has a data width of 8 bits, input and output of up to 32 bits can be performed simultaneously. The operation of the address aligner of the semiconductor memory device of the present invention constructed as described above is as follows. First, when an address is input to access the memory device, the input address is decoded by the first address decoder 29 and the second address decoder 30, respectively. At this time, an address is also inputted to the control circuit unit 20 and the data input / output selection signal S ), (S1), (S2), (S3), (SU ) And (SU1). The operation of each constituent block according to each address value will be described with reference to FIG. 3 shows a case where the least significant bit of the input address A is A , And the next lower bit is assumed to be A1, A2, ..... The address entered is (S) output from the control circuit section 20 ), The data input / output selection signals of (S1), (S2), and (S3) Multiplexers 21, 22, 23 and 24 are all connected to the first memory cell block 31. The first input / And (SU ), Data input / output selection signal of (SU1) Multiplexers 25, 26, 27 and 28 are sequentially connected to the input / output ports 33, 34, 35 and 36, respectively. Therefore, the input / output of each of the input / output ports 33, 34, 35, , Byte 1, byte 2, and byte 3. If the input address is 1 (S The data input / output selection signal of Multiplexers 22, 23 and 24 are connected to the first memory cell block 31. The second input / And (SU ) And the data input / output selection signal of (SU1) Multiplexers 25, 26, 27 and 28 are connected to the first, second, third and fourth input / output ports 33, 34 and 35 36 operate as bytes 1, 2, 3, and 4, respectively. If the input address is 2 (S The data input / output selection signal of S1 is 1, so that the 2-input first and second D / MUXs 21 and 22 are connected to the second memory cell block 32 (S2) The signal And the two-input third and fourth D / MUXs 23 and 24 are connected to the first memory cell block 31. And (SU ) ≪ / RTI > (SU1) Multiplexers 25, 26, 27 and 28 are connected to the first, second, third and fourth input / output ports 33, 34 and 35 36 operate as bytes 2, 3, 4, and 5, respectively. If the input address is 4 (S The data input / output selection signals of S1, S2 and S3 are all 1, so that the 2-input first, second, third and fourth D / MUXs 21, 22, 23, 2 < / RTI > memory cell block 32 as shown in FIG. And (SU ) ≪ / RTI > (SU1) The first, second, third, and fourth input / output ports 33, 34, 35, and 36 are connected to the four input first, second, third, and fourth multiplexers 25, 26, 27, And the input and output are byte 4, byte 5, byte 6, and byte 7, respectively. If the input address is 4, 5, 6, or 7, the address of the first memory cell block 31 is set to 1 and decoded. For example, in a case where the input sampling is 6, the address of the first memory cell block 31 is byte 8 to byte 11. (S ) The data input / output selection signal of (S1) The data input / output selection signal of (S2) and (S3) becomes 1, so that the 2-input first and second input and output of the first and second multiplexers 21 and 22 are connected to the first memory cell block 31, The third and fourth demultiplexers 23 and 24 are connected to the second memory cell block 32. And (SU ) ≪ / RTI > (SU1) Multiplexers 25, 26, 27 and 28 are connected to the first, second, third and fourth input / output ports 33, 34 and 35 36 are byte 6, byte 7, byte 8, and byte 9, respectively.

As described above, the address alignment apparatus of the semiconductor memory device according to the present invention has the effect of improving the data transfer efficiency and the use efficiency of the memory device since the memory locations of consecutive bytes can be accessed regardless of any address selected . Especially. When the main memory of the CPU having various instructions having different lengths is used, the address access operation is efficiently performed, and the processing speed and reliability are improved.

Claims (6)

Address decoders that decode an input address to divide m cells having an n-bit size into at least two blocks having a size of a by b to access each cell corresponding to the block, and a data input / output A cell selecting means for selecting a cell of a block by a data input / output selection signal of the control means portion, the cell selecting means being connected to a cell of the same row of the blocks simultaneously, And a " a " input / output selectors for selecting any one of the a cell selector means for rearranging data in order of addresses by a negative input / output selection signal, and a & And the address alignment device of the semiconductor memory device. 2. The apparatus according to claim 1, wherein when the address decoder accesses the cells of the corresponding row of the last block, the other address decoder corresponding to the first block accesses the cells of the next row. A first and a second address decoder for decoding the input address and accessing the first and second demo cell blocks, respectively; When an address is inputted, a data input / output selection signal S ), (S1), (S2), (S3), (SU ) And (SU1) output from the control circuit unit, and a control circuit for outputting the respective data input / output selection signals S 1, 2, 3, 4, D / MUXs for selecting the cells of the first memory cell block or the second memory cell block by means of (S1), (S2) Output selection signal SU Multiplexer connected to any one of the 2-input first, second, third, and fourth D / MUXs by (SU1), and a 4-input first, second, And the first, second, third, and fourth input / output ports for inputting and outputting the connecting door data to and from the third and fourth di / multiplexers, respectively. The semiconductor memory device according to claim 3, characterized in that when the second address decoder accesses the cells of the corresponding row of the second memory cell block, the first address decoder accesses the cells of the next row of the first memory cell block Address alignment device. 4. The method of claim 3, wherein the 4-input first, second, third, and fourth D / MUXs multiplex the data input / output selection signals (SU ), And (SU1), respectively, to select the memory cell block. The address aligning apparatus according to claim 3, wherein each of the input / output ports has a data width of 8 bits. ※ Note: It is disclosed by the contents of the first application.