KR0140918B1 - Overhead timing detection circuit of the synchronous transport apparatus - Google Patents

Abstract

The present invention relates to an overhead timing detection circuit of a synchronous transmission device, which replaces a conventional address decoder and a plurality of payload counters with RAM to generate a counter enable signal and a data read signal during overhead timing detection. The present invention relates to an overhead timing detection circuit of a synchronous transmission device which simplifies the circuit design and is suitable for the design of digital logic.

The control generates an INC signal of each signal DS1, DSIE, DSIC, DS2, which is synchronized with a clock, and generates a data read signal and a group size address, and a group size address output from the counter. A RAM for generating a group size selection signal, a payload address generating means for receiving a respective INC signal generated from the counter and reading the INC signal according to a data read signal to generate a payload address; A payload address selection means for selecting and outputting a payload address obtained from the payload address generation means according to the group size selection signal obtained from the RAM, and a payload address and a current pointer value obtained from the payload address selection means. Pointer value ratio to compare and output the result as overhead timing detection signal. This is accomplished by having a faculty member.

Description

Overhead Timing Detection Circuit of Synchronous Transmission

1 is an overhead timing detection circuit diagram of a conventional synchronous transmission window value.

FIG. 2 is a timing diagram of input / output parts of FIG. 1.

3 is an overhead timing detection circuit diagram of the synchronous transmission device of the present invention.

4 is a timing diagram of input and output of each part of FIG.

* Explanation of symbols for the main parts of the drawings

100: counter 200: ram

300: payload address generator 400: payload address selector

500: pointer value comparison unit

The present invention relates to an overhead timing detection circuit of a synchronous transmission apparatus, and in particular, replaces an address decoder and a plurality of payload counters, which were previously used to generate a counter enable signal and a data read signal, when detecting an overhead timing. The present invention relates to an overhead timing detection circuit of a synchronous transmission device which simplifies the circuit design and is suitable for the design of digital logic.

In general, up to seven VT groups can be mapped to STS-1 (Synchronous Transport Signel Level-1) SPE (Synchronous Payload Envelop). In one VT group, DS1 can be mapped according to the type of VT. Is 4 channels, 3 channels for DSIE, 2 channels for DSIC, and 1 channel for DS2.

In this case, up to 28 VTs exist in the input STS-1 SPE, and counters that operate separately according to the configuration of each VT, that is, DS1, DSIE, DSIC, and DS2 exist.

However, only one signal of DS1, DSIE, DSIC, and DS2 can be mapped to one VT group, so the remaining three payload counters do not operate.

In the synchronous transmission device, the conventional overhead timing detection circuit generates an INC signal of each signal DS1, DSIE, DSIC, and DS2 mapped as shown in FIG. The counter 10 and the address and control clock CK corresponding to the channel and the VT group obtained from the counter 10 are inputted to output the counter enable signal EN and the data read signal LD. The address decoder 20, the counter enable signal EN and the data read signal LD obtained from the address decoder 20 are input, and the INC signal of each signal obtained from the counter 10 is counted. The payload counter 30 includes a plurality of payload counters 30a to 30g for generating a payload address, and the payload counter 30 includes a payload counter 30 and a payload counter 30a. by teeth An address selector 40 which selects and outputs a payload address obtained from the first to seventh payload counters 30a to 30g in the counter 30, and a payout obtained from the address selector 40; The pointer value comparison unit 50 compares the load address with the current pointer value to detect the overhead timing.

The operation of the overhead timing detecting circuit of the conventional synchronous transmission device configured as described above will be described in detail with reference to FIG. 2. First, the counter 10 is input to the control clock CK as shown in FIG. The count signal is input to the payload counter unit 30 which generates the INC signal of each signal DS1, DSIE, DSIC, and DS2 that are mapped, and adds a channel address and a group address to correspond to a channel and a group. Generate an address.

The address generated from the counter 10 is inputted to the address decoder 20. Accordingly, the address decoder 20 is synchronized with the control clock CK as shown in FIG. Is generated and input into the payload counter unit 30 described above.

In addition, the data read signal LD is outputted and input to the payload counter unit 30, where the data read signal LD has an address obtained from the counter 10 as shown in FIG. As shown in (d) in the case of VTGR1, (e) in the case of VTGR2, and (f) in the case of VTGR7, the read signals delayed by one cycle are sequentially output based on VTGR1.

Accordingly, the payload counter unit 30 enables the first to seventh payload counters 30a to 30g therein according to the counter enable signal EN output from the address decoder 20. In addition, each INC (DS1 DINC, DSIE INC, DSIC INC, DS2 INC) obtained from the counter 10 in accordance with the data read signal LD as shown in (d) to (e) shown in FIG. Processing to generate a Payload Address.

In more detail, since the payload counter unit 30 does not know which of the input VT group signals is mapped to DS1, DSIE, DSIC, or DS2, four counters are configured for each VT group (VTGR1 to VTGR7). All the payload counters 30a to 30g are operated.

That is, one VT group has a payload counter for DS1, a payload counter for DSIE, a payload counter for DSIC, and a payload counter for DS2, and there are seven VT groups from VTGR1 to VTGR7. That's a total of 28 payload counters.

Meanwhile, as described above, the payload addresses generated by operating the 28 payload counters to read the corresponding data are the payload addresses corresponding to the channel 1 (CH1) of the VTGR1, as shown in FIG. 2 (g), and the VTGR2, The payload address corresponding to channel 1 (CH1) is shown in (h) of FIG. 2, and VTGR7, CH1 is (i), and VTGR1, CH2 are (j).

However, since only one signal of DS1, DSIE, DSIC, and DSW can be mapped to one VT group, 28 payload counters operate, but the payload address generated according to the input signal is one VT group. The payload address is only generated from the payload counter for each VT group.

As a result, only one payload counter is operated per VT group. Therefore, three payload counters per VT group operate but do not operate because there is no output.

Meanwhile, the payload addresses generated by the operation of the payload counter unit 30 are input to the address selector 40, and accordingly, the address selector 40 is a VTGR which is a selection signal input from the outside. According to the signal VTGR and the VT size signal VTSIZE, a corresponding payload address is selected from the input payload addresses and input to the pointer value comparison unit 50.

The pointer value comparison unit 50 compares the input payload address with the current pointer value Pointer, and outputs the result value as the overhead timing detection signal V5T as shown in FIG. .

However, the overhead timing detection circuit of such a conventional synchronous transmission apparatus uses an address decoder to generate a counter enable signal and a data read signal, and thus, there is a disadvantage in that information about the VT size cannot be provided. In order to generate the payload address by operating 28 payload counters having the same function to generate the address, the circuit configuration is complicated and the reliability of the device is deteriorated.

Accordingly, an object of the present invention is to replace the conventional address decoder used to generate a counter enable signal and a data read signal with RAM in order to provide VT size information and digital logic design. By reducing the payload counter to a counter for one VT group, an overhead timing detection circuit of a synchronous transmission device is provided to facilitate circuit design.

Means for achieving the object of the present invention comprises a counter for generating the INC signal of each signal (DS1, DSIE, DSIC, DS2) mapped in synchronization with the control clock, and generating a data read signal and a group size address; RAM generating a group size selection signal according to the group size address outputted from the counter, each INC signal generated from the counter is input, and the payload address is read by reading the INC signal according to a data readout signal. A payload address selecting means for selecting and outputting a payload address generating means generated, a payload address obtained from the payload address generating means according to the group size selection signal obtained from the RAM, and the payload address selecting means; Compares the current payload value with the payload address obtained from To be achieved by constituted by any pointer value comparison means for outputting as a detecting head timing signal, hereinafter will be described in detail based on the accompanying drawings, the present invention.

3 is an overhead timing detection circuit diagram of the synchronous transmission device of the present invention, which generates an INC signal of each of the signals DS1, DSIE, DSIC, and DS2 mapped in synchronization with the control clock CK, as shown in FIG. A counter 100 for generating a data read signal LD and a group size address GR, and a RAM for generating a group size selection signal SEL according to the group size address GR output from the counter 100. 200 and a payload address generator 300 for receiving a respective INC signal generated from the counter 100 and reading the INC signal according to the data read signal LD to generate a payload address. And a payload address selector 400 for selectively outputting the payload address obtained from the payload address generator 300 according to the group size selection signal SEL obtained from the RAM 200, and the payload. Address Payload address obtained from the taekbu 400 and compares the current value pointer (Pointer), which are configured the result as the pointer value comparison unit 500 for outputting the detection signal as a timing overhead (V5T).

The operation and effects of the overhead timing detection circuit of the synchronous transmission device of the present invention configured as described above will be described in detail with reference to FIG. 4.

First, the counter 100 is an INC signal DS1 INC, DSIE INC, DSIC INC, DS2 INC of each of the signals DS1, DSIE, DSIC, DS2 mapped in synchronization with the control clock CK (a) of FIG. Is generated and input to the payload address generator 300, and the data read signal is output from the last bit of the previous frame as shown in FIG. 4A to the payload address generator 300. Will be entered.

In addition, a VT size address corresponding to (VTGR) is generated to the corresponding VT group in units of 3 bits, and the VT size address GR is input at V1 time, and accordingly, the size of the VT group is input. The address GR is generated.

Accordingly, the RAM 200 according to the size address GR of the input VT group, size information of the VT size according to the type (DS1, DSIE, DSIC, DS2) stored therein, that is, the payload address selection signal ( SEL) is output in units of 2 bits and input to the payload address selector 400.

In addition, the payload address generation unit 300 may convert each of the INC signals DS1 INC, DSIE INC, DSIC INC, and DS2 INC obtained from the counter 100 into a data read signal obtained from the counter 100. It reads according to LD) to generate a payload address.

Here, the payload address generator 300 has only four payload counters unlike the prior art, and (b) of FIG. 4 is timing of the DS1 INC obtained from the counter 100, and (c) is accordingly. The payload address generated from the payload counter for DS1 in the payload address generator 300.

Meanwhile, the payload addresses generated from the four payload counters in the payload address generator 300 are input to the payload address selector 400, respectively. The payload address is selectively outputted according to the VT size information generated from the RAM 200, that is, the payload address selection signal.

The payload address selected and output from the payload address selector 400 is input to the pointer value comparator 500. Accordingly, the pointer value comparator 500 inputs the input payload address and the current pointer. The values will be compared.

As a result of this comparison, if the input payload address and the current pointer value are the same, V5Time is set.

As described in detail above, the present invention can simplify the selection signal by using a RAM instead of the conventional address decoder, thereby simplifying the configuration of the payload address selection unit, and by generating a read signal through the counter, the payload address generation unit The internal payload counter can be reduced, simplifying the overall circuit configuration and improving the economics and reliability of the product. Also, the use of RAM has a valid and effective effect in digital logic design.

Claims (4)

According to the counter which generates the INC signal of each signal DS1, DSIE, DSIC, DS2 mapped in synchronization with the control clock, and generates a data read signal and a group size address, and according to the group size address outputted from the counter. RAM for generating a group size selection signal, payload address generating means for receiving each INC signal generated from the counter and reading the INC signal according to a data read signal to generate a payload address; Comparing the payload address selection means for selecting and outputting the payload address obtained from the payload address generating means according to the group size selection signal obtained from < RTI ID = 0.0 > Pointer value ratio that outputs the result as an over timing detection signal. The overhead of a synchronous transmission apparatus characterized by means consists of a timing detecting circuit. 2. The overhead timing detection circuit of claim 1, wherein the counter outputs a data read signal at the last bit of the previous frame. The overhead timing detection circuit according to claim 1, wherein the counter generates a group size address in units of 3 bits according to the input of the V1 time. The overhead timing detection circuit of a synchronous transmission device according to claim 1, wherein the RAM stores VT size information according to the type of the VT group (DS1, DSIE, DSIC, DS2).