KR100273246B1 - Apparatus for correcting error of state machine - Google Patents

Abstract

PURPOSE: A state machine error correcting device is provided to be capable of correcting an algorithm error of a state machine using a comparison and correction logic circuit, after a chip is made. CONSTITUTION: A state logic part(10) receives a current state value of a state machine and an input to the state machine to determine a next state value. A state vector flip-flop(11) stores and outputs the next state value from the state logic part(10) in synchronization with a clock signal. A comparison and correction logic part(20) compares a current state value from the state vector flip-flop(11) with a state value to be detected. The comparison and correction logic part(20) selects one of the current state value from the state vector flip-flop(11) and an externally applied correction state value in response to a comparison result, and outputs the selected state value to the state logic part(10) as a current state value. An output logic part(12) determines a state value, which the state machine outputs, from the current state value from the comparison and correction logic part(20).

Description

State machine error correction device {APPARATUS FOR CORRECTING ERROR OF STATE MACHINE}

The present invention relates to a state machine error correcting apparatus, and more particularly, to a state machine error correcting apparatus that allows to correct the error in the algorithm of the state machine used in the integrated circuit design after the chip is made.

FIG. 1 is a block diagram showing a configuration of a conventional state machine, and as shown therein, a state logic unit 10 for combining a current state value of a state machine with an input applied to the state machine to determine a next state; A state vector flip-flop (11) for storing and outputting the next state value generated by the state logic unit (10) in synchronization with a clock; It consists of an output logic section 12 that determines the output value that the state machine should output from the current state value.

In FIG. 1, the state logic unit 10 combines the current state value with an input condition applied to the state machine to determine the next state value of the state machine, and the next state value determined here is transferred to the state vector flip-flop 11. It is stored and applied to the state logic section 10 and the output logic section 12 as a current state value for the next clock period.

In addition, the output logic unit 12 determines and outputs the state value to be output from the current state value (in the case of the mealy state machine, the current input affects the current output and thus includes the input). .

As described above, in the conventional technology, the state machine is composed only of hardware, and when an error occurs in an algorithm, there is a problem in that a chip must be newly made by designing an integrated circuit from the beginning.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a state machine error correction device that can correct errors in the state machine's algorithm after the chip is made using logic for comparison and correction. Has its purpose.

1 is a block diagram showing the configuration of a conventional state machine.

Figure 2 is a block diagram showing the configuration of the state machine error correcting apparatus of the present invention.

Figure 3 is a block diagram showing another embodiment of the present invention.

Figure 4 is a block diagram showing the configuration of the comparison and correction logic in Figure 2;

*** Description of the symbols for the main parts of the drawings ***

10: state logic portion 11: state vector flip-flop

12: output logic part 20: comparison and correction logic part

21: comparison unit 22: multiplexer (MUX)

In the state machine error correcting apparatus of the present invention for achieving the above object, in the state machine used in the design of the integrated circuit, the state value determined by the state vector flip-flop of the state machine is compared with the state value to be detected. And a comparison and correction logic unit for selecting one of a state value generated in the state vector flip-flop of the state machine or a state value applied from the outside and outputting the current state value according to the comparison result.

The comparison and correction logic unit includes: a plurality of comparison units for comparing a state value to be detected with a current state value determined by a state vector flip-flop of a state machine; And a multiplexer which selects one of a state value generated in the state logic unit of the state machine or a modified state value applied externally by the comparison signal output from the comparison unit and outputs the state signal to the state vector output unit.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing the configuration of a state machine error correcting apparatus of the present invention. As shown in FIG. )Wow; A state vector flip-flop (11) for storing and outputting the next state value generated by the state logic unit (10) in synchronization with a clock; The current state value output from the state vector flip-flop 11 is compared with a state value to be detected, and according to the comparison result, the current state value output from the state vector flip-flop 11 or a state value applied from the outside. A comparison and correction logic unit 20 for selecting one of (modified state values) and outputting the current state value to the state logic unit 10; The output logic unit 12 determines a state value to be output by the state machine from the current state value output from the comparison and correction logic unit 20.

FIG. 3 is a block diagram showing another embodiment of the present invention. As shown in FIG. 2, the configuration of FIG. 2 is the same, except that the position of the comparison and correction logic unit 20 is a state vector flip-flop 11. The difference is that it is located at the front of.

Referring to Figures 2 and 3 attached to the operation of the embodiment according to the present invention configured as described above are as follows.

First, as shown in FIG. 2, the current state value output after one clock from the state vector flip-flop 11 is input and detected by the comparator 21 of the comparison and correction logic unit 20 as shown in FIG. 4. When the comparison value is the same or different, a comparison signal is generated. The comparison signal is received by the multiplexer 22. If the comparison value is the same, the modified state value is obtained. The value is output after one clock.

On the other hand, when the comparison and correction logic portion 20 is located in front of the state vector flip-flop 11, as shown in Figure 3 receives the current state value from the state logic portion 10 and performs the same operation as described above, but only when input and output The only difference is that there is no delay.

As described above, the state machine error correcting apparatus of the present invention is easy to predict the result after chip modification by simply correcting an error occurring in the state machine of the finished chip without redesigning the chip. It is effective to speed up the time of entry.

Claims (2)

A state logic unit for combining a current state value and an input of a state machine to determine a next state value, a state vector flip-flop for storing and outputting the next state value generated in the state logic unit in synchronization with a clock, and the state vector Compares the current state value output from the flip-flop with the state value to be detected, and selects either the current state value output from the state vector flip-flop or a modified state value applied from the outside according to the comparison result, and the state logic is selected. And a output logic section for determining a state value to be output by the state machine from the current state value output from the comparison and correction logic section. Machine Error Correction Sheet . 2. The apparatus of claim 1, wherein the comparison and correction logic unit comprises: a plurality of comparison units for comparing a state value to be detected with a current state value output from a state vector flip-flop; And a multiplexer configured to select and output one of a current state output from the state vector flip-flop or a modified state value externally applied by the comparison signal output from the comparison unit.

Images