KR100259139B1 - Input buffer controlling apparatus for audio decorder - Google Patents

Abstract

PURPOSE: An apparatus for controlling an input buffer for an audio decoder is provided to reduce a time for decoding by using an input buffer for storing an audio bit stream in a memory and constructing a device writing in a memory in short time and accessing to a memory directly and performing a time sharing control. CONSTITUTION: A signal detecting unit(10) generates a frame pulse by analyzing an inputted and encoded audio bit stream and detecting a synchronizing signal included in the bit stream. A buffer control unit(20) supplies 24-bit data in an input buffer(30) and generates an input buffer writing clock. The input buffer(30) consists of 128*24-bit FIFO memory. A buffer control unit 2(40) reads data from the input buffer(30) and controls a writing operation in a RAM(50). The RAM(50) stores data generated from an audio 2 frame and an audio decoder. A memory reading/writing control unit(60) controls a RAM writing/reading operation. A decoding unit(70) inputs and decodes audio 1 frame data being stored in the RAM(50) by an audio data algorithm. A 33MHz oscillator(80) offers a decoder and a RAM reading/writing clock. A 10-frequency divider(90) adjusts a data processing time of the input buffer(30) and the RAM(50).

Description

Input Buffer Control for Audio Decoder

1 is an overall configuration diagram of an audio decoder input buffer control device,

2 is a block diagram of a synchronization signal detector of FIG.

3 is a configuration diagram of the buffer control unit 1 of FIG.

4 is a configuration diagram of the buffer control unit 2 of FIG.

5 is a configuration diagram of the memory read / write control unit of FIG.

6 is an operating waveform diagram of FIG.

(a) is an operation waveform diagram of a synchronization signal detector;

(b) is a waveform diagram of a RAM operation and a decoder operation.

* Explanation of symbols for main parts of the drawings

10: synchronization signal detection unit 11: comparator

12: reference data 13: frame counter

14: asynchronous control unit 15: frame counter control unit

16: frame pulse counter 17: bit delay unit

20: buffer controller 1 21: serial / parallel converter

22, 62: flip-flop 23: 24 divider

24: 16 divider 25: Write completion signal generator

30: input buffer 40: buffer control unit 2

41: logic end 42: reset signal generator

50: RAM 60: Memory Write / Read Control

61: 10-bit counter 63: address decoder

64: selector 65: ram chip select signal generator

66: write / read control 70: decoder

80: 33 MHz oscillator 90: 10 minute period

In the field of audio of high-definition television, the next-generation television of the present invention, the audio decoder is applicable to direct hardware production and application specific integrated circuits (ASIC) design of the audio decoder, and also applicable to other digital audio data compression extension devices. It relates to an input buffer control device.

Generally, a decoder is a device used to receive a specific code and signal, and to find an original information signal. The present invention uses an input buffer to store an audio bit stream in a memory when designing and manufacturing an audio decoder. In addition, a device for writing to a memory in a short time is configured, and the decoding time is reduced by direct memory access and time division control.

That is, the input buffer control apparatus for an audio decoder according to the present invention comprises: a sync signal detector for analyzing the input encoded audio bit stream and detecting a sync signal included in the bit stream to generate a frame pulse; A buffer controller 1 for supplying 24-bit data to the input buffer and generating an input buffer write clock; An input buffer consisting of a 128 * 24 bit first-in first-out memory; A buffer controller 2 which reads data from an input buffer and controls a write operation to RAM; A RAM for storing data generated from an audio 2 frame and an audio decoder; A memory read / write controller configured to control a RAM write / read operation; A decoder which input-decodes the audio 1 frame data stored in the RAM by an audio data extension algorithm; 33MHZ oscillator, which provides a decoder and RAM read / write clock, and a 10M frequency divider that adjusts the input buffer and RAM data processing time by dividing the 33MHZ oscillator.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

1 is an overall configuration diagram of an input buffer control autonomy for an audio decoder. A sync signal for generating a frame pulse by analyzing an input encoded audio bit stream, analyzing a bit stream, and detecting a sync signal included in the bit stream. A detection unit 10; A buffer controller 20 for supplying 24-bit data to the input buffer 30 and generating an input buffer write clock; An input buffer 30 composed of a 128 * 24 bit first-in first-out memory; A buffer control unit 2 (40) which reads data from the input buffer 30 and controls a write operation to the RAM 50; A RAM 50 for storing the audio 2 frames and the data generated in the audio decoder; A memory read / write control unit 60 for controlling a RAM write / read operation; A decoder 70 for input decoding audio 1 frame data stored in the RAM 50 by an audio data extension algorithm; A 33 MHz oscillator providing a decoder and a RAM read / write clock; A 33 MHz oscillator 80 is divided into 10 dividers 90 which adjust the data processing time of the input buffer 30 and the RAM 50.

FIG. 2 is a block diagram of the synchronization signal detecting unit 10 of FIG. 1, and compares the input encoded audio bit stream signal S1 with the reference data 12 having the FFFH value, if the synchronization is equal. A comparator 11 for outputting a signal S3; A frame counter 13 which starts counting 6144 and outputs a count completion signal S4 when the count is completed; An asynchronous controller 14 for inputting the synchronization match signal S3 and the count completion signal S4 and outputting an IFP signal S5 when both signals are '0'; A frame counter controller 15 for inputting the IFP signal S5 to reactivate the frame counter 13 with a reset signal S6; An FFP counter 16 which inputs an output signal EFP signal S7 of the frame counter control unit 15 and outputs it as an FFP signal S8; And a 12-bit delay section 17 for outputting the input audio bit stream signal S1 as data 1 S9.

3 is a configuration diagram of the buffer control unit 1 (20) of FIG. 1, and a serial / parallel conversion unit 21 for converting 1-bit serial data S9 output from the synchronization signal detection unit 10 into 24-bit parallel data. Wow; A flip-flop (12) for latching the output 24-bit parallel data with a clock signal (S1) of a 24 divider (23); A 24 divider 23 synchronized with the output signal FFP signal S8 of the FFP counter 16; A 16 divider 24 which divides the 24 divided clock signals S1 into 16 and inputs them to the write completion signal generator 25; Write completion signal outputting a write completion signal S13 indicating that a write operation is completed when the full flag FF signal S14, which is an output signal of the input buffer 30, is generated as the clock signal S2 / 16-hour unit. It is comprised by the generation part 25.

4 is a block diagram of the buffer control unit 2 40 of FIG. 1. When the write completion signal S13 is logic '1', the clock of the 3318 MHZ of the clock sheath CK SYS S16 is inputted. A logic end 41 for outputting a write completion signal S13 as a read signal 1 S17; Reset to output the reset signal S18 to the input buffer 30 by the empty flag EF signal S15 and the clock signal S2 of the input buffer 30 to prevent a malfunction of the input buffer 30. It consists of a signal generator 42.

FIG. 5 is a block diagram of the memory read / write control unit 60 of FIG. 1, which is synchronized with the FFP signal S20 to count the serial input clock read signal 1 S17 to parallel 10 bits. A 10-bit counter 61 for generating an address S21; A flip-flop 62 for inputting the write completion signal S19 and the read signal 1 S17 to output the RAM chip select signal 1 S22 to the RAM chip select signal generator 61; Analyzing the address data (S23) output from the decoder 70 to make a RAM access address (S24) to output to the selector 64, the address decoder for creating a RAM chip select signal 2 (S25) and read signal 2 (S26) 63; A selector 64 which selects the input 10-bit parallel address S21 and the RAM access address S24 as the control signal and outputs them to the address S30; RAM chip select signal generator 65 for selecting the output signal RAM chip select signal 1 (S22) of flip-flop 62 and the output signal RAM chip select signal 2 (S25) of address decoder 63 by the control signal of selector 64. ); A write / read control unit which receives the read signal 1 (S17) and the read signal 2 (S26) and selects and outputs the write signal line S28 and the read signal line S29 of the RAM 50 according to the control signal of the selector 64. It consists of (66).

According to the present invention configured as described above, if the encoded audio bit strip S1 input from the synchronization signal detection unit 10 is equal to the reference data 12 having the FFFH value in the comparator 11, The synchronization coincidence signal S3 is output. This signal is then logic '0'. On the other hand, the frame counter 13 starts counting 6144 and outputs a count completion signal S4 when the count is completed. When the synchronization match signal S3 and the count completion signal S4 output as described above are input to the asynchronous control unit 14 and both signals are '0', the IFP signal S5 is output and this is a logic. Is '0'. This signal S5 is input to the frame counter control unit 15 and has a function of reactivating the frame counter 13 through an output terminal. In the frame counter control unit 15, if the IFP signal S5 is input three or more times in a row, the EFP signal S7 is output and the FFP counter 16 is connected to the FFP. Outputs the (FP) signal S8. On the other hand, the input audio signal S1 is output as the data 1 S9 by the 12-bit delay unit 17. The buffer control unit 1 (20) is the data buffer (S9) and FFP (S8) and the clock signal (S2) output from the synchronization signal detection unit 10 and the input buffer full flag output from the input buffer (30) The (FF) signal S14 is input. The serial / parallel converter 21 converts 1-bit serial data S9 into 24-bit parallel data, which is a 24-bit signal inputted from the flip-flop 22 using a clock output from the 24 divider 23. Latch. This output is represented by data 2 (S10). At this time, the 24 divider 23 is synchronized by the FFP signal S8. The 24 divided clock S11 becomes a write signal and is commonly used as the write clock S12 of the input buffer 30. The signal S11 is further divided into 16 by the 16 divider 24 and input to the write completion signal generator 25. The write completion signal generator 25 outputs a write completion signal S13 indicating that a write operation is completed when the input buffer output signal flag FF is generated in units of clocks and in units of 16 hours.

When the input write completion signal S13 is logic '1', that is, when the operation is completed in the input buffer 30, the buffer control unit 2 40 inputs a clock of 33 / 8MHZ of the clock system S16, The write completion signal S13 outputs the read signal 1 S17, which is the input buffer 30 read clock, by the logic end 41. In order to prevent a malfunction of the input buffer 30, the reset signal generator 42 outputs a signal reset S18 to reset the first-in, first-out memory that is the input buffer 30 when the sequential write and read operations are completed. The signal S18 receives the empty flag EP signal S15 of the input buffer 30 and controls to output a reset signal, that is, a logic '0', during the clock signal S2 period.

In the memory read / write control unit 60, the 10-bit counter 61 is synchronized with the FFP signal S20 to count the serial input clock read signal 1 S17 so that the 10-bit parallel address S21 is used. Make The 10-bit output data S21 output from this device 61 is input to the selector 64. In addition, the address data S23 output from the decoder 70 is analyzed to generate a RAM access address S4 and output to the selector 64. In addition, the address decoder 63 generates a RAM chip select signal 2 (S25) and a read signal 2 (S26). The RAM chip select signal generator 65 receives the RAM chip select signal 1 (S22) output from the flip-flop 62 and the RAM chip select signal 2 (S25) output from the address decoder 63, and then the ram chip select signal 1 (S22). When this logic is '0', the RAM chip select signal 1 (S22) is output as the RAM chip select signal S27, the RAM chip select signal 1 (S22) is logic '1', and the RAM chip select signal 2 (S25) is logic '0'. When the RAM chip select signal S27 outputs a logic '0', the select signal of the selector 64 selects a logic '0' when the RAM chip select signal 1 (S22) is a logic '0' and a RAM chip select signal 1 ( If S22) is a logic '1', the controller 22 outputs a logic '1'. The selector 64 selects the 10-bit parallel address S21 and the RAM access address S4 signal input as the control signal, and outputs them to the address S30. That is, when the select signal is logic '0', the 10-bit parallel address S21 is selected. When the signal is logic '1', the RAM access address S24 is selected and output to the address S30. The write / read control unit 66 outputs the input read signal 1 (S17) and read signal 2 (S26) to the write signal line S28 and the read signal line S29 according to the logic state of the select signal. . If the select signal is logic '0', the input read signal 1 (S17) is directly output to the write signal line S28, and the logic '1' is output to the read signal line S29, and if the select signal is logic '1', The logic '1' is output to the write signal line S28, and the input read signal 2 (S26) is output to the read signal line S29 as it is.

The input buffer control device of the present invention operating as described above operates while making an operating waveform diagram as shown in FIG.

(a) is an operation waveform diagram of the synchronization signal detection unit 10. The input data S1 is a bit stream encoded by a computer simulation test by an audio compression decompression algorithm, and includes 32-bit header data including a synchronization signal. And one frame of CRC-16 error check data, scale factor information, scale factor, bit allocation information, audio data, and additional data, which has a size of 6144 bits. The clock signal S2 is a transmission clock of the input audio bitstream S1 and is a clock having a 256KHZ frequency. The frame pulse (EP) S8 contains a synchronization signal in the first 12 bits of one audio frame, and this output signal S8 represents a frame pulse FP (S8) indicating the beginning of the audio frame.

(b) shows a RAM write operation, a RAM read operation, and a decoding operation waveform based on the frame pulse. The RAM write operation is performed at regular intervals per frame of audio (1/16). 2 msec) 16 times. One write operation is (10 / (33 * 10 ⁶ ) * 16 3.9usec). For decoding at the decoder 70, the time for reading the data of the RAM 50 can be any time other than the RAM write operation in one frame. You can decode at a time other than the RAM read / write operation that stores the audio data.

As described above, according to the present invention, by reducing the size of the first-in, first-out memory for the input buffer as much as possible, the time / partition memory access and decoding operation, and shorten the operation time of the decoder using a direct memory approach, By reducing a large amount of hardware and shortening in real time, a large amount of hardware can be reduced in hardware and real-time decoding processing can be performed, thereby reducing the number of gates and simplifying chip design in ASIC hardware design. It can be used for digital satellite broadcasting and data transmission devices that use audio data compression / extension algorithms.

Claims (5)

A synchronization signal detection device 10 for detecting a synchronization signal S1 of an input encoded audio bitstream; A buffer controller 1 (20) for controlling a write operation of the input buffer 30; An input buffer 30 having the input data in parallel 24-bit 16 words; A buffer control unit 2 (40) for reading data stored in the input buffer (30); RAM 50 for storing two frames of audio data for decoding and the extra data generated when diding; A memory write / read control unit 60 for controlling read / write operations of the RAM 50 memory; A decoder unit 70 for decoding the encoded audio data; A 33MHZ oscillator section 80 for generating a 33MHZ system clock; An audio decoder input buffer control device comprising: a 10-dividing unit (90) for dividing a 33 MHZ clock in order to provide an input buffer (30) and a RAM (50) operation clock. The method of claim 1, The synchronization signal detecting apparatus 10 compares the input encoded audio bit stream signal S1 with the reference data 12 having the FFFh value and outputs a synchronization match signal S3 if it is equal. )Wow; A frame counter 13 which starts counting 6144 and outputs a count completion signal S4 when the count is completed; An asynchronous control unit 14 for inputting the synchronization matching signal S3 and the count completion signal S4 and outputting an IFP signal S5 when both signals are '0'; A frame counter controller 15 for inputting the IEP signal S5 to reactivate the frame counter 13 with the reset signal S6; An FFP counter 16 which inputs an output signal EFP signal S7 of the frame counter control unit 15 and outputs the signal as an FFP signal S8; And a 12-bit delay unit (17) for outputting the input audio bit stream signal (S1) as data 1 (S9). The method of claim 1, A buffer controller 1 (20) includes a serial / parallel converter 21 for converting 1 (S9), which is 1-bit serial data output from the synchronization signal detector 10, into 24-bit parallel data; A flip-flop 12 for latching the output 24-bit parallel data into the clock signal S11 of the 24 divider 23; and an output signal FP signal S8 of the FFP counter 16; A 24 divider 23 synchronized by); A 16 divider 24 which divides the 24 divided clock signal S11 into 16 and inputs them to the write completion signal generator 25; Write completion signal outputting a write completion signal S13 indicating that a write operation is completed when the full signal FF, S14, which is an output signal of the input buffer 30, is written as the clock signal S2 / 16-hour unit. Input buffer control device for an audio decoder, characterized in that consisting of a generator (25). The method of claim 1, When the input write completion signal S13 is logic '1', the buffer control unit 2 40 inputs a clock of 33 / 8MHZ of the clock system CKSYS S16 to read the write completion signal S13 into a read signal 1 ( A logic end 41 outputted to S17); Reset to output the reset signal S18 to the input buffer 30 by the empty flag EF signal S15 and the clock signal S2 of the input buffer 30 in order to prevent malfunction of the input buffer 30. Input buffer control device for an audio decoder, characterized in that consisting of a signal generator (42). The method of claim 1, The memory read / write control unit 60 is synchronized with the FFP signal S20 to count the serial input clock read signal 1 S17 to form a 10-bit parallel address S21, which is a 10-bit counter 61. )Wow; A flip-flop 62 for inputting a write completion signal S19 and a read signal 1 S17 to output the RAM chip select signal 1 S22 to the RAM chip select signal generator 65; Analyzing the address data (S23) output from the decoder 70 to create a RAM access address (S24) to output to the selector 64, the address decoder (2) to create a RAM chip select signal 2 (S25) and read signal 2 (S26) ( 63); A selector 64 that selects the input 10-bit parallel address S21 and the RAM access address S24 as the control signal and outputs the address to the address S30; Ram chip select signal generator 65 for selecting the output signal of the flip-flop 62, the ram chip select signal 1 (S22) and the address decoder 63, the ram chip select signal 2 (S25), by the control signal of the selector 64. )Wow; A write / read control unit which receives the read signal 1 (S17) and the read signal 2 (S26) and selects and outputs the write signal line S28 and the read signal line S29 of the RAM 50 according to the control signal of the selector 64. Input buffer control device for an audio decoder, characterized in that consisting of (66).