JP2612004B2 - Teletext data reception circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a circuit for extracting teletext data from a television signal subjected to video detection and temporarily storing the received teletext data.

(Prior art) Teletext data superimposed on a television broadcast signal is obtained by extracting character data from a video signal detected by video detection, and the extracted character data is searched for a program by a microprocessor (hereinafter referred to as a CPU). To do
All transmitted data is temporarily stored in the reception data buffer. Since the CPU must selectively perform the search of the reception data buffer and the presentation processing of the display memory, the address and data bus lines of the reception data buffer are separated from the bus lines controlled by the CPU to improve the presentation processing efficiency. I have. In such a case, a dedicated RAM is often used as the reception data buffer. As a result, the character data retrieval process and the presentation process are performed in parallel, and the waiting time can be reduced.

By the way, if the dedicated reception data buffer is used as described above, the address specification for the search is not performed by the CPU, so that the address is specified by the order counter.

FIG. 5 shows an example of a conventional counter means for controlling the writing of the received data buffer RAM.

In FIG. 5, a horizontal synchronization signal HD is led to a terminal P11, and a vertical synchronization signal VD is led to a terminal P12. The horizontal synchronizing signal HD is counted by the line address counter 11 as a horizontal synchronizing pulse, and the count output is output as 9-bit address data corresponding to one frame. Further, the horizontal synchronization signal HD and the vertical synchronization signal VD are supplied to the timing signal generation circuit 12. As a result, the timing signal generation circuit 12 generates a gate pulse DG (hereinafter referred to as a character data extraction pulse) corresponding to the period in which the character data is superimposed. The output of the line address counter 11 is such that the lower three bits are used as a line address AH during the vertical blanking period as a receive data buffer R (not shown).
Supplied to AM. Further, the timing signal generation circuit 12
When the line address counter 11 outputs a line count for one frame, a reset pulse RV is supplied to the line address counter 11 to reset the count output to an initial value.

According to such a configuration, the 14H, 15H of the first field in the vertical blanking period in which the character data is superimposed.
H, 16H, and 21H, 227H, 228H, and 229th of the second field
Each of the periods H and 284H is distinguished by the lower three bits of the address from the line address counter 11, and the line address of the reception data buffer is designated correspondingly.

However, in the case of the conventional circuit, the line address counter
11 simply uses the output obtained by counting the horizontal synchronizing signal HD as address data. Therefore, in order to store character data for four data lines in one field period, the storage area as the reception data buffer is equivalent to eight data lines. Required. If the storage capacity of the reception data buffer is determined as described above, data is continuously stored from the area corresponding to the 14H to the area corresponding to the 16H as shown in FIG. 6A. Since there is no character data from the 17th to the 20th, it is an unused area. Therefore, according to the conventional line counter method, when one data line stores 34 bytes (272 bits) of character data, an area of 272 bytes is required to store data of one field. Generally, the reception data buffer is used in an appropriate area so as to hold a plurality of programs in the order of transmission of the character data. However, when an area for 4 data lines per field is unused, a huge amount of area is required. The character data is stored without using.

In addition, the teletext data is standardized so that it can be superimposed on the 10th to 13th periods in the first field, for example, in addition to the above period. In this case, the section from the first data to the last data in one vertical blanking period extends for 12 horizontal scanning periods. Therefore, according to the character data holding circuit using the line address counter 11, since the lower 4 bits are used as a line address, a RAM capable of storing character data for 16 data lines in one field is required.

Therefore, it is conceivable to use a special counter that returns to the initial value when counting from 10H to 21H.
As shown in FIG. 6B, the area corresponding to four lines remains unused.

(Problems to be Solved by the Invention) Since the reception data buffer in the conventional teletext receiver specifies the address by the output of the line address counter 11 counting the horizontal synchronization signal HD,
The address area corresponding to the period in which the character data is not superimposed remains unused, and there is a disadvantage that the use efficiency of the storage area is extremely low.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit for receiving teletext data which eliminates the above-mentioned problems and improves the area use efficiency of the reception data buffer.

[Structure of the Invention] (Means for Solving the Problems) In the circuit for receiving teletext data of the present invention, character data is superimposed on a predetermined line, and character data is interposed between the lines on which the character data is superimposed. An input end to which a video signal having a non-superimposed line is inputted, a line address counter for counting the lines of the video signal, and a count output from the line address counter, wherein the character data is superimposed. A line address converting means for converting a predetermined line into a continuous line address value in the order in which the line occurs, and character data superimposed on the predetermined line by the line address value from the line address converting means. A reception data buffer RAM that holds the data for each data line.

(Operation) According to the present invention, the count output of the character data superimposition section (from the first data to the last data) from the line address counter is determined by the superposition horizontal scanning period before the superimposition section of the character data becomes discontinuous. Since the count value is logically converted so that the count value of the horizontal scanning period, which is the superimposition period again, is continuous, the line address where the numerical value is continuously obtained by skipping the discontinuous period and counting only the number of superimposition periods of the character data is counted. Is obtained. Therefore, the reception data buffer RAM driven by this line address is sequentially packed and stored without leaving a storage area for character data.
The use efficiency of the storage area can be improved.

Hereinafter, the present invention will be described with reference to the illustrated embodiments.

FIG. 1 is a circuit diagram showing one embodiment of a circuit for receiving teletext data according to the present invention. In the figure, a terminal P1 is a signal input terminal to which a video signal subjected to video detection is supplied. The video signal from the terminal P1 is input to the serial / parallel conversion circuit 4 and also to the sync separation circuit 1. The synchronization separation circuit 1 separates the vertical and horizontal synchronization signal components from the video signal, outputs a horizontal synchronization signal HD and a vertical synchronization signal VD, respectively, and outputs the frequency f of the color subcarrier.
The sampling clock 8 / 5fsc reproduced from the sc is output. This sampling clock 8 / 5fsc is connected to the serial /
The character data in the video signal supplied to the parallel conversion circuit 4 is sampled, and the circuit 4 stores 1-byte character data. Reference numeral 2 denotes a byte address counter, which receives the sampling clock 8 / 5fsc and divides the frequency to output a frequency-divided signal for giving an address (hereinafter referred to as a byte address) to data in bytes in each data line. doing. The byte address counter 2
Is 364, and the number of bits of the frequency-divided signal is nine.

Reference numeral 3 denotes a timing signal generator for generating a timing signal for controlling the serial / parallel conversion circuit 4, the byte address counter 2, and the reception data buffer RAM 7. The timing signal generator 3 inputs the frequency-divided signal from the byte address counter 2 and supplies the upper 6 bits to the reception data buffer RAM 7 as the byte address Ab.
A write pulse and a chip enable pulse are supplied to the reception data buffer RAM 7, a load pulse is further supplied to the serial / parallel conversion circuit 4, and a reset pulse is supplied to the byte address counter 2. The load pulse is generated based on a character data extraction pulse DG generated by a timing signal generator 6 described later.

On the other hand, 5 is a line address counter, 6 is a timing signal generator for controlling the line address counter 5,
The timing signal generator 6 is constituted by a predetermined logic circuit, and outputs the horizontal and vertical synchronization signals H from the synchronization separation circuit 1.
D and VD output a line clock PH corresponding to a section from a horizontal scanning period in which character data is superimposed first to a period in which character data is superimposed last, and a reset pulse Rv for resetting the line address counter 5 in one field. And a character data extraction pulse DG is supplied to the timing signal generator 3. Line address counter 5
Is the line clock PH from the timing signal generator 6.
, And outputs the lower four bits V0, V1, V2, V3 of the bits necessary for line counting for one field to the timing generator 6. The timing signal generator 6 detects the count value of the 16th H based on the four signals V0 to V3, and outputs the output V obtained by inverting the signal V2 from the 17th H.
A 3-bit signal consisting of 2 'and signals V0 and V1 is defined as a line address signal AH. The line address signal AH is supplied as an address signal to the reception data buffer RAM 7 together with the byte address signal Ab from the timing signal generator 3, so that the line address and the byte address of the character data stored in byte units can be added. become.

The present embodiment is configured as described above, and FIG.
The operation will be described with reference to FIG. 4 and FIG.

FIG. 2 is a time chart showing a character data holding operation centered on the timing signal generator 3, where D indicates a character data string, CK indicates a sampling clock 8 / 5fsc,
D 'indicates a character data string input to the serial / parallel conversion circuit 4. Further, RH is a reset signal for resetting the byte address counter 2 generated from the timing signal generator 3, LD is a load pulse for determining data of the serial / parallel conversion circuit 4, WP is a write pulse for the reception data buffer RAM 7, CE is a chip enable signal of the RAM7.

The character data string S1 is shifted into the serial / parallel converter 4 bit by bit at the rising timing of the sampling clock 8 / 5fsc, and the serial / parallel converter 4 shifts the last bit data B7 of one byte. When the load pulse LD rises after the timing t1, the bit data B0 to B7
Confirm. When the data in the serial / parallel conversion circuit 4 is determined, the write pulse WP presents a pulse P5, and in synchronization with this, the chip enable signal CE shows a low-level pulse P6, and one byte of data B0 to B7 is received. Data buffer
Written to RAM7.

Note that the byte address Ab at this time is determined by latching the frequency-divided output of the byte address counter 2 at any time when the serial / parallel conversion circuit 4 shifts one byte of data. That is, the sampling clock 8 / 5fsc indicated by CK is reset at t0 and the byte address counter 2 is reset and counted as an initial clock. Thereafter, the byte address Ab is fixed at "0" until the loading by the load pulse LD is completed. doing. The next byte address “2” is determined when the bit data B8 is sampled. Therefore, the divided output of the byte address counter 2 may be latched during that time.

As described above, the character data is stored in the reception data buffer RAM 7 in byte units.

Next, a time chart for adding a line address to the above-mentioned byte unit data will be described with reference to FIG.

In FIG. 3, the symbols indicating the respective waveforms are the same as those in FIG. 1, HD is a horizontal synchronizing signal, VD is a vertical synchronizing signal, Rv is a reset pulse for resetting the line address counter 5, V
The dotted waveforms 0, V1, V2 'and V3 are count outputs output from the line address counter 5, DG is a character data extraction pulse, AH is a line address signal output from the timing signal generator 6, and PH is a line clock. is there.

The horizontal synchronization signal HD has the first H to
The period up to the ninth H is omitted. The timing signal generator 6 resets the line address counter 5 when the low-level pulse P13 of the reset pulse Rv rises to the high level at the beginning t2 of the 10th H. As a result, the counter output by V0 to V3 is “0000” from the upper bit, 11H is “0001”, 12H is “0010”, 13H is “0011”, and 14H is
Indicates “0100”, the 15th H indicates “0101”, the 16th H indicates “0110”, and so on, in the order of binary numbers. Of these four signals, the timing signal generator 6 outputs V0, V1, V2 'as the line address signal AH, so that the address A10 becomes "000", A11 becomes "001", and so on. The data is guided to the reception data buffer RAM 7 together with the byte address signal Ab. As a result, a line address is assigned to the data whose byte address has been determined.

By the way, the output V2 'is inverted from the normal binary operation shown by the dotted line at the 17th H, as shown by the solid line. As a result, the line address AH after the 17th hour
Is “011”, “100”, “101”, “110”, and the 21st
It becomes "111" at the Hth eye.

By operating the line address AH in this way,
The line address signals A10 to A16, A21 sequentially become increment values, and the reception data buffer RAM 7 stores the data lines from the 10th line data to the 21st line in the area where addresses are successively arranged. FIG. 4 shows the state of use of the storage area at this time. As compared with FIG. 6B, the storage area for the 17th to 20th hours can also be used.

Note that DG takes in character data during the high level period. This period corresponds to the 10H to 16H and the 21H.

Thus, according to the present invention, it is possible to hold character data without making a space in the reception data buffer RAM 7,
As a result, a program having a small storage capacity can be selected, or a program having the same capacity can hold a larger number of programs. Also, at the time of the search by the CPU, since the address increment becomes "1" plus progress, there is an advantage that the processing is simplified. Further, the circuit can be simplified because a complicated circuit for detecting a period in which character data is superimposed using a special counter is not used.

[Effects of the Invention] As described above, according to the present invention, data is sequentially stored in the reception data buffer, and there is no area where no data is stored. There is an effect that character data can be received.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a circuit for receiving teletext data according to the present invention, FIGS. 2 and 3 are time charts showing the operation of the embodiment of FIG. 1, and FIG. FIG. 5 is an explanatory diagram showing an area use state of a reception data buffer RAM according to the invention, FIG. 5 is a circuit diagram showing an example of a conventional line address counter circuit, and FIG.
FIG. 8 is an explanatory diagram showing a state of using the area M. 1 ... sync separation circuit, 2 ... byte address counter,
3 timing signal generation circuit 4, serial / parallel conversion circuit 5, line address counter 6, timing signal generator 7, reception data buffer RAM, V0, V1, V
2 ', V3: Line address count output, AH: Line address signal.

Claims (1)

(57) [Claims] An input terminal for inputting a video signal having a line in which character data is superimposed on a predetermined line and having no character data superimposed between the lines on which the character data is superimposed; and a line of the video signal. A line address counter that counts, and a count output from the line address counter.
A line address converting means for converting the line address value into a continuous line address value in the order in which the line occurs, and character data superimposed on the predetermined line by the line address value from the line address converting means, sequentially held in data line units And a receiving data buffer RAM for receiving the received text broadcast data.