JPS6324703Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is designed to combine information signals such as characters and simple patterns that are multiplexed with television signals and transmitted, and characters and simple patterns that are input from tape recorders, telephone lines, etc. The present invention aims to provide a new information receiving device that can receive both low-speed information signals such as graphics using a common processing circuit.

In recent years, systems have been proposed in various countries for multiplexing character information and simple pattern graphic information into television signals and transmitting the multiplexed information. For example, the Teletext system in the UK, Antiope in France
system etc. Also, systems have been proposed in which similar information is recorded on a recording medium such as a cassette tape and transmitted, or transmitted via a telephone line. An example of the latter is View in the UK.
There are Data (Prestel) systems, etc. However,
Since each of these systems was developed as an individual system, there was an inconvenience in that if one wanted to receive information from both, separate receiving devices suitable for each had to be provided.

Therefore, the present invention has been devised to make it possible to receive both the information multiplexed into such television signals and the information transmitted by recording devices and telephone lines (hereinafter referred to as low-speed information sources) with a simple configuration. The purpose of this invention is to provide an information receiving device that can perform the following functions.

For this reason, in the present invention, an information signal multiplexed with a television signal and transmitted is received, written into a memory using a clock synchronized with the information signal, stored, and then read from this memory at an arbitrary speed. In addition to reading and generating video signals for display, information signals of different formats input from low-speed information sources such as recording devices and telephone lines are transferred to the input interface circuit by a clock synchronized with the information signals. Then, while converting this into the same format as the television multiplexed information signal, it is read from this buffer memory using a clock equivalent to the clock for the television multiplexed information signal, and the above television multiplexed information is written. By converting it into a signal equivalent to that for the television multiplexed information signal, it can be added to the processing circuit for the television multiplexed information signal and processed as is, and this processing circuit can be used in common to process information from low-speed information sources. This device is characterized in that the signals are also written and stored in the memory mentioned above.

In this way, all the information processing circuits for receiving television multiplexed information signals can be used as they are for low-speed information signals, and the configuration is extremely simple, just by adding an interface circuit such as a buffer memory. , it is possible to receive both information signals multiplexed into television signals and information signals from recording devices and telephone lines.

Hereinafter, the present invention will be described in detail with reference to the drawings showing one embodiment thereof.

First, FIG. 1 shows the information signals handled here. This information signal is a 16-bit clock run-in signal.
RI, 8-bit framing code signal FC,
A total of 40 bits of control signals consisting of an 8-bit page code signal PC and an 8-bit row code signal RC, and a total of 256 bits of character code signals for 32 characters each consisting of an 8-bit code signal. Therefore, the signal for one row is composed of a total of 296 bits. This character code signal is obtained by converting alphanumeric characters, symbols, etc. into binary code signals of 8 bits (of which 1 bit is a parity check bit).

When such an information signal is multiplexed with a television signal and transmitted, it has a data rate of about 5 to 6 MHz, in the format shown in Figure 1, and can be transmitted during any horizontal scanning period during the vertical retrace period. For example, one line is superimposed on the 20th H (in an even field, it is the 283rd H, but in the following description both are referred to as the 20th H) and transmitted in a time-division manner. The clock of the information signal in that case is synchronized to the synchronization signal and the color subcarrier of the television signal.

On the other hand, when such information signals are recorded on a recording device such as an audio tape recorder and transmitted, the recordable bandwidth is narrow, so it takes several kilograms of data.
The data is kept at a low data rate of about Hz or less, and unlike the time-division format used in television multiplexing, data is recorded and read out one line at a time in succession. When data is transmitted over a telephone line, it is similarly transmitted one line at a time at a low data rate.

Next, an embodiment of a receiving apparatus that receives both such a television multiplexed information signal and a low-speed information signal will be described. Figure 2 shows its basic configuration, where 1 is a video detection circuit that detects the multiplexed television signal received by the television receiver circuit, 2 is a sync separation circuit, and 3 is a vertical detection circuit for the television signal. A waveform shaping circuit that shapes the information signal etc. superimposed on the 20th H during the blanking line (VBL) period into a binary signal, 4 is a gate pulse generator that generates a gate pulse that becomes high level only in the 20th H. A circuit 5 is a gate circuit that uses this gate pulse to take out only the information signal superimposed on the 20th H, and 6 is an information processing circuit that processes the information signal.

This information processing circuit 6 includes a clock regeneration circuit 7 that uses the clock run-in signal RI in the information signal to regenerate a sampling clock synchronized therewith, and uses this sampling clock to generate the information signal output from the gate circuit 5. A control signal detection circuit 8 that samples and stores and detects the control signal portion, a main memory 9 consisting of a high-speed RAM with a capacity of, for example, 256 bits x 20 lines, which stores character code signals for about 20 lines, and its columns. Address circuit 1
0, its row address circuit 11, main memory 9
The video signal generating circuit 12 includes a video signal generation circuit 12 such as a character generator that converts a character code signal read from a character code signal into a video signal for display, and an amplifier circuit 13. 1
4 is a switching circuit, and 15 is a cathode ray tube for display.

The above sections are built into the television receiver 16, or the waveform shaping circuit 3 to information processing circuit 6 are attached externally in the form of an adapter.

The operation of this information processing circuit 6 is basically the same as that of the known Teletext system, in which the character code signal of the received information signal is written and stored in the main memory 9 according to the control signal, Thereafter, the signal is read out in synchronization with the cathode ray tube 15, and converted into a video signal for display by the video signal conversion circuit 12.

Further, 17 is a low-speed information signal source such as a tape recorder or an acoustic coupler for connecting telephone lines, and 18 is a high-speed information signal having a data rate equivalent to that of the television multiplexed information signal. (hereinafter referred to as a converted information signal); 19 is a switching circuit that switches between the television multiplexed information signal and selectively supplies it to the information processing circuit 6;

In this input interface circuit 18, a low-speed information signal supplied from the low-speed information signal source 17 is written into a buffer memory, and is then applied to the television multiplexed information signal from the clock recovery circuit 7 via the terminal _P1 . It is read out by a readout clock equivalent to the clock, and is converted into an information signal with _a data rate equivalent to that of the television multiplexed information signal.
By being output only during the 20th gate pulse time, it is converted into the same time division format as the television multiplexed information signal, and is supplied to the information processing circuit 6 from the terminal P ₃ via the switch 19. . Note that the low-speed information signal source 17 and the information processing circuit 6
of low-speed information signals to synchronize operation with
The FC code detection output is applied to the clock recovery circuit 7 from terminal _P4 .

Next, the detailed structure and operation of this device will be explained with reference to FIGS. 3 and 4. 3 shows the information processing circuit 6 and its surroundings, and FIG. 4 shows the input interface circuit 18 and its surroundings.

First, when receiving a television multiplexed signal, the switch 19 is switched to the gate circuit 5 side, and the information signal from the gate circuit 5 is applied to the information processing circuit 6. First, the clock run-in signal RI is extracted by the RI signal extraction circuit 20 of the clock regeneration circuit 7, amplified by the tuned amplifier circuit 21, and then applied to the oscillation circuit 22. is created.
When receiving the television multiplexed information signal, this clock is applied to the control signal detection circuit 8 via gates 23X and 23Z. Therefore, the FC signal detection circuit 25 detects the framing code signal in the information signal.
When FC is detected, its detection output is sent to gate 25
It is applied to the sampling clock generation circuit 26 via X and 25Z, and a sampling clock for each subsequent signal processing is created. Using this sampling clock, the page code signal PC is sampled and detected in the PC signal detection circuit 27.
Furthermore, the RC signal detection circuit 28 also detects the row code signal RC.
is sampled and detected. The detected row code signal RC is applied to the row address circuit 11, and this signal specifies the row address at which the character code signal is written into the main memory 9.
On the other hand, the column address circuit 10 is reset by the clock generated by the last bit of the sampling clock for row code signal detection, and the clock from the oscillation circuit 22 is reset to the gate 2 at the 20th H.
By being added to the column address circuit 10 via 9W and 29S and counted, the write column address of the character code signal to the main memory 9 is designated.

Through the above operations, the character code signal of the television multiplexed information signal is written and stored in a predetermined storage device of the main memory 10.

On the other hand, during the display period, for example, during the 200H period from the 41st to the 240th H in the cathode ray tube 15, the flip-flop FF 33 is set by a horizontal pulse slightly delayed by the horizontal pulse delay circuit 30, and from that point on, the gated oscillator 32 starts oscillating. to generate a read clock. During reading, when the read clock counts 256 bits by the counter 23, the output resets the flip-flop 31 via the gates 34W and 34S, thereby generating a 256-bit read clock every H. This read clock is connected to gates 29R, 2
It is applied to the column address circuit 10 via 9S, and is counted to designate a column address at the time of reading.

At this time, in the row address circuit 11, the 41st to 240H
Horizontal pulses are counted during the eye display period, and the row address at the time of reading is specified. In this way, character code signals are read out from the main memory 9 during the display period in synchronization with the scanning of the cathode ray tube 15.
The character generator of the video signal conversion circuit 12 converts the video signal into a video signal for display, and then the cathode ray tube 15
in addition to, for example, 36 per line on that screen.
Approximately 20 lines of character information are displayed.

Next, a section that processes the low-speed information signal supplied from the low-speed information signal source 17 will be explained. For this process, the switch 19 is first switched to the terminal P3 side, and the input interface circuit 18 is switched to the terminal _P3 side.
The converted information signal from is applied to the information processing circuit 6. Furthermore, the clock generated by the gated oscillator 32 from the clock regeneration circuit 7 is sent to the gate 23Y on the 20th H as the same as the clock for receiving the television multiplexed information signal (the clock generated by the oscillation circuit 22). and applied to the input interface circuit 18 from terminal _P1 as a read clock. Note that this read clock is generated by taking out the 272-bit count output of the counter 33 via the gates 34W and 34S and resetting the flip-flop 31.
Only 272 bits are generated. Further, as will be described later, when the detection output when the framing code signal C of the low-speed information signal is detected at the input interface is applied via the terminal _P4 , the flip-flop 35 is reset, and the subsequent 20th H By being set at the trailing edge of the gate pulse, the first signal from gate 36 after detection of the FC signal is
A 1H width gate pulse for read control is generated at the 20th H, which determines the read clock generation period, and this gate pulse is also connected to the terminal.
P ₂ is supplied to the input interface circuit 18 .

On the other hand, in the input interface circuit 18, as shown in FIG. 4, the signal inputted from the low-speed information signal source 17 is first reproduced by the waveform reproduction circuit 37. A binary low-speed information signal is obtained by decoding, waveform shaping, etc. Next, using the clock run-in signal RI of this low-speed information signal, a clock regeneration circuit reproduces a sampling clock synchronized with the low-speed information signal, and using this, the sampling circuit 39 samples the signal to determine the correct low-speed clock. Create information signals. This low-speed information signal is passed through gates 40A and 40B.
The data is input into two buffer memories 41A and 41B, respectively.

At the same time, the FC signal detection circuit 42 detects the framing code signal FC, and each time the framing code signal FC is detected,
Detects input of information signals for rows. However, since the framing code signal FC is added to the beginning of one line of low-speed information signals, when it is detected, it is detected that the previous one line of low-speed information signals has been input. It turns out. Therefore, this FC detection output is used to trigger the flip-flop 43, and each time the FC detection output is detected, the flip-flop 43 is triggered.
Invert the output of FF43. The two outputs of this FF43 are gates 40A, 40B, 44A to 46B
, and these are switched every time one line of the low-speed information signal is input. So for example now FF
If the Q output of 43 is at a high level,
The low-speed information signal output from the sampling circuit 39 is input to the buffer memory 41A via the gate 40A, and the clock from the clock recovery circuit 38 is input to the buffer memory 4 via the gates 44B and 44C.
Since it is added to 1A, after that the low speed information source 17
The signal supplied from the buffer memory 41A will be written into the buffer memory 41A. On the contrary, buffer memory 4
Since no input is applied to the buffer memory 41B and the read clock supplied from the information processing circuit 6 through the terminal _P1 is applied through the gates 45A and 45C, the low-speed information previously written in the buffer memory 41B is The signal is read out at high speed, converted into a conversion information signal, passed through the gates 46B and 46C, and then taken out at the gate 47 at the 20th H by the gate pulse from the terminal _P2 , and sent to the switch from the terminal _P3 . Information processing circuit 6 via 19
is supplied to What should be noted here is that this converted information signal is read out using the same readout clock as used for receiving television multiplexed information signals, so it is equivalent to the television multiplexed information signal.
and the conversion information signal is the first part of the television signal.
Since it is supposed to exist only in the 20th H and has the same time division format as the television multiplexed information signal, the information processing circuit 6
After the control signal is supplied to the main memory 9, the control signal is detected and written in the main memory 9 in the same manner as described above. However, in this case, the buffer memory 41
Since the conversion information signal from the page code signal PC which is later than the framing code signal FC is read out and supplied from B, the clock from the gated oscillator 32 is also used for receiving it. , the FC detection output uses the detection output from the input interface circuit.

In this way, when the input of one row of low-speed information signals is completed and the framing code signal of the next row is detected, the FF 43 is inverted, and the writing and reading states of the buffer memories 41A and 41B are reversed, resulting in the above-mentioned state. The same action is repeated.

In this way, low-speed information signals from low-speed information signal sources such as tape recorders and telephone circuits can also be written into the main memory 9 using the information processing circuit 6 for receiving television multiplexed information signals, and then read out and displayed. The Rukoto.

As detailed above, according to the present invention, low-speed information signals obtained from a tape recorder or telephone line are television multiplexed by an input interface circuit in a continuous format different from the time division format of television multiplexed information signals. converts the information signal into a time-division format information signal that exists at the same high speed and in the same transmission time as the television multiplexed information signal, and switches between the format-converted information signal and the television multiplexed information signal and supplies it to a common information processing circuit. By doing so, the information processing circuit of the device that receives the information signal multiplexed with the television signal and transmitted can be used as is, and the low-speed and continuous information input from the tape recorder, telephone line, etc. The result is a useful device capable of receiving even formatted information signals.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing the transmission mode of an information signal, FIG. 2 is a block diagram of an information receiving device according to an embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams of the main parts of the device. be. 1...Video detection circuit, 2...Synchronization separation circuit, 3
... Waveform shaping circuit, 4 ... Gate pulse generation circuit, 5 ... Gate circuit, 6 ... Information processing circuit, 7
... Clock regeneration circuit, 8 ... Control signal detection circuit, 9 ... Main memory, 10 ... Column address circuit, 11 ... Row address circuit, 12 ... Video signal conversion circuit, 13 ... Amplification circuit, 14 ... ...Switching circuit, 15...Cathode ray tube, 17...Low speed information signal source, 18...Input interface circuit.

Claims (1)

[Scope of utility model registration request] gate means for extracting a television multiplexed information signal from a television signal that is multiplexed and transmitted during a vertical blanking period; and a gate means for generating a clock synchronized with the television multiplexed information signal and The information processing means reads the television multiplexed information signal, writes it in a memory, stores it, reads it from the memory, and converts it into a video signal for displaying an information image, and the information processing means reads the television multiplexed information signal, writes it in a memory, and converts it into a video signal for displaying an information image. a receiving means for receiving a low-speed information signal in a format different from the television multiplexed information signal; a buffer memory for writing and storing the low-speed information signal; and a buffer memory for transmitting the low-speed information signal from the buffer memory to the television multiplexed information signal. and reading means for reading at the same speed as and at the same time as the existence time of the television multiplexed information signal, to convert the low speed information signal into a signal equivalent to the television multiplexed information signal in speed and time. an input interface circuit, means for supplying a clock equivalent to the clock for reading the television multiplexed information signal to the input interface circuit as a clock for speed conversion, and a clock for speed conversion by the input interface circuit; and switching means for inputting a high-speed converted low-speed information signal equivalent to the supplied television multiplexed signal to the information processing means instead of the television multiplexed information signal.