KR20020090741A - thin film transistor array panel for liquid crystal display and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A TFT substrate for a liquid crystal display device and a fabricating method thereof are provided to form uniform parasitic capacitances with pixel electrodes and auxiliary data lines via an insulating film regardless of a distance between the data lines and the pixel electrodes. CONSTITUTION: A TFT substrate for a liquid crystal display device includes gate wires having traverse gate lines(21) and gate electrodes(22) as a part of the gate lines, a gate insulating film formed on the substrate covering the gate wires, a semiconductor layer(41) formed on the gate insulating film, a resistant contact layer formed on the semiconductor layer, data wires having data lines(61) formed on the resistant contact layer, source electrodes(62) as a part of the data lines, and drain electrodes(63) separated from the source electrodes, a protecting film formed on the data wires and having contact holes(73,74) for exposing the data lines, pixel electrodes(80) formed on the protecting film, and auxiliary data lines(81) formed on the same layer with the pixel electrodes and connected to the data lines via the contact holes, wherein a width of the auxiliary data lines is larger than the data lines by 0.2-5micrometer at both sides.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {thin film transistor array panel for liquid crystal display and manufacturing method}

The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof, and more particularly, to a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same that can ensure a uniform screen.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device for controlling the amount of light transmitted by rearranging them.

One substrate of such a liquid crystal display device generally includes a thin film transistor for switching a voltage applied to an electrode. In addition to the thin film transistor, the substrate includes a wiring including a gate line and a data line and a gate line receiving a signal from the outside. And gate pads and data pads respectively transferred to the data lines. A pixel electrode electrically connected to the thin film transistor is formed in the pixel region defined by the intersection of the gate line and the data line.

When driving such a liquid crystal display, (+) voltage and (-) voltage are periodically inverted and input to the data line, and the pixel electrode voltage changes with the change of the data line voltage due to the coupling between the data line and the pixel electrode. On the other hand, the thin film transistor substrate is used to form the wiring, the thin film transistor and the pixel electrode using a number of photolithography process, the relative position between the wiring, the thin film transistor and the pixel electrode pattern is uneven due to the alignment error of the mask during the photo process. Will be lost. In other words, when the substrate surface is separated into several parts using a stepper and exposed, the distance between the patterns becomes uneven due to the difference in alignment between the separated parts. Even when exposing at once, the distance between each layer pattern becomes uneven due to the interlayer alignment error. However, when the distance between the pixel electrode and the data wiring becomes uneven, the degree of coupling between the pixels is different, resulting in poor stitches and screen irregularities, thereby degrading image quality.

The technical problem to be achieved by the present invention is to prevent the image quality degradation caused by the coupling unevenness between the pixel electrode and the data line.

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first embodiment of the present invention.

2 is a cross-sectional view taken along the line II-II in FIG.

3A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention;

FIG. 3B is a cross sectional view taken along line IIIb-IIIb in FIG. 3A;

FIG. 4a is a layout view in the next step of FIG. 3a;

4B is a cross sectional view taken along line IVb-IVb in FIG. 4A;

FIG. 5A is a layout view of the next step of FIG. 4A;

FIG. 5B is a cross sectional view taken along the line Vb-Vb in FIG. 5A;

FIG. 6a is a layout view in the next step of FIG. 5a;

FIG. 6B is a cross sectional view taken along the line VIb-VIb in FIG. 6A;

FIG. 7 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

8 is a cross-sectional view taken along line VII-VII in FIG. 7,

9A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to the second embodiment of the present invention;

FIG. 9B is a cross sectional view taken along the line VIIb-VIIb in FIG. 9A;

FIG. 10A is a layout view in the next step of FIG. 9A;

FIG. 10B is a cross-sectional view taken along the line VIIb-VIIb in FIG. 10A;

FIG. 11A is a layout view in the next step of FIG. 10A;

FIG. 11B is a cross-sectional view taken along the line XIB-XIB in FIG. 11A,

12A is a layout view at the next step of FIG. 11A;

FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb in FIG. 12A.

In order to achieve this problem, the present invention forms an auxiliary data line larger than the line width of the data line in the same layer as the pixel electrode.

According to the present invention, a gate wiring including a gate line and a gate electrode that is part of the gate line is formed on an insulating substrate, and a gate insulating film is formed on the gate wiring. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating film, and a data line including a data line, a source electrode that is part of the data line, and a drain electrode separated from the source electrode is formed on the ohmic contact layer. A protective film having a contact hole for exposing the data line is formed on the data line, and a pixel electrode is formed on the protective film. An auxiliary data line connected to the data line through a contact hole is formed in the same layer as the pixel electrode. Here, the line width of the auxiliary data line is preferably formed to be 0.2 μm to 5 μm larger on both sides than the line width of the data line.

According to another embodiment of the present invention, a gate line including a gate line and a gate electrode that is part of the gate line is formed on an insulating substrate, and a gate insulating film is formed on the gate line. The pixel electrode is formed on the gate insulating film, and the auxiliary data line is formed on the same layer as the pixel electrode. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating film, and a data line including a data line, a source electrode that is part of the data line, and a drain electrode separated from the source electrode is formed on the ohmic contact layer. A protective film having an opening for exposing the pixel electrode is formed. At this time, the line width of the auxiliary data line is preferably 0.2 μm to 5 μm larger on both sides than the line width of the data line.

The pixel electrode may be made of any one of a transparent conductive material such as ITO and IZO or a conductive material having excellent reflectance such as aluminum and silver.

When manufacturing a thin film transistor substrate for a liquid crystal display according to the present invention, first, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate, and a gate insulating film is formed. Next, the semiconductor layer and the ohmic contact layer are sequentially formed, and a data line including a data line, a source electrode, and a drain electrode is formed. Next, a passivation layer having a contact hole for exposing the data line is formed, and the pixel electrode connected to the drain electrode and the same layer as the pixel electrode are connected to the data line through the contact hole and the two sides of the data line are positioned between the two sides. A data line is formed.

When manufacturing a thin film transistor substrate for a liquid crystal display according to another exemplary embodiment of the present invention, first, a gate wiring including a gate line and a gate electrode is formed on an insulating substrate, and a gate insulating film is formed. Next, the auxiliary data line is formed of the same layer as the pixel electrode and the pixel electrode. Next, the semiconductor layer and the ohmic contact layer are sequentially formed. Next, a data line including a data line, a source electrode, and a drain electrode positioned between two sides of the auxiliary data line is formed, and a protective film having a contact hole exposing the pixel electrode is formed.

In the present invention, since the distance between the pixel electrode and the auxiliary data line is constant, the parasitic capacitance formed between the pixel electrode and the auxiliary data line is the same even though the distance between the pixel electrode and the auxiliary data line varies depending on the position, so that the screen between pixels due to the difference in left and right parasitic capacitance Unevenness can be prevented.

Next, a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same. do.

First, the structure of the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

1 and 2, on the insulating substrate 10, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten alloy (MoW), chromium (Cr), tantalum (Ta) and the like Gate wirings 21, 22, and 23 made of a metal or a conductor are formed. The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23.

The gate wirings 21, 22, and 23 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance, and the other layer is formed of a material having good contact properties with other materials. For example, a double layer of Cr / Al (or an Al alloy) or Al ( Or an Al alloy) / Mo double layer.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate lines 21, 22, and 23.

A semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30, and a resistivity made of a semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. The contact layers 52 and 53 are formed separated from both sides with respect to the gate electrode 22.

On the ohmic contacts 52 and 53, data wirings 61, 62, 63 and 64 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium and tantalum are formed. The data line includes a data line 61 extending in the vertical direction, a source electrode 62 which is a part of the data line 61, a drain electrode 63 facing the source electrode 62 around the gate electrode 22, and data. And a data pad 64 connected to the line 61 to receive an image signal from the outside and transmit the image signal to the data line 61.

The data wirings 61, 62, 63, and 64 can be formed in a single layer similarly to the gate wirings 21, 22, and 23, but can also be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials.

A protective film 70 made of silicon nitride or an organic insulating film is formed on the data lines 61, 62, 63, and 64 and the gate insulating film 30. The passivation layer 70 has not only a contact hole 73 exposing the gate pad 23 together with the gate insulating film 30, but also a contact hole 74 and a drain electrode 63 exposing the data pad 64. It has a contact hole 72 that exposes. Further, contact holes 711, 712, and 713 are formed in the passivation layer 70 to expose the data lines 61 and are positioned at a predetermined interval.

On the passivation layer 70, a pixel electrode 80, an auxiliary data line 81, and an auxiliary material made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a conductive material having high reflectivity such as aluminum or silver The gate pad 83 and the auxiliary data pad 84 are formed.

The pixel electrode 80 is connected to the drain electrode 63 through the contact hole 72 to receive an image signal. The auxiliary data line 81 overlaps the data line 61 and is connected to the data line 61 through contact holes 711, 712, and 713. Here, the auxiliary data line 81 is formed to be 0.2 µm to 5 µm larger in the horizontal direction than the line width of the data line 61, so that the distance from the pixel electrode 80 is closer than that of the data line 61. Therefore, the parasitic capacitance formed between the pixel electrode 80 is more influenced by the auxiliary data line 81 than the data line 61 itself. However, since the auxiliary data line 81 is formed by the same photolithography process as that of the pixel electrode 80, the distance unevenness due to the mask alignment error does not occur. Therefore, the parasitic capacitance formed between the pixel electrode 80 and the data line 61 and the auxiliary data line 81 becomes almost uniform throughout the substrate 10. The auxiliary gate pad 83 and the auxiliary data pad 84 are connected to the gate pad 23 and the data pad 64 through contact holes 73 and 74, respectively, which are pads 23 and 64 and external circuits. It serves to complement the adhesion with the device and to protect the pads 23 and 64.

As described above, in the first exemplary embodiment of the present invention, the auxiliary data line 81 forms a parasitic capacitance between the pixel electrode 80 together with the data line 61 on the same layer as the pixel electrode 80. Even if the distance between the 61 and the pixel electrode 80 varies depending on the position, the parasitic capacitance formed between the pixel electrode 80 and the auxiliary data line 81 is the same, so that screen unevenness between pixels due to the difference in left and right parasitic capacitances can be prevented. Can be.

In addition, when the data line 61 is disconnected, since the data line 61 is connected to the auxiliary data line 81 through the contact holes 711, 712, and 713, a signal may be transmitted by bypassing the disconnection point. .

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 6B and FIGS. 1 and 2.

First, as shown in FIGS. 3A and 3B, a gate wiring conductor or a metal is deposited on the insulating substrate 10 to a thickness of 1,000 Å to 3,000 으로 by sputtering, and patterned by a photolithography process using a mask. As a result, a gate wiring including the gate line 21, the gate electrode 22, and the gate pad 23 is formed.

Next, as shown in FIGS. 4A and 4B, the gate insulating layer 30, the amorphous silicon layer, and the amorphous silicon layer doped with n-type impurities are respectively 1,500 kPa to 5,000 using chemical vapor deposition (CVD). 증착, 500 Å to 1,500 Å and 300 Å to 600 Å in thickness, and the two upper layers are patterned by a photolithography process using a mask to form a semiconductor layer 41 and an ohmic contact layer 51.

Next, as shown in FIGS. 5A and 5B, a conductor or a metal for data wiring is deposited to a thickness of 1,500 kPa to 3,000 kPa by a method such as sputtering, and patterned by a photolithography process using a mask to form a data line 61 and a source. A data line including an electrode 62, a drain electrode 63, and a data pad 64 is formed. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIGS. 6A and 6B, silicon nitride is deposited or an organic insulating layer is coated to form the passivation layer 70, and then patterned by a photolithography process using a mask to form the drain electrode 63 and the gate pad 23. And contact holes 72, 73 and 74 for exposing the data pad 64 and contact holes 711, 712 and 713 for exposing the data line 61, respectively.

Next, as shown in FIGS. 1 and 2, a transparent conductive material such as ITO or IZO, or a metal having excellent reflectivity such as aluminum or silver is deposited on the protective layer 70 to a thickness of 400 μs to 500 μs by a sputtering method. The pixel electrode 80, the auxiliary data line 81, the auxiliary gate pad 83, and the auxiliary data pad 84 are formed by patterning by a photolithography process using a mask.

In the first embodiment of the present invention, the pixel electrode 80 is formed on the passivation layer 70 as an example. However, the present invention may also be applied when the pixel electrode 80 is formed under the passivation layer 70. Can be.

First, a structure of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 7 and 8.

As shown in FIGS. 7 and 8, gate wirings 21, 22, and 23 formed of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, and tantalum are formed on the insulating substrate 10. . The gate wiring is connected to the gate line 21 extending in the horizontal direction, the gate electrode 22 that is part of the gate line 21, and the end of the gate line 21, and receives a scan signal from the outside to the gate line 21. A gate pad 23.

A gate insulating film 30 made of silicon nitride is formed on the gate wirings 21, 22, and 23.

An auxiliary data line 81 is formed on the gate insulating layer 30 by a transparent conductive material such as ITO or IZO or a conductive material having excellent reflectivity such as aluminum or silver, and overlaps with the data line 61 described later. The pixel electrode 80 is formed between the auxiliary data lines 81.

In addition, a semiconductor layer 41 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30, and a semiconductor such as amorphous silicon doped with n-type impurities such as phosphorus (P) is formed on the semiconductor layer 41. The ohmic contacts 52 and 53 formed on the gate electrode 22 are separated from each other.

On the ohmic contacts 52 and 53, data wirings 61, 62, 63 and 64 made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium and tantalum are formed. The data line faces the source electrode 62 centering on the data line 61 extending in the vertical direction, the source electrode 62 which is a part of the data line 61, and the gate electrode 22, and a part of the pixel electrode 80. And a drain electrode 63 overlapping the data line 61 and a data pad 64 that is connected to the data line 61 and receives an image signal from the outside and transfers the image signal to the data line 61.

A protective film 70 made of silicon nitride or an organic insulating film is formed on the data lines 61, 62, 63, and 64 and the gate insulating film 30. The passivation layer 70 has an opening 72 exposing the pixel electrode 80, and not only has a contact hole 73 exposing the gate pad 23 together with the gate insulating film 30, but also a data pad ( It has a contact hole 74 that exposes 64. Here, only the passivation layer 70 and the gate insulating layer 30 on the gate pad 23 and the data pad 64 may be removed, but the passivation layer 70 and the gate insulating layer 30 therebetween may also be removed. .

As described above, the data lines 61 are overlapped with each other on the auxiliary data line 81, and the auxiliary data lines 81 are formed to have a width of 0.2 μm to 5 μm larger than the line width of the data line 61 in the left and right directions, respectively. A coupling is formed with the electrode 80.

In the second embodiment of the present invention, as in the first embodiment, the pixel electrode 80 forms parasitic capacitance together with the auxiliary data line 81, and the auxiliary electrodes positioned on the left and right of the pixel electrode 80 and the pixel electrode 80 are formed. Since the parasitic capacitances between the data lines 81 are the same, screen unevenness between pixels due to the difference in the left and right parasitic capacitances can be prevented.

In addition, when the data line 61 is disconnected, the data line 61 is connected to the auxiliary data line 81 so that a defect due to disconnection can be prevented.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 9A to 12B and FIGS. 7 and 8.

First, as shown in FIGS. 9A and 9B, a gate wiring conductor or metal is deposited on the insulating substrate 10 by a sputtering method, and patterned by a photolithography process using a mask to form a gate line 21 and a gate electrode 22. ) And a gate wiring including the gate pad 23.

Next, as illustrated in FIGS. 10A and 10B, after the gate insulating layer 30 is deposited, a transparent conductive material such as ITO or IZO or a conductive material having excellent reflectivity such as aluminum or silver is deposited and patterned by a method such as sputtering. The pixel electrode 80 and the auxiliary data line 81 are formed.

Next, as shown in FIGS. 11A and 11B, the amorphous silicon layer and the amorphous silicon layer doped with n-type impurities are sequentially deposited by using a chemical vapor deposition method, and patterned by a photolithography process using a mask to form a semiconductor layer 41 and The ohmic contact layer 51 is formed.

Next, as shown in FIGS. 12A and 12B, a conductor or a metal for data wiring is deposited by a method such as sputtering, and patterned by a photolithography process using a mask to form a data line 61, a source electrode 62, and a drain electrode ( 63) and a data line including the data pad 64 is formed. Next, the ohmic contact layer 51 not covered by the source electrode 62 and the drain electrode 63 is removed to separate the two portions 52 and 53.

Next, as shown in FIG. 7 and FIG. 8, an opening for exposing the pixel electrode 80 by depositing silicon nitride or by coating an organic insulating layer to form the passivation layer 70 and patterning the photolithography process using a mask. Contact holes 73 and 74 are formed to expose 72, gate pad 23 and data pad 64, respectively.

As described above, in the present invention, the pixel electrode forms a parasitic capacitance together with the auxiliary data line with an insulating film interposed therebetween. However, the parasitic capacitance formed between the pixel electrode and the auxiliary data line is the same even if the distance between the data line and the pixel electrode varies depending on the position. The screen unevenness between pixels due to the difference in capacitance can be prevented.

Claims (5)

A gate wiring including a gate line formed on an insulating substrate and a gate electrode which is a part of the gate line; A gate insulating film covering the gate wiring, A semiconductor layer formed on the gate insulating film, An ohmic contact layer formed on the semiconductor layer, A data line including a data line formed on the ohmic contact layer, a source electrode which is a part of the data line, and a drain electrode separated from the source electrode; A protective film formed on the data line and having a contact hole for exposing the data line; A pixel electrode formed on the passivation layer, An auxiliary data line formed of the same layer as the pixel electrode and connected to the data line through the contact hole; Including; The line width of the auxiliary data line is 0.2 μm to 5 μm larger on both sides than the line width of the data line. A gate wiring including a gate line formed on an insulating substrate and a gate electrode which is a part of the gate line; A gate insulating film covering the gate wiring, A pixel electrode formed on the gate insulating film, An auxiliary data line formed of the same layer as the pixel electrode; A semiconductor layer formed on the gate insulating film An ohmic contact layer formed on the semiconductor layer, A data line including a data line formed on the ohmic contact layer, a source electrode which is a part of the data line, and a drain electrode separated from the source electrode; A protective film having an opening that exposes the pixel electrode. Including; The line width of the auxiliary data line is 0.2 μm to 5 μm larger on both sides than the line width of the data line. The method of claim 1 or 2, The pixel electrode may be formed of any one of a transparent conductive material such as ITO and IZO or a conductive material having excellent reflectivity such as aluminum and silver. Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film, Forming a semiconductor layer, Forming an ohmic contact layer, Forming a data line including a data line, a source electrode and a drain electrode, Forming a protective film having a contact hole exposing the data line; Forming an auxiliary data line connected to the data line through the contact hole with a pixel electrode connected to the drain electrode and the same layer as the pixel electrode, and having two sides of the data line positioned between the two sides; Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. Forming a gate wiring including a gate line and a gate electrode on the insulating substrate, Forming a gate insulating film, Forming an auxiliary data line with a pixel electrode and the same layer as the pixel electrode; Forming a semiconductor layer, Forming an ohmic contact layer, Forming a data line including a data line, a source electrode, and a drain electrode positioned between two sides of the auxiliary data line; Forming a protective film having a contact hole exposing the pixel electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a.