JP2000352940A - Matrix array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a matrix array substrate which does not incure the reduction of the aperture ratios of a planar display device even when a signal line 1 has a redundant wiring structure in an matrix array substrate for the planar display device. SOLUTION: A signal line 1 is constituted by allowing a low resistance conductive layer 13 which is produced simultaneously with a drain electrode 22 and an auxiliary electrode layer 14 which is produced simultaneously with a pixel electrode 3 are conducted with each other through a contact hole 15 penetrating the insulating film existing between these layers. In the signal line 1 of such a redundant wiring structure, a contact hole forming part 11 whose width is wider than that of the other part 12 of the signal line 1 is provided at the intersection part with a scanning line 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix array substrate used for a flat panel display represented by a liquid crystal display.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have been used in various fields as display devices such as personal computers, word processors or TVs, and as projection display devices, taking advantage of the features of thinness, light weight, and low power consumption. ing.

Among them, an active matrix type display device in which a switch element is electrically connected to each pixel electrode is capable of realizing a good display image without crosstalk between adjacent pixels. Have been done.

[0004] The structure of the active matrix type liquid crystal display device of the light transmission type will be briefly described below.

Generally, in an active matrix type liquid crystal display device, a matrix array substrate (hereinafter, referred to as an array substrate) and an opposing substrate are arranged close to each other at a predetermined interval, and are provided on the surface layer of both substrates during this interval. The liquid crystal layer is held via the aligned alignment film.

In an array substrate, for example, a plurality of signal lines as an upper metal wiring pattern and a plurality of scanning lines as a lower metal wiring pattern are formed on a transparent insulating substrate such as glass via an insulating film. ITO (Indium-Tin-Oxid) is arranged in a grid, and in an area corresponding to each square of the grid.
A pixel electrode made of a transparent conductive material such as e) is provided. At each intersection of the grid, a switching element for controlling each pixel electrode is arranged. When the switching element is a thin film transistor (hereinafter abbreviated as TFT), the gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the pixel electrode. It is connected to the.

[0007] The opposing substrate is formed by disposing an opposing electrode made of ITO or the like on a transparent insulating substrate such as glass, and a color filter layer for realizing color display.

[0008] In the past, in the manufacture of an array substrate, there has been a problem that the yield and the manufacturing efficiency are reduced due to a disconnection failure of a signal line. In particular, when the signal line width is narrowed to improve the aperture ratio, a disconnection defect due to dust at the time of resist exposure has become a problem. Further, when a large substrate is divided into a plurality of regions and each region is sequentially exposed (divided exposure), a disconnection defect due to a displacement of a division boundary has been a problem.

Therefore, in Japanese Patent Application Laid-Open No. 9-101541, a redundant wiring structure of a first conductive layer and a second conductive layer which are superposed via an insulating film is provided for a signal line. It has been proposed to electrically connect the second conductive layer by a contact hole.

A conventional array substrate based on the proposal of JP-A-9-101541 will be described below.

In this example, the switching element is of an inverted stagger type in which an extended portion of the scanning line is used as a gate electrode.
An amorphous silicon (a-Si: H) layer as a semiconductor layer and a phosphorus-doped amorphous silicon (n) as an ohmic contact layer are formed on the gate electrode via a first insulating film made of silicon oxide and silicon nitride. ⁺ a-Si: H)
The layers are arranged. On top of this, aluminum (Al)
Electrodes and drain electrodes made of a low-resistance conductive layer mainly composed of molybdenum or molybdenum (Mo) are arranged. The wiring pattern of the low-resistance conductive layer including the source electrode and the drain electrode is covered with a second insulating film made entirely of a silicon nitride film.

A pixel electrode made of an ITO layer is disposed on the second insulating film, and is electrically connected to a source electrode via a contact hole provided in the second insulating film.

In such a configuration, the signal line has a redundant wiring structure of a first conductive layer formed simultaneously with the drain electrode and a second conductive layer formed simultaneously with the pixel electrode. The first conductive layer and the second conductive layer are electrically connected to each other via a through hole provided in the second insulating film. This contact hole is desirably provided for each pixel opening.

[0014]

However, if the width of the signal line is made sufficiently small in order to meet the demand for higher definition of the flat display device and improvement of the aperture ratio of the array substrate, contact holes in the signal line are formed. It is becoming impossible to fit the portion within the narrow width of the signal line. Therefore, it has become necessary to make the signal line wide only in the portion where the contact hole is formed.

The reason why the dimensions of the contact hole forming portion must be made somewhat large is as follows.

For example, when forming a contact hole in a second insulating film made of silicon nitride, it is necessary to obtain a large amount of side etching and to obtain a reliable contact between the first and second conductive layers. Therefore, the size of the contact hole must be relatively large. In addition, the contact hole forming portion of the first conductive layer needs to be larger than the size of the contact hole so that the contact hole does not protrude from the first conductive layer. The contact hole is protruding
If so, it may cause interlayer short-circuiting.

As described above, if the contact hole forming portion of the first conductive layer is provided wider than the other portion of the signal line and projects into the pixel opening, the area of the pixel opening portion is reduced by that much, and the array is reduced. The aperture ratio of the substrate and the flat panel display decreases.

The present invention has been made in view of the above-mentioned problems, and is intended to provide a matrix array substrate used for a flat panel display device and the like, in which a signal line has a redundant wiring structure.
An object of the present invention is to provide a matrix array substrate that does not cause a decrease in pixel aperture ratio.

[0019]

According to a first aspect of the present invention, there is provided a matrix array substrate comprising: a plurality of scanning lines arranged substantially in parallel on a substrate; a plurality of signal lines substantially orthogonal to the scanning lines; A plurality of pixel electrodes arranged, the signal line penetrating the first conductive layer, a second conductive layer overlaid on the first conductive layer via an interlayer insulating film, and the interlayer insulating film;
A contact hole for electrically connecting the first and second conductive layers to each other, in the matrix array substrate for a flat display device, the contact hole is disposed at an intersection of the scanning line and the signal line. It is characterized by being performed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Matrix array substrate 1 of an embodiment
0 will be described with reference to FIGS. FIG. 1 schematically shows a schematic configuration of a pixel portion of an array substrate. Also,
FIG. 2 shows the signal line 1 other than the contact hole forming portion 11.
FIG. 3 is a partial cross-sectional view showing the laminated structure of FIG.
FIG. 4 is a partial cross-sectional view showing a laminated structure of a contact hole forming portion 11 of FIG.

The array substrate 10 has a diagonal dimension of an image display area of 13.3 inches and is used for an XGA-TFT type normally white mode light transmission type liquid crystal display device.

On the glass substrate 5, 1024 × 3 signal lines 1 and 768 scanning lines 4 are arranged so as to be orthogonal to each other. The lower metal wiring pattern including the scanning lines 4 is formed directly on a glass substrate by using a low-resistance material such as aluminum, an aluminum alloy, or molybdenum-tungsten (Mo-W). The lower metal wiring pattern includes a silicon oxide film 61 and a silicon nitride film 62.
Is covered with a gate insulating film 6 made of a laminated film.

In each pixel opening defined by the signal line 1 and the scanning line 4, a TFT 2 as a switching element is arranged near the intersection of the signal line 1 and the scanning line 4. The TFT 2 is of an inverted stagger type having the extended portion 41 of the scanning line 4 as a gate electrode, and a portion covering the gate electrode 41 is provided with an amorphous silicon via a gate insulating film 6.
A semiconductor film 24 made of (a-Si: H) is disposed. On this semiconductor film, a channel protection film 2 is formed at a substantially central channel portion.
3 and a low-resistance semiconductor film made of phosphorus-doped amorphous silicon (n ⁺ a-Si: H) is stacked and arranged other than the channel portion. Further thereon, a source electrode 21 and a drain electrode 22 each of which is a three-layer film in which a layer of aluminum (Al) is laminated from above and below by a layer of molybdenum (Mo) are arranged. The upper metal wiring pattern including the source electrode 21 and the drain electrode 22 is entirely covered with the interlayer insulating film 7 made of a silicon nitride film.

On the interlayer insulating film 7, an IT
A pixel electrode 3 made of an O layer is provided, and is electrically connected to a source electrode 31 via a contact hole 35 penetrating through the interlayer insulating film 7. The pixel electrode 3 is, as shown in FIG.
The auxiliary portion (Cs) is formed by the extending portion 31 overlapped with the scanning line 4 farther from T2.

The signal line 1 is a low-resistance conductive layer (Mo / Al / Mo laminated metal film) 13 formed simultaneously with the drain electrode 22.
And an auxiliary conductive layer (ITO formed simultaneously with the pixel electrode 3)
A low-resistance conductive layer 13 and an auxiliary conductive layer 14 are electrically connected to each other via a contact hole 15 penetrating through the interlayer insulating film 7.

The width of the portion 12 of the signal line 1 other than the contact hole forming portion 11 is as small as 5 μm. On the other hand, the contact hole forming portion 11 of the signal line 1 is formed to be considerably wide. The diameter of the contact hole 15 alone is about 10 μm.
The contact hole 15 is formed to have a size larger than that of the contact hole 15 by a size that allows for the variation in etching for forming the contact hole 15 and the exposure position so that the contact hole 15 does not protrude.

This wide contact hole forming portion 11
Are arranged at the intersections of the signal lines 1 and the scanning lines 4 as shown in FIG. As shown in the figure, since the contact hole forming portion 11 is substantially circular, the portion where the signal line 1 protrudes from the original width (here, 5 μm) to the left and right sides is mostly a region on the scanning line 4. Can be stored in
Further, even if the pixel electrode protrudes into the pixel opening, it is located at a corner of the pixel opening, so that the margin between the pixel electrode and the auxiliary conductive layer (ITO layer) of the signal line 1 is hardly cut out. Can be taken.

On the other hand, if the contact hole forming portion 11 is disposed on the intersection with the scanning line 4 as described above, the area where the signal line 1 and the scanning line 4 overlap with each other becomes large. There is a problem that the electric capacitance formed between the scanning line 1 and the scanning line 4 increases, and the time constant at the time of drive control increases. However, an increase in the time constant can be sufficiently prevented by appropriately increasing the thickness of the low-resistance conductive layer 13 of the signal line 1 and the thickness of the scanning line 4 to lower the wiring resistance.

In the example shown in FIGS. 2 and 3, the low-resistance conductive layer 13 of the signal line and other upper metal wiring patterns
Amorphous silicon (aS
i: H) layer 16 and phosphorus-doped amorphous silicon (n ⁺ a) as a low-resistance semiconductor layer (ohmic contact layer).
-Si: H) is formed by being patterned together with the layer 17. Therefore, the signal line 1 is always stacked on the semiconductor layers 16 and 17, and an increase in electric capacity at the intersection with the scanning line 4 is suppressed.

Although not shown in the drawing, a counter substrate combined with the array substrate 10 is a lattice-shaped light-shielding film made of chrome or the like on a glass substrate, and red (R) and green (G) disposed therebetween. And blue (B) coloring patterns. This light-shielding film, when combined with the array substrate, shields the location of the TFT and the gap between the pixel electrode and the signal line 1 and the scanning line 4. That is, the light-shielding film is provided corresponding to the effective opening area of the array substrate. Therefore, the aperture ratio of the liquid crystal display device is determined solely by the effective area of the pixel aperture in the array substrate if the alignment accuracy between the array substrate and the counter substrate is the same.

According to the present embodiment, since the contact hole forming portion 11 of the signal line 1 is disposed at the intersection with the scanning line 4, the effective area of the pixel opening defined by the signal line 1, the scanning line 4 and the TFT2. Is hardly reduced by the contact hole forming portion 11.

FIG. 4 shows an array substrate 100 of a comparative example. In the comparative example, the contact hole forming portion 11 was provided at a portion other than the intersection with the scanning line 4, and the other portions were the same. In the array substrate of this comparative example, the contact hole forming portion 11 protrudes into the pixel opening. Therefore, a cutout 33 is provided in the pixel electrode 3 so that the pixel electrode 3 is not connected to the auxiliary conductive layer 13 of the signal line 1. According to the array substrate of this comparative example, the effective area of the pixel opening is reduced by about 0.5% as compared with the case where the signal line is not provided with the redundant structure and the contact hole forming portion is not provided.

Therefore, in the array substrate of the embodiment, the aperture ratio is about 0.5 in comparison with the comparative example in which the contact hole forming portion of the signal line is provided at a portion other than the intersection with the scanning line.
It can be improved by 5%.

[0034]

According to the matrix array substrate of the present invention, the aperture ratio can be improved, and a high display luminance can be attained when used in a display device.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a schematic configuration of a pixel portion on an array substrate according to an embodiment.

FIG. 2 is a partial cross-sectional view showing a stacked structure of signal lines other than a contact hole forming portion in the array substrate of the embodiment.

FIG. 3 is a partial cross-sectional view showing a laminated structure of a contact hole forming portion of a signal line in the array substrate of the embodiment.

FIG. 4 is a plan view schematically illustrating a schematic configuration of a pixel portion on a conventional array substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Signal line 11 Wide contact hole formation part in signal line 12 Equal width thin line part other than contact hole formation part in signal line 13 Low resistance conductive layer (Mo / Al / Mo) 14 Auxiliary conductive layer (ITO layer) 15 Contact hole in signal line 16 Low-resistance semiconductor layer (a-Si: H) patterned simultaneously with signal line 17 Low-resistance semiconductor layer (n ⁺ a-Si: H) 2 patterned simultaneously with signal line 2 TFT 21 Source electrode 22 Drain electrode 23 Channel protective film 24 Semiconductor layer 3 Pixel electrode 31 Extension portion for forming auxiliary capacitance of pixel electrode 35 Contact hole between pixel electrode and source electrode 4 Scanning line 41 Gate electrode 5 Glass substrate 6 Gate insulating film 7 Interlayer insulation film

Continued on the front page F term (reference) 2H092 GA17 GA25 GA29 JB24 JB33 NA07 NA12 5C094 AA07 BA03 BA43 CA19 DB04 EA04 EA07 HA08 5F033 GG04 HH38 JJ38 KK08 KK09 KK19 KK20 MM15 NN21 UU04 VV15 5F01 FF02 FF03 HJ01 HK03 HK04 HK21 HL03 HL04 HL11 NN02 NN12 NN24 NN41 NN46 NN72 NN73

Claims (6)

[Claims] A plurality of scanning lines arranged substantially in parallel on a substrate, a plurality of signal lines substantially orthogonal to the plurality of scanning lines, and a plurality of pixel electrodes arranged in a matrix; A first conductive layer, a second conductive layer superposed along the first conductive layer via an interlayer insulating film, and penetrating the interlayer insulating film to electrically connect the first and second conductive layers to each other A matrix array substrate for a flat panel display device, comprising: a contact hole formed at a crossing of the scanning line and the signal line. 2. A scanning line disposed on a substrate, a gate insulating film disposed thereon, a semiconductor film disposed thereon,
A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film; a signal line substantially orthogonal to the scan line; and a pixel electrode electrically connected to the source electrode; A first conductive layer derived from the drain electrode, a second conductive layer superposed along the first conductive layer via an interlayer insulating film, and a wire penetrating the interlayer insulating film; A contact hole for electrically connecting the two conductive layers to each other, wherein the contact hole is arranged at an intersection of the scanning line and the signal line. Matrix array substrate. 3. The matrix array substrate according to claim 1, wherein the first or second conductive layer is formed of the same material in the same step as the pixel electrode. 4. The matrix array substrate according to claim 1, wherein the width of the signal line is larger at a position where the contact hole is formed than at other positions. 5. The matrix array substrate according to claim 1, wherein said contact hole is provided for each pixel opening. 6. The pixel electrode is disposed at least with the interlayer insulating film interposed therebetween, and is made of the same material as the semiconductor film that matches the contour of the signal line in the intersection region between the scanning line and the signal line. 3. The matrix array substrate according to claim 2, wherein a semiconductor layer is interposed.