KR20020061353A - Method for forming contact hole for semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to form the contact hole necessary for the semiconductor device without deteriorating an electrical characteristic of the semiconductor device by etching an insulation film in a small etching selection ratio condition. CONSTITUTION: A gate electrode(20) and a source/drain region(32) are formed on a semiconductor substrate(10). A metal silicide film(34) is formed only on the source/drain region of a logic circuit region. The first interlayer insulation film(40) is formed on a surface of the results. A self-align contact pad(42) is formed between two gate electrodes adjacent to a cell array region. The second interlayer insulation film(50) is formed on the results. A photoresist pattern is formed on the second interlayer insulation film. The first and the second interlayer insulation film and the silicon nitride film(26) are etched by a MERIE(Magnetically Enhanced Reactive Ion Etching) method using a mixture gas of CHF3, CO and O2 as an etching gas. Then, the first, the second and the third contact hole(H1,H2,H3) are formed.

Description

Method for forming contact hole of semiconductor device {Method for forming contact hole for semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole for forming a highly integrated semiconductor device.

In general, semiconductor devices are mainly composed of metal oxide semiconductor (MOS) transistors. The electrical characteristics of MOS transistors are closely related to those of semiconductor devices. Accordingly, in order to improve characteristics such as switching speed of the MOS transistor, a salicide technique that selectively forms a metal silicide film having a low specific resistance in the gate electrode and the source / drain region is widely used.

Recently, as the integration of semiconductor devices increases, a complex chip such as merged DRAM and logic (MDL), in which memory and logic such as DRAM are merged into one chip, has been developed. As described above, in a semiconductor device having both a function of a semiconductor memory element and a function of a logic element, a metal silicide film is selectively formed on the gate electrode of the memory cell transistor, and the gate electrode and the source / drain regions of the transistor of the logic circuit In all, a technique for forming a metal silicide film is required.

In addition, as the degree of integration of semiconductor devices increases, the process for manufacturing semiconductor devices becomes increasingly complex, and therefore, development of highly difficult unit process technology is required. In particular, in the etching process of forming a narrow and deep contact hole having a large aspect ratio, in order to form a contact stud for forming a wiring which must be formed through multiple layers of various kinds of films. By controlling the selectivity for the various films to be etched, it is urgent to develop a technique to prevent the contact holes from being open or over-etched more than necessary.

In the conventional semiconductor device, since the insulating film is mainly composed of an oxide-based material, the type of insulating film to be etched to form the contact stud for wiring formation is mainly limited to the oxide film, so that the contact hole formation process required for forming the contact stud is required. Etching gases such as CF ₄ , CHF ₃ , and CH ₂ F ₂ have been used. However, in recent years, as the degree of integration of semiconductor devices increases, design rules have been reduced, and self-aligned contact (SAC) forming technology has been introduced. Accordingly, in order to form self-aligned contact holes for forming SAC, The lower conductive layer, for example, the gate electrode layer, is covered with a silicon nitride film having a relatively thick thickness and is used as an etching stopper to perform an etching process under conditions having a high selectivity to the oxide film.

However, in the case of the MDL element, it is necessary to form a contact stud exposing the gate electrode layer in order to connect the upper metal wiring layer to the gate electrode layer in the peripheral circuit region. In this case, in the case of the device employing the SAC technology, both the oxide film constituting the interlayer insulating film and the thick silicon nitride film covering the gate electrode layer must be etched to form a contact stud on the gate electrode layer. In this case, when the contact hole is formed by a conventional contact hole forming method, a large amount of CN-based by-products are generated during etching of the silicon nitride film, so that the silicon nitride film cannot be removed efficiently, and the etching is stopped in the silicon nitride film covering the gate electrode layer. The gate electrode layer cannot be exposed.

In order to prevent this, a method of increasing an etching target may be considered. However, the contact hole forming process for forming the contact stud is typically not only a gate electrode layer in a peripheral circuit region, but also a contact pad self-aligned by two adjacent gate electrodes in a cell array region, and a source in a logic circuit region. The same is true for the / drain region. Therefore, when the etching process is performed by increasing the etching target in the contact hole forming process for forming the contact stud, it is possible to expose the gate electrode layer in the peripheral circuit region, but in the logic circuit region, the metal silicide film of the source / drain region is over. Overetching deteriorates the resistivity and leakage current characteristics.

Disclosure of Invention An object of the present invention is to etch an insulating film in which an oxide film and a silicon nitride film are mixed in a condition that the etching selectivity between the oxide film and the nitride film is small, thereby enabling the formation of a contact required for the semiconductor device without deteriorating the electrical characteristics of the semiconductor device. It is to provide a method for forming a contact hole.

1 to 8 are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate, 20 gate electrode, 22 doped polysilicon film, 24 metal silicide film, 26 silicon nitride film, 32 source / drain region, 34 metal silicide film, 40 first interlayer insulating film, 42 : Self-aligned contact pad, 50: second interlayer insulating film, 60: photoresist pattern, 62a: first hole, 62b: second hole, 62c: third hole, 64: mixed gas, 66a, 66b, 66c: contact stud , 70: metal wiring layer.

In order to achieve the above object, in the contact hole forming method of a semiconductor device according to an aspect of the present invention, a conductive layer is formed on a semiconductor substrate. A silicon nitride film is formed to cover the conductive layer. An oxide film is formed on the silicon nitride film. A photoresist pattern is formed on the oxide film to partially expose an upper surface of the oxide film. Using the photoresist pattern as an etching mask, the oxide layer and the silicon nitride layer are etched to expose the conductive layer by a magnetically enhanced reactive ion etching (MERIE) method using a mixed gas of CHF ₃ , CO, and O ₂ as an etching gas. Contact holes are formed.

The flow rate of O ₂ in the mixed gas is 3 to 10% by volume based on the total flow rate of the mixed gas.

The said etching step is performed in the temperature range of -10-40 degreeC.

The conductive layer may form a gate electrode having a polyside structure in which a doped polysilicon layer and a metal silicide layer are stacked. At this time, in the etching step, a contact hole for exposing the metal silicide layer is formed.

In the method for forming a contact hole in a semiconductor device according to another aspect of the present invention, a plurality of gate electrodes and source / drain regions completely covered with a silicon nitride film are respectively formed in a logic circuit region, a peripheral circuit region, and a cell array region on a semiconductor substrate. . A first metal silicide film is formed in the source / drain regions of the logic circuit region. An interlayer insulating film is formed on the entire surface of the product to cover the silicon nitride film and the first metal silicide film. A photoresist pattern is formed on the interlayer insulating layer to partially expose an upper surface of the interlayer insulating layer. The interlayer insulating film and the silicon nitride film are etched by the MERIE method using the photoresist pattern as an etch mask and a mixed gas of CHF ₃ , CO, and O ₂ as an etch gas to form a first metal silicide film in the logic circuit region. And a first contact hole and a second contact hole exposing the gate electrode of the peripheral circuit region, respectively.

According to the present invention, even if the plurality of films in which the oxide film and the silicon nitride film are mixed are etched in a single etching process, the etching selectivity of the oxide film to the nitride film becomes 2: 1 or less, so that the etching is not stopped. Since the etching process is performed on the conditions which provide the excellent etching selectivity with respect to various etching stoppers, such as a film | membrane and a metal silicide film | membrane, it can be advantageously applied in the contact hole formation process which uses various kinds of base films as an etching stopper.

Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The following exemplary embodiments can be modified in many different forms, and the scope of the present invention is not limited to the following exemplary embodiments. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the accompanying drawings, the size or thickness of the films or regions is exaggerated for clarity. In addition, when a film is described as "on" another film or substrate, the film may be directly on top of the other film, and a third other film may be interposed therebetween.

1 to 8 are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to a preferred embodiment of the present invention in a process sequence.

Referring to FIG. 1, a plurality of gate electrodes 20 and source / drain regions 32 are formed in a logic circuit region, a peripheral circuit region, and a cell array region on a semiconductor substrate 10, respectively. The gate electrode 20 is formed so that the top and sidewalls thereof are completely covered by the silicon nitride film 26. The gate electrode 20 is formed to have a polyside structure in which a doped polysilicon layer 22 and a metal silicide layer 24, for example, a tungsten silicide layer are stacked.

Referring to FIG. 2, the metal silicide layer 34, for example, a cobalt silicide layer, is formed only in the source / drain region 32 of the logic circuit region. The metal silicide layer 34 is formed only in the source / drain region 32 of the logic circuit region as follows. In other words, when the degree of integration of the MDL composite chip is increased, the line width and the contact size of the gate electrode are reduced, thereby increasing the contact resistance and the sheet resistance. As a result, not only the semiconductor device may not perform high-speed operation but also an increase in signal delay and power consumption due to RC time delay may cause a decrease in reliability. In order to prevent this, the metal silicide layer 34 is formed. However, in the case of forming the silicide film over the entire region of the semiconductor device, the junction solution is formed in the cell array region, particularly in the active region in which the storage node is formed, due to the silicide film formed in the active region of the DRAM cell array region. Leakage increases, resulting in a poor storage capacity of the capacitor and a failure in the refresh characteristics of the DRAM cell. Therefore, in order to prevent this, the metal silicide layer 34 is formed only in the source / drain region 32 of the logic circuit region.

Referring to FIG. 3, the first interlayer insulating layer 40 covers the silicon nitride layer 26 and the first metal silicide layer 34 on the entire surface of the resultant product in which the metal silicide layer 34 is formed in the logic circuit region. To form. The first interlayer insulating film 40 may be formed of, for example, a high density plasma (HDP) oxide film.

Thereafter, a self-aligned contact pad 42 is formed between two adjacent gate electrodes 20 in the cell array region using a conventional self-align contact (SAC) forming process.

Referring to FIG. 4, a second interlayer insulating film 50 is formed on the entire surface of the resultant self-aligned contact pad 42. The second interlayer insulating film 50 may be formed of a tetraethylorthosilicate (P-TEOS) film.

Referring to FIG. 5, a photoresist pattern 60 is formed on the second interlayer insulating film 50 to partially expose an upper surface of the second interlayer insulating film 50. The photoresist pattern 60 may be formed on top of the thin metal silicide layer 34 formed on the logic circuit region, on the gate electrode 20 formed on the peripheral circuit region, and on the self-aligned contact pad 42 formed on the cell array region. Is formed to have a first hole 62a, a second hole 62b, and a third hole 62c exposing the top surface of the second interlayer insulating film.

Referring to FIG. 6, the photoresist pattern 60 is used as an etch mask and the magnetically enhanced reactive ion etching (MERIE) method uses a mixed gas 64 of CHF ₃ , CO, and O ₂ as an etching gas. The second interlayer insulating film 50, the first interlayer insulating film 40, and the silicon nitride film 26 are etched. As the mixed gas 64, for example, 45 sccm of CHF ₃ , 150 sccm of CO and 6 sccm of O ₂ can be supplied. The flow rate of O ₂ in the mixed gas 64 is 3 to 10% by volume based on the total flow rate of the mixed gas. In addition, the MERIE etching process using the said mixed gas 64 is performed in the temperature range of -10-40 degreeC. When the MERIE etching process is performed under the conditions described above, the etching selectivity ratio of the oxide film to the nitride film becomes 2: 1 or less, so that the second interlayer insulating film 50, the first interlayer insulating film 40, and the silicon nitride film 26 are one step. Even if the process is etched, there is no problem that etching is stopped in the middle. In addition, the MERIE method performed under the above conditions using the mixed gas 64 provides an excellent etching selectivity with respect to the polysilicon film, the metal silicide film and the like. Therefore, it can be advantageously applied in the process of forming a contact hole required for forming an element using various kinds of underlayers as an etching stopper.

In this embodiment, the etching process using the mixed gas 64 is performed by the metal silicide film 34 of the logic circuit region, the metal silicide film 24 of the peripheral circuit region, and the self-aligned contact pads of the cell array region. By providing an excellent etching selectivity with respect to 42, there is no fear that the metal silicide film 34 will be damaged by overetching. Therefore, as a result of the etching process according to the above conditions, the first contact hole H1 exposing the metal silicide film 34 formed in the source / drain region 32 of the logic circuit region and the gate electrode of the peripheral circuit region. A second contact hole H2 exposing the metal silicide layer 24 constituting the 20 and a third contact hole H3 exposing the self-aligned contact pad 42 in the cell array region. Can be.

Referring to FIG. 7, the contact studs 66a, 66b, and 66c may be filled by filling a conductive material such as tungsten in the first contact hole H1, the second contact hole H2, and the third contact hole H3. Form.

Referring to FIG. 8, a conductive film, for example, a tungsten film, is formed on the contact studs 66a, 66b, and 66c to form a metal wiring layer 70.

According to the present invention, a mixed gas of CHF ₃ , CO and O ₂ is used as an etching gas to etch a plurality of films in which an oxide film and a silicon nitride film are mixed in a single etching process to form a contact hole having a large aspect ratio. Use the MERIE method. Accordingly, the etching selectivity ratio of the oxide film to the nitride film is 2: 1 or less, so that the etching is not stopped even when the plurality of films in which the oxide film and the silicon nitride film are mixed are etched in a single etching process. In addition, in the case where a plurality of films in which an oxide film and a silicon nitride film are mixed are present and an oxide film is formed at the same time, etching is performed at the same time to form the necessary contact holes in each area. There is no problem such that the etching is stopped before the layer is completely exposed. In addition, the MERIE method using the mixed gas provides excellent etching selectivity for various etching stoppers such as polysilicon film, metal silicide film and the like. Therefore, it can be advantageously applied in the process of forming a contact hole using various kinds of underlayers as etching stoppers, for example, in the manufacturing process of MDL elements.

The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

Claims (10)

Forming a conductive layer on the semiconductor substrate, Forming a silicon nitride film covering the conductive layer; Forming an oxide film on the silicon nitride film; Forming a photoresist pattern partially exposing the top surface of the oxide film on the oxide film; Using the photoresist pattern as an etching mask, the oxide layer and the silicon nitride layer are etched to expose the conductive layer by a magnetically enhanced reactive ion etching (MERIE) method using a mixed gas of CHF ₃ , CO, and O ₂ as an etching gas. Forming a contact hole for forming a contact hole. The method of claim 1, wherein the flow rate of O ₂ in the mixed gas is 3 to 10% by volume based on the total flow rate of the mixed gas. The method of claim 1, wherein the etching step is performed within a temperature range of -10 to 40 ℃. The method of claim 1, wherein the conductive layer is a gate electrode. The method of claim 4, wherein The gate electrode has a polyside structure in which a doped polysilicon layer and a metal silicide layer are stacked. And forming a contact hole exposing the metal silicide layer in the etching step. Forming a plurality of gate electrodes and source / drain regions completely covered with a silicon nitride film, respectively, in the logic circuit region, the peripheral circuit region, and the cell array region on the semiconductor substrate; Forming a first metal silicide film in a source / drain region of the logic circuit region; Forming an interlayer insulating film over the entire surface of the product to cover the silicon nitride film and the first metal silicide film; Forming a photoresist pattern on the interlayer insulating film to partially expose an upper surface of the interlayer insulating film; The interlayer insulating film and the silicon nitride film are etched by the MERIE method using the photoresist pattern as an etch mask and a mixed gas of CHF ₃ , CO, and O ₂ as an etch gas to form a first metal silicide film in the logic circuit region. And forming a first contact hole and a second contact hole exposing the gate electrode of the peripheral circuit region, respectively. The method of claim 6, wherein the flow rate of O ₂ in the mixed gas is 3 to 10% by volume based on the total flow rate of the mixed gas. The method of claim 6, wherein the etching is performed in a temperature range of −10 to 40 ° C. 8. The method of claim 5, wherein the gate electrode has a polyside structure in which a doped polysilicon layer and a second metal silicide layer are stacked. And forming said first contact hole in said etching step to expose said second metal silicide layer. 7. The method of claim 6, wherein the first metal silicide layer is a cobalt silicide layer.