JPH11251544A - Manufacture of semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor storage device in which a contact-not- open state due to the difference of etching rates of an insulating layer is prevented. SOLUTION: A first insulating layer 106 formed on a semiconductor substrate 100 having cell array regions and a peripheral circuit region is etched, and pad contact holes are formed. The pad contact holes are filled with conductive films, and conductive film pads 110b are formed. A second insulating layer 112a, having an etching selection ratio to a first insulating layer material is formed on the first insulating layer 106 containing the conductive film pads 110b. Bit lines 114' are formed on the second insulating layer 112a in cell array regions. The second insulating layer 112a in the remaining regions, in which the lower parts of the bit lines 114' are eliminated, is eliminated by a whole surface etch back process. A third insulating layer 118 and a fourth insulating layer 120 are formed in order on the whole surface of the semiconductor substrate 100 containing the bit lines 114', and storage node contact holes 122 are formed in the cell array regions by etching the layers 118, 120. The fourth, third and first insulating layers 120, 118, 106 are etched, and metal contact holes are formed in the peripheral circuit region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to an etching rate of an insulating layer.
The present invention relates to a method of manufacturing a semiconductor memory device, which improves the problem of contact formation due to the difference of e).

[0002]

2. Description of the Related Art FIG. 1 shows a layout of a semiconductor memory device for explaining a conventional manufacturing method and a manufacturing method of the present invention.
yout). Referring to FIG. 1, a layout of a cell array region of a semiconductor memory device is as follows.
A plurality of gate poly GP1 to GP
4 and a plurality of bit lines BL1
~ BL3. Bit line contact (bit line c
ontact) BT and stridinodo contact (storage no)
de contact) ST.

FIG. 2 is a cross-sectional view of a conventional semiconductor memory device cut along the line XX 'of FIG. Referring to FIG. 2, in a conventional method for forming a stridino contact in a cell array region of a semiconductor memory device, an element isolation film 12 is formed on a semiconductor substrate 10 and a first isolation layer 12 is formed on the semiconductor substrate 10 including the element isolation film 12. An insulating layer 14 is formed.

A poly pad 16 is formed so as to be electrically connected to the semiconductor substrate 10 between the device isolation films 12 with the first insulating layer 14 left. The first insulating layer 14 and the poly pad 16 are formed to have a planarized upper surface. On the poly pad 16 and the first insulating layer 14, a second insulating layer 18, which is a bit line lower insulating layer, is formed.

The third and fourth insulating layers 22 and 24 are sequentially formed on the second insulating layer 18 including the bit line 20 formed on the second insulating layer 18 and the bit line 20. The bit line 20 includes, for example, a polysilicon film 20 a and a tungsten silicide (tungsten silicide) 20.
b and anti-reflective coating
A multilayer film 20c is sequentially laminated.

[0008] The second to fourth insulating layers 18, 22, and 24 are etched to form stridino contact holes 26 so that a portion of the polypad 16 is exposed.

[0007] The first and third insulating layers 14, 22 and
The fourth insulating layer 24 is generally made of BPSG (Boro Phospho Sil
icate Glass) membrane is used.

However, the second insulating layer 18 has a relatively low erosion probability than the BPSG film.
de) A membrane is used.

HTO is used as the bit line lower insulating layer 18.
The reason for using the membrane is as follows.

When electrically connecting the gate electrode of the peripheral circuit region to the bit line, the contact resistance is maintained constant unless the bit line poly and the gate electrode poly are directly contacted. Can not do.

Since the gate electrode has a double structure of poly and tungsten silicide, a step of removing tungsten silicide from the contact portion is required.

The tungsten silicide removal process is generally performed for tungsten silicide etching.
This is accomplished using When the tungsten silicide removal process is performed, the HTO layer serves as an etch prevention layer for the BPSG layer thereunder.

However, when a stridino contact hole 26 is formed by using an HTO film as the bit line lower insulating layer 18, as shown by reference numeral 28,
A slop is generated due to a difference in erosion probability between different insulating layers. The HTO film has a relatively slow erosion probability.

[0014] Due to the etching inclination, the area of the contact region is reduced, thereby increasing the contact resistance. Also, contact knot open (contact no
t open) It gives the possibility of phenomenon.

FIG. 3 is a sectional view showing a metal contact of a conventional semiconductor memory device. Referring to FIG. 3, a conventional method for forming a metal contact in a peripheral circuit region of a semiconductor memory device includes forming a transistor 30 on a semiconductor substrate 10,
First to fourth insulating layers 14, 18, 22, and 24 are sequentially formed on the semiconductor substrate 10 including the transistor 30.

The first to fourth insulating layers 14, 18, 22,
24, the semiconductor substrate 10 between the transistors 30
The metal contact hole 32 is formed so that a part of the metal contact hole is exposed.

As in the case of the stridino contact hole 26, the metal contact hole 32 has a sharp inclination as shown by reference numeral 34 at the interface between the insulating layers having different etching rates. This may cause a failure when a subsequent barrier layer is formed and a conductive layer such as tungsten is filled.

[0018] Also, a steep incline poses a danger of contact not opening.

In order to prevent the contact not-open, the critical dimension of the contact must be increased. However, when the line width of the contact is increased, a problem arises that the space gene a between the metal contact hole 32 and the transistors 30 on both sides thereof is weakened.

[0020]

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and it has been found that when a stridin contact hole and a metal contact hole are formed, a failure such as a contact not-open phenomenon occurs. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can prevent the occurrence of a misalignment and can improve a margin for misalignment between a metal contact and a gate electrode.

It is another object of the present invention to provide a method of manufacturing a semiconductor device which can unify an insulating layer at a portion where a stridino contact hole and a metal contact hole are formed.

[0022]

In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention comprises the steps of forming a first insulating layer on a semiconductor substrate, and etching the first insulating layer. Forming a pad contact hole, filling the pad contact hole with a conductive film to form a conductive film pad, and forming a second insulating layer on the first insulating layer including the conductive film pad. Forming a material having an etch selectivity with the insulating layer, forming a bit line on the second insulating layer, removing the second insulating layer on both sides of the bit line, and a semiconductor substrate including the bit line Forming a third insulating layer and a fourth insulating layer on the entire surface using a material having the same etching rate as the first insulating layer;
Forming a stridino contact hole so as to expose a portion of the conductive layer pad by etching the insulating layer;

In a preferred embodiment of the method, the first
The insulating layer, the third insulating layer, and the fourth insulating layer material are B
PSG.

In a preferred embodiment of the method, the second
The insulating layer material is HTO.

In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention comprises the steps of forming a first insulating layer on a semiconductor substrate, and etching the first insulating layer to form a pad contact hole. Forming a conductive film pad by filling a pad contact hole with a conductive film, and forming a second insulating layer on the first insulating layer including the conductive film pad. Forming a bit line on the second insulating layer, patterning a multi-layered film in which a conductive layer and an anti-reflection layer are sequentially formed, and forming the bit line on both sides of the bit line. Removing the second insulating layer by etching back the entire surface of the semiconductor substrate, and removing the anti-reflection layer by the etch back process to have the same etching rate as the first insulating layer over the entire surface of the semiconductor substrate including the bit line. First to substance Comprising the steps of gradually forming the insulating layer and the fourth insulating layer, the step of the fourth and third insulating layer by etching a part of the conductive film pads to form a string-di throat contact hole to expose.

In a preferred embodiment of the method, the first
The insulating layer, the third insulating layer, and the fourth insulating layer material are B
PSG.

In a preferred embodiment of the method, the second
The insulating layer material is HTO.

In a preferred embodiment of the method, the removal of the anti-reflection layer compensates for the step of the bit line due to the etching of the second insulating layer.

In order to achieve the above object, a method of manufacturing a semiconductor memory device according to the present invention forms an element isolation film by defining an active region and a specific active region on a semiconductor substrate having a cell array region and a peripheral circuit region. Forming a transistor having a gate electrode in the active region of the cell array region; and forming a first transistor on the entire surface of the semiconductor substrate including the transistor.
Forming an insulating layer; etching a first insulating layer in a cell array region to form a pad contact hole;
Forming a conductive film pad by filling the pad contact hole with a conductive film, and forming a second insulating layer on the first insulating layer including the conductive film pad, the material having an etch selectivity with the first insulating layer. Forming a bit line on the second insulating layer in the cell array region, patterning and forming a multi-layered film in which a conductive layer and an anti-reflection layer are sequentially formed; Removing the second insulating layer in the peripheral circuit region by an overall etch-back process;
Removing the anti-reflection layer by an etch-back process and gradually forming a third insulating layer and a fourth insulating layer on the entire surface of the semiconductor substrate including the bit line using a material having the same etching rate as the first insulating layer; Etching the fourth and third insulating layers to form stridino contact holes so as to expose a portion of the conductive film pad; and etching the fourth, third, and first insulating layers to form a peripheral region. Forming a metal contact hole such that a portion of the semiconductor substrate is exposed between the gate electrodes in the circuit region.

In a preferred embodiment of the method, the first
The insulating layer, the third insulating layer, and the fourth insulating layer are formed of materials having the same etching rate.

In a preferred embodiment of the method, the first
The insulating layer, the third insulating layer, and the fourth insulating layer material are B
PSG.

In a preferred embodiment of the method, the second
The insulating layer material is HTO.

In a preferred embodiment of the method, the removal of the anti-reflection layer compensates for the bit line step due to the etching of the second insulating layer.

(Operation) According to the present invention, the method of manufacturing a semiconductor device is such that a single insulating layer is formed at a portion where a stridinodo contact hole and a metal contact hole are formed, so that the contact knot is reduced by the etching rate of another insulating layer. And improves the misalignment margin between the metal contact and the gate electrode.

[0035]

Referring to FIGS. 4 and 8, a method of manufacturing a novel semiconductor memory device according to an embodiment of the present invention includes a semiconductor substrate 1 having a cell array region and a peripheral circuit region.
The pad contact hole is formed by etching the first insulating layer 106 formed on the substrate. A pad contact hole is filled with a conductive film to form a conductive film pad 110b, and a first conductive film pad 110b is formed on the first insulating layer 106 including the conductive film pad 110b.
A second insulating layer 112 having an etch selectivity with the insulating layer material is formed. A bit line 114 is formed on the second insulating layer 112 in the cell array region. The second insulating layer 112 in a region other than the lower portion of the bit line 114 is removed by an etch back process. A third insulating layer 118 and a fourth insulating layer 120 are formed on the entire surface of the semiconductor substrate 100 including the bit line 114 ′.
Is gradually formed, and this is etched to form a stridino contact hole 122 in the cell array region. The fourth and third insulating layers 120 and 118 and the first insulating layer 106 are etched to form metal contact holes 126 in the peripheral circuit region. According to the method of manufacturing the semiconductor memory device, the types of the insulating layers in the bit line contact, the stridino contact, and the metal contact forming region are unified, so that the insulating layers having different etching rates from each other can be formed. It is possible to prevent the contact not-open phenomenon and the failure of filling the conductive film, and therefore, it is possible to reduce the size of the contact,
The misalignment margin between the metal contact and the gate electrode can be improved. Further, the step of the metal contact in the peripheral circuit region can be reduced.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.

5 to 8, components having the same functions as those of the semiconductor memory device shown in FIG. 4 are denoted by the same reference numerals.

FIG. 4 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention, taken along line XX 'of FIG.

Referring to FIG. 4, a method for forming a stridinodo contact according to an embodiment of the present invention includes the steps of:
An element isolation film 102 is formed thereon, and a first insulating layer 106 is formed on the semiconductor substrate 100 including the element isolation film 102.

The first insulating layer 106 is opened, and the element isolation film 10 is formed.
A conductive film pad 110b is formed of a polysilicon film or the like so as to be electrically connected to the semiconductor substrate 100 between the two.

Element isolation film 102 and conductive film pad 110b
Are formed to be partially overlapped to increase a margin for forming a pad contact hole.

First insulating layer 106 and conductive pad 110b
Has a planarized top surface.

A second insulating layer 112a, which is a bit line lower insulating layer 112a, is locally formed on the first insulating layer 106, and a bit line 114 'is formed on the second insulating layer 112a.

The bit line 114 'is formed of, for example, a polysilicon film 114a and a tungsten silicide film 114b.
Is a multilayer film sequentially laminated.

A third insulating layer 118 and a fourth insulating layer 120 are gradually formed on the entire surface of the semiconductor substrate 100 including the bit line 114 ′.

The first insulating layer 106 and the third insulating layer 118,
The fourth insulating layer 120 is BPSG used as a general interlayer insulating film, and the second insulating layer 112a is a BPSG.
An HTO film having an etching rate relatively lower than that of the SG film.

Fourth insulating layer 120 on poly pad 110b
Then, the third insulating layer 118 is etched to form a stridino contact hole 122.

Since the stridino contact hole 122 is formed by etching the fourth and third insulating layers 120 and 118, that is, the BPSG single film, the entrance area of the stridinodo contact hole 122 is compared with the uniform erosion probability. There is no problem that the area of the lower portion is rapidly reduced.

FIGS. 5 to 8 illustrate a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
9 to 12 are sectional views taken along line ZZ 'of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIGS. 5 and 9, in a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, an element isolation film 102 and a transistor 104a are formed on a semiconductor substrate 100 by a conventional method in a cell array region.

The transistor 104a includes, for example, a gate electrode layer in which a polysilicon film, a tungsten silicide film, and a silicon nitride film are sequentially stacked, and a gate electrode configured as a silicon nitride film spacer.

A first insulating layer 106 as an interlayer insulating film is formed on the entire surface of the semiconductor substrate 100 including the transistor 104a. The first insulating layer 106 is, for example, BPSG.

The first insulating layer 106 is etched and the element isolation film 1 is formed.
The pad contact holes 108a and 108b are formed so that the semiconductor substrate 100 is exposed during the period 02 and between the transistors 104a.

In particular, the pad contact hole 10 shown in FIG.
8b is a self-aligned contact
ct; SAC) method.

In FIGS. 6 and 10, the pad contact holes 108a and 108b are filled with a conductive film such as a polysilicon film to form conductive film pads 110a and 110b.

First insulating layer 106 and conductive film pad 110
a and 110b are CMP (Chemical Mechanical Polishin)
It is formed to have an upper surface planarized by a planarization etching process such as g).

The second insulating layer 112 is formed on the first insulating layer 106 including the conductive film pads 110a and 110b.
The first insulating layer 106 is formed of a material having an etch selectivity, for example, HTO.

Referring to FIGS. 7 and 11, the second insulating layer 112 is etched to expose the bit line contact hole 1 so that portions of the conductive film pads 110a and 110b are exposed.
13a and 113b are formed. A multilayer film is formed on the second insulating layer 112 including the bit line contact holes 113a and 113b, in which the bit line forming conductive layers 114a and 114b and the antireflection film 114c are sequentially stacked.

The conductive layers 114a and 114b are, for example, a multilayer film in which a polysilicon film and a tungsten silicide film are laminated, and the anti-reflection film 114c is made of PE-TEOS.
This is a multilayer film in which a film and a silicon nitride film (SiON) are stacked.

The conductive layers 114a and 114b and the antireflection film 114c are etched using a photoresist layer pattern (not shown) as a bit line forming mask. Then, bit line 1
14 are formed.

Finally, after removing the photoresist film pattern, an etch back process is performed on the entire surface to remove the bit line 114 under the bit line 114.
When the second insulating layers 112 on both sides are removed, FIGS.
As shown in FIG. 5, bit line contacts in the cell array region are formed.

The anti-reflection film 114 is formed in the entire surface etch-back process.
c is removed, and the step due to the bit line 114 'is maintained to be similar as compared with the conventional case.

FIGS. 13 to 16 are sectional views of a peripheral circuit region for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 13, in a method of manufacturing a semiconductor device according to an embodiment of the present invention, an element isolation film 102 and a transistor 104b are formed on a semiconductor substrate 100 in a peripheral circuit region by a conventional method.

The first insulating layer 106 is formed on the semiconductor substrate 100 including the transistor 104b, for example, by BPSG.

In FIG. 14, a material having an etching selectivity with respect to the first insulating layer 106, such as HTO, is formed on the first insulating layer 106.
Next, a second insulating layer 112 is formed.

Referring to FIG. 15, the second insulating layer 112 and the first insulating layer 106 are etched to expose the bit line contact holes 11 so that a portion of the semiconductor substrate 100 is exposed.
3c is formed.

A multilayer film is formed on the third insulating layer 112 including the bit line contact hole 113c, in which a conductive anti-reflection film for forming a bit line is sequentially laminated.

The bit line is formed by patterning the multilayer film using a photoresist film pattern (not shown) in the same manner as the method of forming the bit line in the cell array region.

Then, the entire surface is etched back to perform the second insulating layer 112 formed below the bit line 114.
When all of the second insulating layer 112 other than the region a is removed, a bit line contact in a peripheral circuit region is formed as shown in FIG.

An anti-reflection film 114 is formed in a whole etch back process.
c is removed, and the step due to the bit line 114 'is maintained to be similar as compared with the conventional case.

Second insulating layer 11 on both sides of bit line 114
By removing 2, when forming the stridino contact hole 122 to be performed in a subsequent process, a unitized insulating layer structure can be formed as shown in FIG. 4. The stridino contact hole 122 can be formed so as not to have a steep inclination.

FIG. 17 is a sectional view showing a metal contact of a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 17, in a method of forming a metal contact in a peripheral circuit region of a semiconductor memory device according to an embodiment of the present invention, a transistor 104c is formed on a semiconductor substrate 100, and a multilayer insulating layer is formed on the semiconductor substrate 100 including the transistor 104c. 106, 118 and 120 are gradually formed.

The metal contact holes 126 are formed by etching the multi-layer insulating layers 106, 118 and 120 so that a part of the semiconductor substrate 100 between the transistors 104c is exposed.

The spacer margin b of the metal contact hole 126 and the transistor 104c is relatively increased as compared with the prior art.

This is because the multilayer insulating layers 106, 118, 12
0 is a substance having the same etching rate, for example, all the nuclear insulating layers are B
This is possible because it is formed of PSG.

The spacer margin b of the metal contact hole 126 and the transistor 104c is relatively increased as compared with the prior art.

This is because the multilayer insulating layers 106, 118, 12
0 is possible because all the materials having the same etching rate, for example, the nuclear insulating layer are formed of BPSG.

Since the HTO film at the metal contact hole formation site has been removed by the above-described overall etch-back step, there is no danger such as contact not-open due to a difference in the etching rate of the insulating layer. It has a relatively lower etching rate than the film.

Further, by removing the HTO film, the step of the metal contact can be reduced to that extent.

The present invention relates to a method of manufacturing a semiconductor memory device for preventing a contact knot-open due to a difference in etching rate of an insulating layer. In summary, the embodiment is formed on a semiconductor substrate having a cell array region and a peripheral circuit region. The first insulating layer is etched to form pad contact holes. The pad contact hole is filled with a conductive film to form a conductive film pad, and a second insulating layer having an etching selectivity with the first insulating layer material is formed on the first insulating layer including the conductive film pad. A bit line is formed on the second insulating layer in the cell array region. The second insulating layer in the remaining area where the lower portion of the bit line is removed is removed by an overall etch-back process. A third insulating layer and a fourth insulating layer are sequentially formed on the entire surface of the semiconductor substrate including the bit lines, and are etched to form stridinide contact holes in the cell array region. The fourth insulating layer, the third insulating layer, and the first insulating layer are etched to form metal contact holes in the peripheral circuit region. According to the method of manufacturing the semiconductor memory device, the bit line contact, the stridino contact, and the contact knot formed by the insulating layers having different etching rates from each other by using a single type of insulating layer in the metal contact formation region. It is possible to prevent the opening phenomenon and the failure of filling the conductive film, thereby reducing the size of the contact, and improving the misalignment margin between the metal contact and the gate electrode. Also, the step of the metal contact in the peripheral circuit region can be reduced.

[0082]

As described above, according to the present invention, the types of insulating layers in the bit line contact, the stridinodo contact, and the metal contact forming region are unified, so that the contact knot-opening can be reduced by the insulating layers having different etching rates from each other. It is possible to prevent the filling of the conductive film, to reduce the size of the contact, and to improve the misalignment margin between the metal contact and the gate electrode. Also, there is an effect that the step of the metal contact in the peripheral circuit region can be reduced.

[Brief description of the drawings]

FIG. 1 is a layout of a semiconductor memory device for explaining a conventional manufacturing method and a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view of the conventional semiconductor memory device cut along the line XX ′ of FIG. 1;

FIG. 3 is a cross-sectional view illustrating a metal contact of a conventional semiconductor memory device.

FIG. 4 is a cross-sectional view of the semiconductor memory device according to the embodiment of the present invention, taken along line XX ′ of FIG. 1;

FIG. 5 is a cross-sectional view taken along a line YY ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along line YY ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line YY ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along line YY ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along a line ZZ ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along line ZZ ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along a line ZZ ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view taken along line ZZ ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 13 is a sectional view of a peripheral circuit region for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 14 is a sectional view of a peripheral circuit region for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 15 is a sectional view of a peripheral circuit region for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 16 is a sectional view of a peripheral circuit region for describing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

FIG. 17 is a sectional view showing a metal contact of a semiconductor memory device according to an embodiment of the present invention.

[Explanation of symbols]

 GP1-GP4 gate gate BL1-BL3 bit line BT bit line contact ST storage node contact 10, 100 semiconductor substrate 12, 102 element isolation film 14, 106 first insulating layer 16 poly pad 18, 112 Second insulating film 20, 114 Bit line 22, 118 Third insulating layer 24, 120 Fourth insulating layer 26, 122 Stridinod contact hole 30, 104 Transistor 32, 126 Metal contact hole 108 Pad Contact hole 110: conductive film pad 113: bit line contact hole

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Chun, Wang-Yaul Republic of Korea, Kyun-Gide, Sung-Nam-shi, Bundang-Kh, Yatop-Dong, 265, Maeva Town, Keong Young Villa 916-202 (72) Inventor No, Jung-Yong Korea, Kunguido, Incheon-si, Namdongkuk, Kangseok-dong, 156-5, Kungin Villa, 208, 227/5

Claims (12)

[Claims] Forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a pad contact hole, and filling the pad contact hole as a conductive film to form a conductive pad. Forming a second insulating layer on the first insulating layer including the conductive layer pad, and forming the second insulating layer on a material having an etch selectivity with the first insulating layer; Forming a bit line on the layer, removing the second insulating layer on both sides of the bit line, and using a material having the same etching rate as the first insulating layer over the entire surface of the semiconductor substrate including the bit line. Forming a third insulating layer and a fourth insulating layer, and etching the fourth and third insulating layers to form a stridino contact hole so that a portion of the conductive pad is not exposed. Including Method of manufacturing a conductor memory device. 2. The method of claim 1, wherein the first and third insulating layers and the fourth insulating layer are BPSG. 3. The method of claim 1, wherein the second insulating layer material is HTO. Forming a first insulating layer on the semiconductor substrate, etching the first insulating layer to form a pad contact hole, and filling the pad contact hole with a conductive film. Forming a pad, forming a second insulating layer on the first insulating layer including the conductive layer pad, using a material having an etch selectivity with the first insulating layer; (B) forming a bit line on the insulating layer by patterning and forming a multilayer film in which a conductive layer and an anti-reflection layer are sequentially formed; and etching back the second insulating layer on both sides of the bit line. Removing the anti-reflective layer in the etch-back process, and forming a third insulating layer and a third insulating material on the entire surface of the semiconductor substrate including the bit line, having the same etching rate as the first insulating layer. 4 insulating layers A method of manufacturing a semiconductor memory device, the method including: gradually forming; and forming a stridinide contact hole such that a portion of a conductive film pad is exposed by etching the fourth and third insulating layers. 5. The method as claimed in claim 4, wherein the first and third insulating layers and the fourth insulating layer are BPSG. 6. The method according to claim 4, wherein the second insulating layer material is HTO. 7. The method according to claim 4, wherein removing the anti-reflection layer compensates for a step of a bit line due to etching of a second insulating layer. 8. A step of defining an active region and a specific active region on a semiconductor substrate having a cell array region and a peripheral circuit region to form an element isolation film, and forming a transistor having a gate electrode in the active region of the cell array region. Forming a first insulating layer on the entire surface of the semiconductor substrate including the transistor; etching the first insulating layer in the cell array region to form a pad contact hole; Forming a conductive film pad by filling as a film, and forming a second insulating layer on the first insulating layer including the conductive film pad, the second insulating layer being formed of a material having an etch selectivity with the first insulating layer. Forming a bit line on the second insulating layer in the cell array region, and patterning a multilayer film in which a conductive layer and an anti-reflection layer are sequentially formed. Forming, removing the second insulating layer on both sides of the bit line and the peripheral circuit region by an entire etch-back process, removing the anti-reflection layer in the etch-back process, and entire surface of the semiconductor substrate including the bit line. Forming a third insulating layer and a fourth insulating layer using a material having the same etching rate as that of the first insulating layer; and etching the fourth and third insulating layers to form a part of a conductive film pad. Forming a stridino contact hole so as to be exposed; and etching the fourth, third and first insulating layers to expose a portion of the semiconductor substrate between gate electrodes in a peripheral circuit region. Forming a metal contact hole as described above. 9. The method of claim 8, wherein the first, third, and fourth insulating layers are formed of materials having the same etching rate. 10. The method of claim 8, wherein the first and third insulating layers and the fourth insulating layer are BPSG. 11. The method of claim 8, wherein the second insulating layer material is HTO. 12. The method of claim 8, wherein removing the anti-reflection layer compensates for a bit line step caused by etching the second insulating layer.