408338 A7 __B7__ 五、發明說明（ί ) 發明領域： 本發明有關於一種製造半導體記憶體裝置之方法，更 明確而言，有關於一種製造半導體記憶體裝置之方法，其 乃解決肇因於絕緣層之不同的蝕刻率而產生的接觸形成之 問題。 發明背景： 第一圖係說明根據先前技藝和本發明之製造半導體記 憶體裝置之方法的佈局圖。 參照第一圖，半導體記憶裝置之單元陣列區域之佈局 係包括複數個閘多晶體GP1-GP4以及複數條位元線BL1- BL3。再者，此佈局顯示位元線接觸bt以及儲存節點接觸 ST - 第二圖係沿第一圖所示之線χ_χ’所取之根據先前技藝 之半導體記憶體裝置之截面圖。 參照第二圖，在先前技藝半導體記憶體裝置中製造單 元陣列區域的儲存節點接觸之方法係包括步驟有：在半導 體基板10上製造裝置隔離層12，以及在包括裝置隔離層 12之半導體基板1〇上製造第一絕緣層η。複數個多晶體 墊係形成以藉由貫穿該第一絕緣層14而在裝置隔離層12 之間電氣連接至半導體基板10»第一絕緣層Μ以及多晶 體墊16係形成爲具有平坦的上表面。第二絕緣層18係作 爲下絕緣層而形成於多晶體墊16以及第一絕緣層14上。 第三和第四絕緣層22、24係依序形成於包括位元線20之 第二絕緣層18上。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） (請先閱讀背面之沒意事項再填寫本頁) 乂--------1 -δϋί-------線- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 408338 a? __^Β7 五、發明說明（少） 上述位元線20係爲其中有多晶矽層20a、矽化鎢層 20b以及抗反射塗層20c依序形成的多層結構。第二、第三 和第四絕緣層18、22、24係經蝕刻以使該多晶體墊16之 部份曝露，從而形成儲存節點接觸孔26 ^第一、第三和第 四絕緣層14、22、24係分別包括一BPSG(硼磷矽酸塩玻璃) 層。 然而，該第二絕緣層18通常包括具有較該BPSG層爲 低的蝕刻率之HTO(高溫氧化物)層。使用HTO層作爲下絕 緣層之理由係如下所述。 當週邊區域閘電極和位元線電氣連接時，可藉由直接 連接位元線之多晶體與閘電極之多晶體而使接觸電阻爲常 數。由於上述閘電極具有包括多晶體和矽化鎢的雙重結構 ，必須移除靠近接觸區域的矽化鎢。矽化鎢一般係藉由使 用移除矽化鎢之化學品而加以移除》在此移除過程中， ΗΤΟ層係用作爲保護ΗΤΟ層之下的BPSG層薄膜免遭移除 〇 然而，因爲HTO層係用作爲位元線之下絕緣層，而當 形成儲存節點接觸孔26時因絕緣層不同蝕刻率而使斜坡產 生，如參考號碼28所示。上述HTO層具有相對慢的蝕刻 率。 接觸區域之面積因蝕刻斜坡減小，因而使接觸電阻增 加。再者，可能產生接觸未開之現象。 第三圖顯示先前技藝半導體記憶體裝置之金屬接觸。 在第三圖中，先前技藝半導體記憶裝置之週邊電路區 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）408338 A7 __B7__ V. Description of the Invention (Field of Invention) The present invention relates to a method for manufacturing a semiconductor memory device, and more specifically, to a method for manufacturing a semiconductor memory device, which solves the problem caused by the insulating layer. The problem of contact formation caused by different etch rates. BACKGROUND OF THE INVENTION: The first figure is a layout diagram illustrating a method of manufacturing a semiconductor memory device according to the prior art and the present invention. Referring to the first figure, the layout of the cell array area of the semiconductor memory device includes a plurality of gate polycrystals GP1-GP4 and a plurality of bit lines BL1-BL3. Furthermore, this layout shows the bit line contact bt and the storage node contact ST-the second diagram is a cross-sectional view of a semiconductor memory device according to the prior art taken along the line χ_χ 'shown in the first diagram. Referring to the second figure, a method for manufacturing storage node contact of a cell array region in a prior art semiconductor memory device includes the steps of manufacturing a device isolation layer 12 on a semiconductor substrate 10 and a semiconductor substrate 1 including the device isolation layer 12 The first insulating layer η is fabricated on 〇. A plurality of polycrystalline pads are formed to be electrically connected to the semiconductor substrate 10 between the device isolation layers 12 by penetrating the first insulating layer 14. The first insulating layer M and the polycrystalline pads 16 are formed to have a flat upper surface. . The second insulating layer 18 is formed on the polycrystalline pad 16 and the first insulating layer 14 as a lower insulating layer. The third and fourth insulating layers 22, 24 are sequentially formed on the second insulating layer 18 including the bit lines 20. 3 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 meals) (Please read the unintentional matter on the back before filling this page) 乂 -------- 1 -δϋί ---- --- Line-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 408338 a? __ ^ Β7 V. Description of the invention (less) The above bit line 20 is a polycrystalline silicon layer 20a , A tungsten silicide layer 20b, and an anti-reflection coating 20c. The second, third, and fourth insulating layers 18, 22, and 24 are etched to expose portions of the polycrystalline pad 16, thereby forming storage node contact holes 26. The first, third, and fourth insulating layers 14, The 22 and 24 series include a BPSG (boron phosphorosilicate glass) layer, respectively. However, the second insulating layer 18 generally includes an HTO (High Temperature Oxide) layer having a lower etch rate than the BPSG layer. The reason for using the HTO layer as the lower insulating layer is as follows. When the gate electrode and the bit line in the peripheral area are electrically connected, the contact resistance can be made constant by directly connecting the poly crystal of the bit line and the poly crystal of the gate electrode. Since the above gate electrode has a dual structure including a polycrystal and tungsten silicide, the tungsten silicide must be removed near the contact area. Tungsten silicide is generally removed by using chemicals that remove tungsten silicide. During this removal process, the ΗΤΟ layer is used to protect the BPSG layer film under the ΗΤΟ layer from being removed. However, because of the HTO layer It is used as the insulating layer under the bit line, and when the storage node contact hole 26 is formed, a slope is generated due to different etching rates of the insulating layer, as shown in reference number 28. The HTO layer described above has a relatively slow etching rate. The area of the contact area is reduced by the etching slope, which increases the contact resistance. Furthermore, contact may not occur. The third figure shows the metal contacts of prior art semiconductor memory devices. In the third picture, the peripheral circuit area of the previous technology semiconductor memory device 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)
Ia--------r l·--11---線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 408393 五、發明說明（> ) 域中的金屬接觸係藉由在半導體基板10上製成電晶體30 ，並在包括該電晶體30之該半導體基板10上製成第一至 第四絕緣層14、18、22、24而形成。第一至第四絕緣層14 、18、22、24係加以蝕刻以使半導體基板10在電晶體30 之間的部份曝露，從而形成金屬接觸孔32。在製造金屬接 觸孔32中，如同儲存節點接觸孔26之形成，係因絕緣層 之不同的蝕刻率而產生如參考號碼34所示之陡峭斜坡。造 成在形成障壁層時以及塡塞如鎢之導電層時產生失敗。此 外，此陡峭斜坡可能導致接觸未打開(contact not open)。 爲了防止接觸未打開，接觸之臨界尺寸應增加。然而 ，當接觸之臨界尺寸增加時，金屬接觸孔32兩側上的金屬 接觸孔32與電晶體30之間的間隔餘裕則會減小。 發明槪述； 本發明係試圖解決上述問題，且其目的爲提供一種製 造半導體記憶體裝置之方法，其可避免故障，如在製成儲 存節點接觸孔及金屬接觸孔時的接觸未打開，並且改良金 屬接觸與閘電極之間的不對準餘裕。 另一目的係提供一種製造半導體記憶裝置之方法，其 可使靠近儲存節點接觸孔及金屬接觸孔的絕緣層均勻化。 圖式之簡單說明 熟知此項技藝者將可藉由參考以下所附圖式而了解本 發明並使其目的更臻明瞭，於該等圖式中： 第一圖係說明根據先前技藝和本發明之製造半導體記 憶體裝置之方方法的佈局圖； 5 本紙張尺度適用令國國家標準（CNS)A4規格（210x297公釐） I ^ I ^ I i I I I I I 1- t ^ I I I I J I 一s]·« l· I I tl — If— (請先w讀背面之注$項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 408388 A7 ________B7 ____ 五、發明說明（y ) 第二圖係沿第一圖所示之線χ-χ’所取之根據先前技藝 之半導體記憶體裝置之截面圖； 第三圖顯示先前技藝半導體記憶體裝置之金屬接觸； 第四圖係沿第一圖所示之線χ·χ’所取之根據本發明之 實施例的截面圖； 第五A至五D圖係沿第一圖中所示之線Y-Y’所取之說 明根據本發明之製造半導體記憶體裝置之方法的截面圖； 第六A至六D圖係沿第一中所示之線Z-Z’所取之說明 根據本發明之製造半導體記憶體裝置之方法的截面圖： 第七A至七D圖係說明根據本發明之製造半導體記憶 裝置之方法的週邊電路區域之截面圖；以及 第八圖係顯示根據本發明之半導體記憶裝置之金屬接 觸的截面圖。 較佳實施例之詳細說明： 參照第四圖至第八圖，在根據本發明之實施例的製造 半導體記憶體裝置之方法中，墊接觸孔係藉由蝕刻在具有 單元陣列區以周邊電路區之半導體基板上的第一絕緣層而 形成。導電墊ll〇b係藉由以導電層塡塞墊接觸孔而形成， 而具有相關於第一絕緣層材料之蝕刻選擇率的第二絕緣層 112係形成在包括導電墊110b之第一絕緣層1〇6上。位元 線1M係形成在單元陣列區中的第二絕緣層112上。位元 線114下部以外的第二絕緣層112區域係藉由回蝕移除。 第三和第四層118、120係依序形成遍於包括位元線114’之 半導體基板100上，而儲存節點接觸孔122係藉由蝕刻該 6 ^張尺度適用1國國家標準（CNS)A4規格（210 X 297公釐） --------^tr-L-------線 <請先Μ讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 408393 A7 _ B7____ 五、發明說明（< ) 第二和第四絕緣層118、120而形成於單元陣列區中。金屬 接觸孔126係藉由蝕刻第四、第三以及第一層120、118、 106而形成於周邊電路區中。根據該方法，可在形成位元 線接觸、儲存節點接觸以及金屬接觸等區域時確認絕緣層 而防止接觸未開及塡塞導電層失敗，從而可使接觸尺寸減 小，並且改良金屬接觸與閘電極之間的不對準餘裕。此外 ，可減小在周邊電路區中，金屬接觸的斜度。 現在將參照第四圖至第八圖詳細說明根據本發明之較 佳實施例。 在第四圖至第八圖中，具有如第四圖中所示之半導體 記憶體裝置之元件相同功能的元件係具有相同的參考號碼 。第四圖係顯示沿第一圖之線X-X’所取之根據本發明的截 面圖。 參照第四圖，元件隔離層102係形成於半導體基板 100上，而第一絕緣層106係形成於包括該元件隔離層102 之半導體基板100上。導電墊ll〇b係藉由蝕刻第一絕緣層 i〇6，利用將電氣連至半導體基板100之多晶矽層等而形成 於元件隔離層102之間。元件隔離層102和導電墊li〇b係 互相部份重疊以改良墊接觸孔形成餘裕。第一絕緣層106 和導電墊ll〇b具有平坦表面。第二絕緣層112a係部份形 成於第一絕緣層106上作爲形成於其上之位元線114’的下 部絕緣層。舉例而言，位元線114’具有由依序形成的多晶 矽層U4a及矽化鎢114b組成的多層圖樣。第三和第四絕 緣層118、120係依序形成覆於包括位元線114’之半導體基 7 本紙適用_國國家標準(CNS)A4規格（210 X 297公g ) 0 I---i I -----I --I----^ (請先閱讀背面之注意事項再填寫本頁) 40S3S8 A7 B7 五、發明說明（V) 板100上。第一、第三、以及第四絕緣層106、118、120 係一般被使用作爲絕緣層的BPSG層，而第二絕緣層U2a 係具有相關於BPSG層爲相對低之蝕刻率的HTO層。 藉由蝕刻多晶墊110b上的第四絕緣層丨20以及第三絕 緣層118，儲存節點接觸孔112即形成。由於儲存節點接 觸孔122係藉由蝕刻同爲BPSG層的第四和第三絕緣層120 、118，則藉由均勻的蝕刻率，儲存節點接觸孔122之底部 面積相對於其口部面積不會大幅減小。 第五A至五D圖係沿第一圖中所示之線Y-Y’所取之的 截面圖，而第六A至六D圖係沿第一圖中所示之線Z-Z’所 取之截面圖，用以說明根據本發明之實施例的製造半導體 記憶體裝置之方法。 參照第五A圖及第六A圖，在根據本發明之實施例的 製造半導體記憶體裝置之方法中，元件隔離層102以及電 晶體104a係根據一般方法形成於半導體基板1〇〇上。 舉例而言，電晶體104a包括具有依序形成之多晶矽層 、矽化鎢層以及矽氮化物層的閘電極，以及由氮化矽間隔 物組成的閘電極。 中間層絕緣薄膜之第一絕緣層106係形成於包括電晶 體104a之半導體基板100上。舉例而言，第一絕緣層1〇6 具有BPSG層。第一絕緣層106係經蝕刻以於元件隔離層 102之間以及電晶體104a之間曝露半導體基板1〇〇，從而 形成墊接觸孔i〇8a、108b »特別而言，第六a圖所示之墊 接觸孔108b係藉由SAC(自對準接觸)方法而形成。 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------I------· I I (請M讀背面之注意事項再填窝本頁) 訂： -線· 經濟部智慧財產局員工消費合作社印製 4083B8 A/ B7 五、發明說明（q) 在第五B圖以及第六B圖中，墊接觸孔i〇8a、108b係 塡塞以導電層，如多晶矽層，以形成導電墊11〇a、11〇b。 第一絕緣層106以及導電墊110a、i10b係藉由如 CMP(化學機械拋光)之平坦蝕刻程序而具有平坦表面。第 二絕緣層112係形成於包括導電墊11〇a、u〇b之第—絕緣 層106上’該第二絕緣層112係由如具有相關於第—絕緣 層i06之蝕刻率的HTO等材料形成。 參照第五C圖以及第六C圖，第二絕緣層112係被蝕 刻以曝露導電墊ll〇a、ll〇b的部份，從而形成位元線接觸 孔113a、113b。用於製造位元線以及抗反射層114c之由依 序形成的導電層114a、114b組成的多重層係形成於包括該 位元線接觸孔113a、113b之該第二絕緣層112上。舉例而 言’導電層114a、114b係包括多晶矽層以及矽化鎢之多重 層’而抗反射層U4c係包括PE-TEOS層以及氧氮化矽 (Si〇N)之多重層。導電層114a、114b以及抗反射層114c係 利用爲位元線形成光罩之光阻劑層圖樣（未圖示)加以蝕刻 以形成位元線114 ^ 最後，在移除該光阻劑層圖樣之後，單元陣列區之位 元線接觸係藉由經由前回蝕程序蝕刻位元線114下部以外 在位元線114兩側之第二絕緣層而形成，如第五D圖及第 六D圖所示。由於抗反射層114c係藉由前回蝕程序移除， 因位元線114’而有的步階差異，相較於先前技藝而言，係 爲相當均勻。 第七A圖至第七D圖係用於說明根據本發明之半導體 9 本纸張反度適用中國國家標準（ClNiS)Ail規格⑵0 x 297公釐） --------------义--- (請t閱讀背面之注意事項再填寫本頁) 訂. i線. 經濟部智慧財產局員工消費合作社印製 408398 at ______B7__________ 五、發明說明（β ) 記億體裝置之製造方法的周邊電路區域之截面圖。 參照第七A圖，在周邊電路區域中’元件隔離層102 和電晶體104b係根據一般方法形成在半導體基板100上。 例如以BPSG製成的第一絕緣層106係形成在包括該 電晶體104b的半導體基板100上。 在第七Β圖中，例如以具有相關於第一絕緣層106之 蝕刻選擇率之ΗΤΟ製成的第二絕緣層112係形成在第一絕 緣層106上。 參照第七C圖，第二絕緣層112和第一絕緣層106係 被蝕刻以曝露半導體基板100的部份，從而形成位元線接 觸孔113c。由依序形成之用於位元線形成之導電層以及抗 反射層組成的多重層係形成在包括該位元線接觸孔113c之 第二絕緣層112上。多重層係利用光阻劑層圖樣(未圖示) 作圖樣作爲單元陣列區域之位元線形成法以形成位元線。 其後，位元線114之下的部份以外的第二絕緣層112 係藉由前回蝕程序移除以形成周邊電路區域之位元線接觸 ，如第七D圖中所示。由於抗反射層114c係藉由前回蝕程 序移除，由位元線114’產生的步階差異相對於先前技藝而 言顯得相當均均。 藉由移除位元線兩側之第二絕緣層112,在以下爲形 成如第四圖所示之儲存節點接觸孔122的程序中，可具有 均勻的絕緣結構，其使得可形成具有和緩斜度的儲存節點 接觸孔122。 第八圖係顯示根據本發明之半導體記憶體裝置之金屬 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----I--------- ^___ - ' {請先閱讀背面之注意事項再填寫本頁) 訂_ _ 線. 經濟部智慧財產局員工消費合作杜印製 408398 A7 ------—------ 五、發明說明（q ) 接觸的截面圖。 參照第八圖，爲了在周邊電路區域形成金屬接觸’電 晶體104c係形成在半導體基板100上，且多重絕緣層106 、118、120係依序形成在包括該電晶體i〇4c的半導體基板 100 上。 多重絕緣層106、118、120係被蝕刻以曝露電晶體 104c之間的半導體基板100部份，從而形成金屬接觸孔 126。相對於先前藝而言，金屬接觸孔126與電晶體l04e 之間的間隔餘裕b係爲增大，此乃因爲所有的多重絕緣餍 106、118、120包括BPSG層。金屬接觸孔區域中的HTO 層係已藉由上述之前回蝕程序移除，則肇因於絕緣層之間 不同的蝕刻率的接觸未打開(contact not open)現象不會發生 〇 此外，金屬接觸之步階差異係因HTO層的移除而減小 (請知閱讀背面之注意事項再填寫本頁) •線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Ia -------- rl · --11 --- line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 408393 V. Description of Invention (>) The metal contact in the domain is formed by forming a transistor 30 on the semiconductor substrate 10 and forming first to fourth insulating layers 14, 18, 22, 24 on the semiconductor substrate 10 including the transistor 30. . The first to fourth insulating layers 14, 18, 22, and 24 are etched to expose portions of the semiconductor substrate 10 between the transistors 30, thereby forming metal contact holes 32. In manufacturing the metal contact hole 32, as in the formation of the storage node contact hole 26, a steep slope as shown in reference number 34 is generated due to the different etching rates of the insulating layer. This results in failures when forming the barrier layer and congesting a conductive layer such as tungsten. In addition, this steep slope may cause contact not open. To prevent the contact from opening, the critical size of the contact should be increased. However, as the critical size of the contact increases, the margin between the metal contact hole 32 and the transistor 30 on both sides of the metal contact hole 32 decreases. SUMMARY OF THE INVENTION The present invention is an attempt to solve the above-mentioned problems, and an object thereof is to provide a method for manufacturing a semiconductor memory device, which can avoid malfunctions, such as contact not being opened when a storage node contact hole and a metal contact hole are made, and Improved misalignment margin between metal contacts and gate electrodes. Another object is to provide a method for manufacturing a semiconductor memory device, which can uniformize an insulating layer near a storage node contact hole and a metal contact hole. Brief description of the drawings Those skilled in the art can understand the present invention and make its purpose clearer by referring to the following drawings, in these drawings: The first drawing illustrates the prior art and the present invention Layout diagram of the method for manufacturing semiconductor memory devices; 5 This paper size applies the national standard (CNS) A4 specification (210x297 mm) I ^ I ^ I i IIIII 1- t ^ IIIIJI one s] · «l · II tl — If— (please read the note $ on the back before filling out this page) Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 408388 A7 ________B7 ____ V. Description of the invention (y) The second picture is along the first picture The cross-sectional view of the semiconductor memory device according to the prior art taken by the line χ-χ 'shown. The third figure shows the metal contact of the semiconductor memory device of the prior art. The fourth figure is along the line χ shown in the first figure. Cross-sectional view of an embodiment according to the present invention taken by χ ′; the fifth A to five D diagrams are taken along the line Y-Y ′ shown in the first diagram to explain the manufacture of a semiconductor memory device according to the present invention Sectional view of the method; sixth A to sixth D series A cross-sectional view taken along the line Z-Z 'shown in the first, illustrating a method of manufacturing a semiconductor memory device according to the present invention: The seventh A to seventh D diagrams illustrate a method of manufacturing a semiconductor memory device according to the present invention A cross-sectional view of a peripheral circuit area of the semiconductor device; and an eighth view is a cross-sectional view showing a metal contact of a semiconductor memory device according to the present invention. Detailed description of the preferred embodiment: Referring to FIGS. 4 to 8, in a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, a pad contact hole is etched in a region having a cell array and a peripheral circuit region by etching. The first insulating layer is formed on a semiconductor substrate. The conductive pad 110b is formed by plugging the pad contact hole with a conductive layer, and the second insulating layer 112 having an etching selectivity related to the material of the first insulating layer is formed on the first insulating layer including the conductive pad 110b. 1〇6. The bit line 1M is formed on the second insulating layer 112 in the cell array region. The area of the second insulating layer 112 other than the lower part of the bit line 114 is removed by etch back. The third and fourth layers 118 and 120 are sequentially formed on the semiconductor substrate 100 including the bit line 114 ', and the storage node contact hole 122 is etched to the 6 ^ th dimension to apply a national standard (CNS) A4 specification (210 X 297 mm) -------- ^ tr-L ------- line < Please read the precautions on the back before filling in this page) Staff of Intellectual Property Bureau, Ministry of Economic Affairs Consumption cooperation Du printed 408393 A7 _ B7____ 5. Description of the invention (<) The second and fourth insulating layers 118 and 120 are formed in the cell array region. The metal contact hole 126 is formed in the peripheral circuit region by etching the fourth, third, and first layers 120, 118, and 106. According to this method, it is possible to confirm the insulating layer when preventing the bit line contact, storage node contact, and metal contact from being formed to prevent contact failure and congestion of the conductive layer, thereby reducing the contact size and improving metal contact and gate electrode. Misalignment between margins. In addition, the slope of the metal contact in the peripheral circuit area can be reduced. A preferred embodiment according to the present invention will now be described in detail with reference to the fourth to eighth drawings. In the fourth to eighth figures, components having the same functions as those of the semiconductor memory device shown in the fourth figure have the same reference numbers. The fourth figure is a sectional view according to the present invention taken along line X-X 'of the first figure. Referring to the fourth figure, the element isolation layer 102 is formed on the semiconductor substrate 100, and the first insulating layer 106 is formed on the semiconductor substrate 100 including the element isolation layer 102. The conductive pad 110b is formed between the element isolation layers 102 by etching the first insulating layer 106 and using a polycrystalline silicon layer or the like that is electrically connected to the semiconductor substrate 100. The element isolation layer 102 and the conductive pad l0b partially overlap each other to improve the pad contact hole formation margin. The first insulating layer 106 and the conductive pad 110b have a flat surface. The second insulating layer 112a is partially formed on the first insulating layer 106 as a lower insulating layer of the bit line 114 'formed thereon. For example, the bit line 114 'has a multi-layered pattern composed of a polycrystalline silicon layer U4a and a tungsten silicide layer 114b which are sequentially formed. The third and fourth insulation layers 118 and 120 are sequentially formed on the semiconductor substrate including the bit line 114 '. 7 This paper is applicable to _National Standard (CNS) A4 specification (210 X 297 g) 0 I --- i I ----- I --I ---- ^ (Please read the notes on the back before filling this page) 40S3S8 A7 B7 V. Description of the invention (V) on the board 100. The first, third, and fourth insulating layers 106, 118, and 120 are generally used as the BPSG layer of the insulating layer, and the second insulating layer U2a is an HTO layer having a relatively low etching rate relative to the BPSG layer. By etching the fourth insulating layer 20 and the third insulating layer 118 on the polycrystalline silicon pad 110b, the storage node contact hole 112 is formed. Since the storage node contact hole 122 is etched by the fourth and third insulating layers 120 and 118, both of which are BPSG layers, the area of the bottom of the storage node contact hole 122 is not relative to its mouth area by a uniform etching rate. Significantly reduced. The fifth A to D drawings are cross-sectional views taken along line Y-Y 'shown in the first figure, and the sixth A to D drawings are taken along line Z-Z' shown in the first figure. The cross-sectional view is taken to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. 5A and 6A, in a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, an element isolation layer 102 and a transistor 104a are formed on a semiconductor substrate 100 according to a general method. For example, the transistor 104a includes a gate electrode having a polycrystalline silicon layer, a tungsten silicide layer, and a silicon nitride layer formed in this order, and a gate electrode composed of a silicon nitride spacer. The first insulating layer 106 of the interlayer insulating film is formed on the semiconductor substrate 100 including the transistor 104a. For example, the first insulating layer 106 has a BPSG layer. The first insulating layer 106 is etched to expose the semiconductor substrate 100 between the element isolation layer 102 and the transistor 104a, thereby forming pad contact holes 108a, 108b »In particular, as shown in the sixth a The pad contact hole 108b is formed by a SAC (self-aligned contact) method. 8 This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) ------- I ------ · II (please read the notes on the back and fill in this page) Order:-Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4083B8 A / B7 V. Description of the Invention (q) In Figures 5B and 6B, the pad contact holes 108 and 108b are blocked. A conductive layer, such as a polycrystalline silicon layer, is used to form the conductive pads 11a and 11b. The first insulating layer 106 and the conductive pads 110a and i10b have a flat surface by a flat etching process such as CMP (Chemical Mechanical Polishing). The second insulating layer 112 is formed on the first insulating layer 106 including the conductive pads 11a and u0b. The second insulating layer 112 is made of a material such as HTO having an etching rate related to the first insulating layer i06. form. Referring to FIG. 5C and FIG. 6C, the second insulating layer 112 is etched to expose portions of the conductive pads 110a and 110b, thereby forming bit line contact holes 113a and 113b. Multiple layers of sequentially formed conductive layers 114a, 114b for manufacturing the bit line and the anti-reflection layer 114c are formed on the second insulating layer 112 including the bit line contact holes 113a, 113b. For example, 'the conductive layers 114a, 114b include multiple layers of a polycrystalline silicon layer and tungsten silicide' and the antireflection layer U4c includes multiple layers of a PE-TEOS layer and silicon oxynitride (SiON). The conductive layers 114a, 114b and the anti-reflection layer 114c are etched using a photoresist layer pattern (not shown) forming a mask for the bit lines to form the bit lines 114. Finally, the photoresist layer pattern is removed After that, the bit line contact of the cell array region is formed by etching the second insulating layers on both sides of the bit line 114 except the lower part of the bit line 114 through a previous etch-back process, as shown in the fifth and sixth D drawings. Show. Since the anti-reflection layer 114c is removed by the previous etch-back procedure, the step difference due to the bit line 114 'is relatively uniform compared to the prior art. The seventh diagram A to the seventh diagram D are used to illustrate the semiconductor 9 according to the present invention. The inversion of this paper applies the Chinese National Standard (ClNiS) Ail specification (0 x 297 mm) ----------- --- Yi --- (Please read the notes on the back and then fill out this page) Order. I line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed at 408398 at ______B7__________ 5. Description of the Invention (β) A cross-sectional view of a peripheral circuit region of a manufacturing method. Referring to FIG. 7A, in the peripheral circuit region, the 'element isolation layer 102 and the transistor 104b are formed on the semiconductor substrate 100 according to a general method. A first insulating layer 106 made of, for example, BPSG is formed on a semiconductor substrate 100 including the transistor 104b. In the seventh B diagram, a second insulating layer 112 made of, for example, YTO having an etching selectivity related to the first insulating layer 106 is formed on the first insulating layer 106. Referring to FIG. 7C, the second insulating layer 112 and the first insulating layer 106 are etched to expose a portion of the semiconductor substrate 100, thereby forming a bit line contact hole 113c. A multiple layer composed of a sequentially formed conductive layer for forming bit lines and an anti-reflection layer is formed on the second insulating layer 112 including the bit line contact hole 113c. The multiple layer system uses a photoresist layer pattern (not shown) as a pattern for forming a bit line of a cell array region to form a bit line. Thereafter, the second insulating layer 112 other than the portion below the bit line 114 is removed by a previous etch-back process to form a bit line contact of the peripheral circuit area, as shown in the seventh D diagram. Since the anti-reflection layer 114c is removed by a previous etch-back process, the step difference produced by the bit line 114 'appears to be quite uniform compared to the prior art. By removing the second insulating layer 112 on both sides of the bit line, in the following procedure for forming the storage node contact hole 122 as shown in the fourth figure, it can have a uniform insulating structure, which can be formed with a gentle slope Degree of storage node contact hole 122. The eighth figure shows that the metal paper size of the semiconductor memory device according to the present invention is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---- I --------- ^ ___ -'{Please read the precautions on the back before filling this page) Order _ _ Line. Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 408398 A7 (Q) Sectional view of the contact. Referring to FIG. 8, in order to form a metal contact in the peripheral circuit region, a transistor 104 c is formed on the semiconductor substrate 100, and multiple insulating layers 106, 118, and 120 are sequentially formed on the semiconductor substrate 100 including the transistor 104 on. The multiple insulating layers 106, 118, and 120 are etched to expose portions of the semiconductor substrate 100 between the transistors 104c, thereby forming metal contact holes 126. Compared with the prior art, the margin b between the metal contact hole 126 and the transistor 104e is increased, because all the multiple insulating layers 106, 118, and 120 include a BPSG layer. The HTO layer in the metal contact hole area has been removed by the previous etch-back procedure described above, and the contact not open phenomenon due to the different etch rates between the insulating layers will not occur. In addition, the metal contact The difference in steps is reduced due to the removal of the HTO layer (please read the notes on the back and fill in this page) A4 size (210 X 297 mm)