KR101195261B1 - Method for manufacturing semiconductor device using damascene process - Google Patents

Abstract

A method of manufacturing a semiconductor device using the damascene process of the present invention includes forming a first interlayer insulating film on a semiconductor substrate provided with a lower structure; Forming a second interlayer insulating film on the first interlayer insulating film; Forming a trench in the second interlayer insulating film; Sequentially depositing a barrier metal film and a bit line conductive film in the trench; Forming a bit line stack including a capping layer pattern, a bit line conductive layer, and a barrier metal layer by forming a capping layer pattern covering the bit line conductive layer and extending to cover the adjacent second interlayer insulating layer; Forming a contact hole between the bit line stacks using the capping layer pattern as a mask, and etching the second interlayer insulating layer so that an insulating layer for spacers remains on sidewalls of the barrier metal layer and the bit line conductive layer; And forming a bit line spacer film on sidewalls of the bit line stack and the spacer insulating film.

Damascene, capping layer pattern, spacer layer

Description

Method for manufacturing semiconductor device using damascene process

1 to 7 are views illustrating a method of manufacturing a semiconductor device using a damascene process according to an embodiment of the present invention.

8 to 11 are views illustrating a method of manufacturing a semiconductor device using a damascene process according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 112 barrier metal film

114: conductive film for bit line 122, 136: capping film pattern

128, 142: spacer insulating film 130, 144: bit line spacer film

The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a damascene process that can implement a fine pattern.

Recently, a DRAM having a high capacity (DRAM) has been used as a semiconductor memory device. In order to form a DRAM device, first, a transistor including word lines and a source / drain is formed on a semiconductor substrate, and contact holes are formed on the source and the drain, respectively, through an interlayer insulating layer. After forming the storage node electrodes of the bit line and the capacitor respectively connected to the source and the drain through the contact hole, the dielectric film and the plate electrode are formed on the storage node electrode to form the capacitor. A self-aligned contact (SAC) process is mainly used to form a contact plug connecting the source, the bit line, the drain, and the storage node electrode. In the self-aligned contact (SAC) process, an etching profile is obtained by using an etch selectivity between an oxide film and a nitride film. Even if a misalignment occurs, the nitride film acts as a buffer film, causing a short circuit between the conductive film and the contact plug. (short) can be prevented.

However, as semiconductor devices are highly integrated, a method of forming a fine pattern is being researched more easily than a conventional self-aligned contact (SAC) process. A way to facilitate fine patterns There is a damascene process in the gown.

Since the damascene process has excellent etching on the oxide film, the use of the damascene process can be easily formed due to the advantage of easily forming a conductive film pattern that is difficult to pattern by etching. However, the damascene process is not easy to apply a method such as a self-aligned contact (SAC) process to surround the conductive film pattern with a spacer film such as a nitride film to prevent a short between the contact plug and the conductive film pattern.

An object of the present invention is to provide a method for manufacturing a semiconductor device using a damascene process that can easily form a fine pattern by preventing a short circuit between the contact plug and the bit line stack.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device using a damascene process according to the present invention, forming a first interlayer insulating film on a semiconductor substrate having a lower structure; Forming a second interlayer insulating film on the first interlayer insulating film; Sequentially depositing a barrier metal film and a bit line conductive film in the trench; Forming a bit line stack including a capping layer pattern, a bit line conductive layer, and a barrier metal layer by forming a capping layer pattern covering the bit line conductive layer and extending to cover the adjacent second interlayer insulating layer; Forming a contact hole between the bit line stacks using the capping layer pattern as a mask, and etching the second interlayer insulating layer so that a spacer insulating layer remains on sidewalls of the barrier metal layer and the bit line conductive layer; And forming a bit line spacer layer on sidewalls of the bit line stack and the spacer insulating layer.

In the present invention, the capping film pattern may be formed to be wider than the width of the bit line conductive film.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device using a damascene process according to the present invention, forming a first interlayer insulating film on a semiconductor substrate having a lower structure; Forming a second interlayer insulating film on the first interlayer insulating film; Sequentially depositing a barrier metal film and a bit line conductive film in the trench, and etching the barrier metal film and the bit line conductive film by a predetermined depth from the surface of the bit line conductive film; Forming a reverse inclined gap between the second interlayer insulating film and the bit line conductive film; Forming a bit line stack by forming a capping layer pattern filling the gap having an inclined shape; Forming a contact hole by etching a second interlayer insulating layer using the capping layer pattern as a mask to leave an insulating layer for spacers on side surfaces of the metal layer and the barrier metal layer; And forming a bit line spacer layer on sidewalls of the bit line stack and the spacer insulating layer.

In the present invention, the capping film pattern may be formed to be wider than the width of the bit line conductive film.

The forming of the reverse inclined gap may be formed by etching an edge of the second interlayer insulating layer adjacent to the bit line conductive layer, and may use wet cleaning.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated by like reference numerals throughout the specification.

1 to 7 are views illustrating a method of manufacturing a semiconductor device using a damascene process according to an embodiment of the present invention.

First, referring to FIG. 1, a first interlayer insulating layer 104 is formed on a semiconductor substrate 100 in which an active region is defined by a trench isolation layer 102. Next, a second interlayer insulating film 106 is formed over the first interlayer insulating film 104. The first interlayer insulating film 104 may include a substructure, for example, a word line and a landing plug. In addition, the first interlayer insulating film 104 may include an oxide-based insulating film, for example, a high density plasma oxide (POS) film, a plasma enhanced tetra ethyl ortho silicate (PETOS), a low pressure (LP) teos or a USG film. It may be formed by selecting one or more from the group of the oxide film series. The second interlayer insulating film 106 serves as a trench formation layer in a subsequent damascene process. In this case, the first interlayer insulating film 104 and the second interlayer insulating film 106 may be formed of the same material. In this case, although not shown in the drawing, an etch stop layer may be inserted into an interface between the first interlayer insulating film 104 and the second interlayer insulating film 106 and used as an etch termination point when forming the trench. Next, a photoresist film is coated and then patterned to form a photoresist pattern 108 that exposes the second interlayer insulating film 106.

Next, referring to FIG. 2, an etching process using the photosensitive film pattern 108 as a mask is performed to form the trench 110 in the second interlayer insulating film 106.

3, the barrier metal film 112 and the bit line conductive film 114 are sequentially stacked in the trench 110. To this end, after the barrier metal film 112 and the bit line conductive film 114 are deposited, the planarization process is performed on the bit line conductive film 114 to expose the second interlayer insulating film 106. The barrier metal film 112 may be formed of a titanium / titanium nitride (Ti / TiN) film, and the bit line conductive film 114 may be formed of a tungsten (W) film. At this time, the titanium nitride (TiN) film serves to prevent the titanium (Ti) film from reacting with the source material when depositing the conductive film 114 for the bit line, for example, the tungsten (W) film, or the conductive material for the bit line. It serves as a glue layer to facilitate the growth of the film 114.

Next, referring to FIG. 4, a capping layer 118 having an interlayer insulating layer and an etching selectivity is formed on the entire surface of the semiconductor substrate 100 including the barrier metal layer 112 and the bit line conductive layer 114. Here, the capping layer 118 may include a silicon nitride layer. Subsequently, the photoresist film is coated on the capping film 118 and then patterned to form the photoresist pattern 120.

Next, referring to FIG. 5, an etching process using the photosensitive film pattern 120 as a mask may be performed to form a first material adjacent to the barrier metal film 112, the bit line conductive film 114, and the bit line conductive film 114. A bit line stack having a structure in which a barrier metal layer 112, a bit line conductive layer 114, and a capping layer pattern 122 are stacked by forming a capping layer pattern 122 covering a portion of the two interlayer insulating layer 106. 124 is formed.

In the conventional case, although the spacer film is formed to surround the bit line stack, in the present invention, the capping film pattern 122 may be formed to have a width wider than that of the bit line conductive film 114. In addition, the space margin between the bit line stack 124 and the bit line stack 124 should be sufficiently taken into consideration, so that the capping layer pattern 122 is positioned at the correct position, for example, the bit line stack 124 and the bit line. A portion of the second interlayer insulating film 106 adjacent to the stack 124 is covered.

Subsequently, a photoresist film is coated and patterned on the entire surface of the substrate including the bit line stack 124 to form a photoresist pattern 125 that exposes a region where a contact hole is to be formed.

Next, referring to FIG. 6, the second interlayer insulating film 106 and the first interlayer insulating film 104 are etched using the photoresist pattern 125 as a mask, and then connected between the bit line stack 124 and the active region of the substrate. The contact hole 126 is formed. The capping layer pattern 122 may prevent the capping layer pattern 122 from acting as a buffer layer and exposing the bit line stack 124 to be damaged and shorted as in the self-aligned contact (SAC) process. Can be.

The spacer insulating layer 128 is formed on the side surface of the bit line stack 124 without removing the second interlayer insulating layer 106 under the capping layer pattern 122.

Next, referring to FIG. 7, a nitride film for bit lines is formed on the entire surface of the semiconductor substrate 100 including the bit line stack 124 and the spacer insulating layer 128. Subsequently, an etch back process is performed on the bit line nitride layer to form the bit line spacer layer 130 on sidewalls of the bit line stack 124 and the first interlayer insulating layer.

Next, a contact plug 131 including a conductive material connected to the active region of the substrate is formed while filling the contact hole.

A semiconductor device using a damascene process according to the present invention includes a first interlayer insulating film 104 formed on a semiconductor substrate 100 and a barrier metal film 112 and a bit line on the first interlayer insulating film 104. A bit line stack 124 including a conductive film 114 and a capping film pattern 122 formed wider than the width of the bit line conductive film 114, and for spacers formed on side surfaces of the bit line stack. And an insulating film 128, a bit line spacer film 130, and a contact plug 131.

As described above, in the case of the semiconductor device using the damascene process according to the present invention, the capping film pattern 122 is formed to be wider than the width of the bit line conductive film 114, so that the self-aligned contact (SAC) process is performed. The capping layer pattern 122 serves as a buffer layer to prevent the bit line stack 124 from being exposed and damaged to short-circuit.

On the other hand, it is preferable to form the capping film pattern 122 so that the position of the capping film pattern 122 overlaps the bit line conductive film 114. Accordingly, a method for enabling accurate overlap will be described.

8 to 13 are views illustrating a method of manufacturing a semiconductor device using a damascene process according to another embodiment of the present invention.

First, as shown in FIGS. 1 to 3, the barrier metal film 112 and the bit line conductive film 114 are disposed in the second interlayer insulating film 106 using a damascene process. Briefly, the first interlayer insulating film 104 and the second interlayer insulating film 106 are formed on the semiconductor substrate 100, and a predetermined region of the second interlayer insulating film 106 is formed on the second interlayer insulating film 106. An exposed photoresist pattern 108 is formed. Next, an etching process is performed using the photoresist pattern 108 as a mask to form the trench 110 in the second interlayer insulating layer 106. Next, a barrier metal film 112 and a bit line conductive film 114 are deposited in the trench 110.

Next, referring to FIG. 8, a planarization process, for example, an etchback process, is performed to expose the second interlayer insulating film 106 to the semiconductor substrate 100. In this case, the etch back process may be performed for a sufficient time to overetch the surface of the bit line conductive film 114 by a predetermined depth d. As a result, an upper edge of the second interlayer insulating layer 106 and sidewalls adjacent to the bit line conductive layer 114 are exposed. As described above, a capping film is formed in the space formed on the bit line conductive film 114 while being etched by a predetermined depth d from the surface of the bit line conductive film 114.

Next, referring to FIG. 9, a cleaning process is performed on the semiconductor substrate 100 including a space formed over the bit line conductive film 114. In this case, it is preferable to use a cleaning solution that can cause loss of the oxide film. When the cleaning process is performed in this way, a portion of the second interlayer insulating film 106 adjacent to the bit line conductive film 114 is lost and a reverse slope is formed between the second interlayer insulating film 106 and the bit line conductive film 114. (negative profile) A gap in the shape occurs. The reverse inclination-shaped gap thus formed serves to guide the capping film to have a wider width than the bit line conductive film 114 as the capping film is formed and then the planarization process is performed.

Next, referring to FIG. 10, a capping layer 134 is formed on the entire surface of the semiconductor substrate 100. The capping layer 134 fills a space formed on the bit line conductive layer 114 and a gap having a reverse slope formed between the second interlayer insulating layer 106 and the bit line conductive layer 114.

Next, referring to FIG. 11, the capping film 134 may be planarized, for example, an etch back process, to expose the second interlayer insulating film 106. Then, the capping film pattern 136 having a width wider than that of the bit line conductive film 114 is naturally formed, and includes the barrier metal film 112, the bit line conductive film 114, and the capping film pattern 136. The bit line stack 138 is formed. Here, the capping layer pattern 122 has a reverse slope shape.

Subsequently, a photoresist film is coated and patterned on the entire surface of the substrate including the bit line stack 138 to form a photoresist pattern 140 that exposes a region where a contact hole is to be formed.

Next, referring to FIG. 12, the second interlayer insulating film 106 and the first interlayer insulating film 104 are etched using the photoresist pattern 140 as a mask to form a contact hole 142 between the bit line stacks 138. . Here, as in the self-aligned contact (SAC) process, the capping layer pattern 136 serves as a buffer layer to prevent the bit line stack 138 from being exposed and damaged to short-circuit. In this case, the second interlayer insulating layer 106 positioned below the capping layer pattern 136 formed to have a width wider than that of the bit line conductive layer 114 may be formed on the side of the bit line stack 138 without being removed. The spacer insulating film 144 is formed.

Next, referring to FIG. 13, a bit line nitride film is formed on the entire surface of the semiconductor substrate 100 including the bit line stack 138 and the spacer insulating layer 144. An etch back process is performed on the bit line nitride layer to form the bit line spacer layer 146 on sidewalls of the bit line stack 138 and the spacer insulating layer 144. A contact plug 148 including a conductive material connected to the active region of the substrate is formed while filling the contact hole.

As described so far, according to the method of manufacturing a semiconductor device using the damascene process according to the present invention, the capping layer pattern is formed in a wide width of the capping layer pattern when the bit line stack is formed. As a result, the bit line stack may be exposed and damaged to prevent short-circuit, thereby easily forming a fine pattern.

In addition, by performing a cleaning process for generating oxide film loss, a mask process may be omitted when forming a spacer, and the occurrence of misalignment may be reduced because the capping film pattern overlaps at the correct position.

Claims (6)

Forming a first interlayer insulating film on a semiconductor substrate having a substructure; Forming a second interlayer insulating film on the first interlayer insulating film; Forming a trench in the second interlayer insulating film; Sequentially depositing a barrier metal film and a bit line conductive film in the trench; Forming a bit line stack including a capping layer pattern, a bit line conductive layer, and a barrier metal layer by forming a capping layer pattern covering the bit line conductive layer and extending to cover the adjacent second interlayer insulating layer; Forming a contact hole between the bit line stacks using the capping layer pattern as a mask, and etching the second interlayer insulating layer so that a spacer insulating layer remains on sidewalls of the barrier metal layer and the bit line conductive layer; And And forming a bit line spacer film on the sidewalls of the bit line stack and the spacer insulating film. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The capping film pattern is a semiconductor device manufacturing method using a damascene process, characterized in that formed to be wider than the width of the conductive film for the bit line. Forming a first interlayer insulating film on a semiconductor substrate having a substructure; Forming a second interlayer insulating film on the first interlayer insulating film; Forming a trench in the second interlayer insulating film; Sequentially depositing a barrier metal film and a bit line conductive film in the trench; Etching the bit line conductive film to expose a portion of the sidewall of the second interlayer insulating film; Forming a reverse inclined gap between the second interlayer insulating film and the bit line conductive film; Forming a bit line stack by forming a capping layer pattern filling the gap having an inclined shape; Forming a contact hole by etching a second interlayer insulating layer using the capping layer pattern as a mask to leave an insulating layer for spacers on side surfaces of the metal layer and the barrier metal layer; And forming a bit line spacer film on the sidewalls of the bit line stack and the spacer insulating film. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3, The capping film pattern is a semiconductor device manufacturing method using a damascene process, characterized in that formed to be wider than the width of the conductive film for the bit line. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3, The forming of the reverse inclined gap may include forming an edge of a second interlayer insulating layer adjacent to the bit line conductive layer by etching the edge line. Claim 6 has been abandoned due to the setting registration fee. The method of claim 3, The step of forming the reverse inclined gap, the method of manufacturing a semiconductor device using a damascene process, characterized in that the use of wet cleaning.

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