KR19990033869A - Method for forming self-aligned contact of semiconductor device - Google Patents

Abstract

A method of forming a self-aligned contact of a semiconductor device is disclosed. After forming an active region and a device isolation region on the semiconductor substrate, a gate provided as a word line is formed on the substrate. A nitride spacer is formed on the sidewall of the gate, and a nitride layer is deposited on the entire surface of the resultant to form an etch stop layer. After forming the interlayer insulating film on the etch stop layer, the interlayer insulating film is selectively etched to form a self-aligned contact that exposes the semiconductor substrate between the gates. Remove the etch stop layer. By forming a thin etch stop layer formed of a nitride film on the active region, it is possible to protect the device isolation layer from being cut by the etch stop layer even if the contact is misaligned with the active region. Therefore, it is possible to prevent a defect such as a refresh or a standby state caused by the deterioration of the separation characteristic from adjacent cells.

Description

Method for forming self-aligned contact of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in forming a contact of a semiconductor device using a self-aligned contact process, to prevent cutting of an element isolation layer. And a method for forming a self-aligned contact of a semiconductor device.

As semiconductor devices become more integrated and faster, the formation of fine patterns is required, and not only the width of the wiring but also the space between the wiring and the wiring is significantly reduced. In particular, the formation of a contact connecting the isolated device regions formed in the semiconductor substrate with the use of a highly conductive thin film should be performed while securing the alignment margin, device isolation margin, and the like. To occupy. Thus, in a memory device such as a dynamic random access memory (DRAM), the contact serves as a major factor in determining the size of a memory cell.

Recently, semiconductor process technology of 0.25 μm or less has been rapidly developed, and it is difficult to form a contact having a fine size using a conventional contact formation method. Furthermore, in a memory device using multiple conductive layers, the height between the conductive layer and the conductive layer is further increased by the interlayer insulating film, making the process of forming a contact between the conductive layers very difficult. Accordingly, a method of forming a contact by a self-aligned method in order to reduce the cell area when a design rule such as a memory cell has no margin and a pattern of the same shape is repeated has been developed.

Self-aligned contact technology is a method of forming a contact by using a step of the surrounding structure, the contact of various sizes by using the height of the surrounding structure, the thickness of the insulating film at the position where the contact is to be formed and the etching method, etc. without using a mask You can get it. Thus, the greatest advantage of the self-aligned contact technique is that it can form fine contacts without requiring an alignment margin. Self-aligned contact technology, which is currently used most, is a method of forming a contact using an etching selectivity of oxide and nitride in an anisotropic etching process.

1A to 4B are cross-sectional views illustrating a method of forming a self-aligned contact of a semiconductor device by a conventional method. Here, each a degree is a sectional view of an active region, and each b degree is a sectional view of a word line (ie, a gate line) region.

1A and 1B, the device isolation layer 12 is formed by performing a conventional device isolation process on the silicon substrate 10, thereby separating the substrate 10 into an active region and a device isolation region. Subsequently, after the gate oxide film 14 is grown on the substrate 10 through a thermal oxidation process, the polysilicon layer 16, the tungsten silicide layer 18, and the first nitride film 20 are sequentially formed thereon. Deposit. Subsequently, a photoresist film (not shown) is formed on the first nitride film 20 through a photolithography process, and the first nitride film 20 is patterned as a gate pattern using the photoresist film as an etching mask. . Subsequently, after the photoresist film is removed, the tungsten silicide layer 18 and the polysilicon layer 16 are continuously etched using the patterned first nitride film 20 as an etching mask to form a gate having a polycide structure. (Word line) is formed.

2A and 2B, after depositing a second nitride film on the entire surface of the resultant product on which the gate is formed, the second nitride film is anisotropically etched to form a nitride film spacer 22 on the sidewall of the gate.

Referring to FIGS. 3A and 3B, by depositing a high temperature oxide (HTO) -based insulating film having a thickness of 300 kPa or more, as an insulating film on the entire surface of the resultant formed nitride film spacer 22, A diffusion barrier layer 26 is formed. The diffusion barrier layer 26 serves to prevent the diffusion of boron (B) and phosphorus (P) in the BPSG film to be used as the interlayer insulating film in the subsequent process to the interface of the silicon substrate 10.

4A and 4B, a borophosphosilicate glass (BPSG) film is deposited on the entire surface of the resultant layer on which the diffusion barrier layer 26 is formed to form an interlayer insulating film 28. Subsequently, a photoresist film 30 is formed on a portion where the contact of the interlayer insulating film 28 is to be formed through a photolithography process, and the interlayer insulating film 28 is anisotropically etched using the photoresist film 30 as an etching mask. Thereby forming a self-aligned contact 32. In this case, since the top and sidewalls of the word line are surrounded by the nitride films 20 and 22, the interlayer insulating film 28 formed of an oxide layer may be selectively etched to prevent short between the word line and the contact 32. (See “B” in FIG. 4B). However, in the active region, since the device isolation layer 12 and the interlayer insulating layer 28 are both formed of an oxide-based film, when the misalignment occurs during the photolithography process for forming the contact, the device isolation layer 12 is cut. Problems appear (see "A" in Figure 4A). As a result, the isolation characteristics of adjacent cells become weak, resulting in a failure such as a refresh or a stand-by fail.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional method described above, and an object of the present invention is to form a contact of a semiconductor device using a self-aligned contact process. The present invention provides a method for forming a contact of a semiconductor device which can prevent the device isolation film from being cut even if phosphorus occurs.

1A to 4B are cross-sectional views illustrating a method of forming a self-aligned contact of a semiconductor device by a conventional method.

5A to 9B are cross-sectional views illustrating a method of forming a self-aligned contact of a semiconductor device according to the present invention.

<Explanation of symbols for main parts of the drawings>

100 semiconductor substrate 102 device isolation film

104: gate oxide film 106,108: polyside gate

110: first nitride film 112: nitride film spacer

114: oxide film 116: etch stop layer

118: interlayer insulating film 120: self-aligned contact

In order to achieve the above object, the present invention, forming an active region and an isolation region on the semiconductor substrate; Forming a gate provided as a word line on the semiconductor substrate; Forming a nitride film spacer on sidewalls of the gate; Forming an etch stop layer by depositing a nitride film on the entire surface of the resultant product on which the nitride film spacer is formed; Forming an interlayer insulating layer on the etch stop layer; Selectively etching the interlayer insulating film to form a self-aligned contact exposing the semiconductor substrate between the gates; And removing the etch stop layer.

The forming of the gate may include forming a gate insulating film, a conductive layer, and a nitride film sequentially on the semiconductor substrate on which the active region and the device isolation region are formed; And etching the nitride layer and the conductive layer through a photolithography process to form a gate capped with the nitride layer.

Before forming the etch stop layer, the method may further include forming an oxide film on the entire surface of the resultant product in which the nitride film spacer is formed. Preferably, the oxide film is formed to a thickness of 200 kPa or less through a thermal oxidation process, and the oxide film is removed in the step of removing the etch stop layer.

Preferably, the etch stop layer nitride film is deposited to a thickness of 200 kPa or less.

According to the present invention, when the photolithography process for forming a self-aligned contact is performed, a thin etch stop layer formed of a nitride film is formed on the active region in the active region, so that the contact is misaligned with the active region. Even if it is, the device isolation layer is protected from being cut by the etch stop layer. Therefore, the separation characteristic from adjacent cells is not deteriorated, and a defect such as a refresh or a standby state error can be prevented from occurring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 9B are cross-sectional views illustrating a method of forming a self-aligned contact of a semiconductor device according to the present invention. Here, each a degree is a sectional view of an active region, and each b degree is a sectional view of a word line (ie, a gate line) region.

5A and 5B illustrate forming a word line. The substrate 100 is made active by performing a conventional device isolation process, such as a local oxidation of silicon (LOCOS) process or an improved LOCOS process, on the silicon substrate 100 to form the device isolation film 102. It is divided into a region and a device isolation region. Subsequently, the gate oxide film 104 is grown on the substrate 100 through a thermal oxidation process, and then the polysilicon layer 106, the tungsten silicide layer 108, and the first nitride film 110 are sequentially formed thereon. Deposit. The first nitride film 110 serves to cap a gate to be formed in a subsequent process.

Subsequently, a photoresist film (not shown) is formed on the first nitride film 110 through a photolithography process, and the first nitride film 110 is patterned as a gate pattern using the photoresist film as an etching mask. . Subsequently, after the photoresist layer is removed, the tungsten silicide layer 108 and the polysilicon layer 106 are continuously etched using the patterned first nitride layer 110 as an etch mask (word line). ).

6A and 6B illustrate forming the nitride film spacer 112. After the gate is formed as described above, a second nitride film is deposited on the entire surface of the resultant product. Next, the nitride film spacer 112 is formed on the sidewall of the gate by anisotropically etching the second nitride film. In this case, since the capping layer 110 positioned on the gate is also formed of a nitride film, the gate is surrounded by the nitride films 110 and 112. The nitride film spacer 112 has a high etching selectivity with respect to an oxide film provided as an interlayer insulating film in an etching process for subsequent self-aligned contact formation.

7A and 7B illustrate forming an etch stop layer 116. After the nitride film spacer 112 is formed as described above, an etch stop layer 116 is formed by thinly depositing the second nitride film to a thickness of 200 μm or less on the entire surface of the resultant. The etch stop layer 116 not only prevents boron (B) and phosphorus (P) from diffusing into the interface of the silicon substrate 100 in the BPSG film to be used as the interlayer insulating film in a subsequent process, but also the subsequent self-alignment. In the etching process for forming a contact, the etch endpoint serves to protect the device isolation layer 102.

On the other hand, when the nitride film provided to the etch stop layer 116 is in direct contact with the interface of the silicon substrate, defects such as stacking faults are generated at the interface. Therefore, in order to prevent such a phenomenon, a thermal oxidation process may be performed before the etching stop layer 116 is formed to form a thin oxide film 114 of 200 μs or less. Since the oxide film 114 and the etch stop layer 116 are to be removed after the contact is formed, the oxide film 114 and the etch stop layer 116 are preferably formed to have a thickness of 200 Å or less.

8A and 8B illustrate forming a self-aligned contact 122. After forming the etch stop layer 116 as described above, a BPSG film is deposited on the entire surface of the resultant to form an interlayer insulating film 118. Next, the BPSG film is flowed to planarize the interlayer insulating film 118.

Subsequently, a photoresist film 120 is formed at a portion where a contact of the interlayer insulating film 118 is to be formed through a photolithography process, and the interlayer insulating film 118 is anisotropic using the photoresist film 120 as an etching mask. Etching forms a self-aligned contact 122. In this case, since the top and sidewalls of the word line are surrounded by the nitride layers 110 and 112, the interlayer insulating layer 118 formed of an oxide layer may be selectively etched to prevent a short between the word line and the contact 122. (See “D” in FIG. 8B). In the active region, although the device isolation layer 102 and the interlayer insulating layer 118 are both formed of an oxide-based film, the contact formation is performed in the etch stop layer 116 made of a nitride film disposed on the device isolation layer 102. Since the etching process is completed, the device isolation layer 102 is not cut even when the contact 122 is misaligned with the active region (see “C” in FIG. 8A).

9A and 9B illustrate a step of removing both the etch stop layer 116 and the oxide film 114 by increasing the etching time after removing the photoresist film 120.

Therefore, according to the contact forming method of the semiconductor device according to the present invention, when the photolithography process for forming a self-aligned contact is performed, a thin etch stop layer formed of a nitride film is formed on the active region in the active region. Even if it is misaligned with the active region, the etch stop layer protects the device isolation layer from being cut. Therefore, the separation characteristic from adjacent cells is not deteriorated, and it is possible to prevent a defect such as a refresh or a standby state error from occurring.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

Forming an active region and an isolation region on the semiconductor substrate; Forming a gate provided as a word line on the semiconductor substrate; Forming a nitride film spacer on sidewalls of the gate; Forming an etch stop layer by depositing a nitride film on the entire surface of the resultant product on which the nitride film spacer is formed; Forming an interlayer insulating layer on the etch stop layer; Selectively etching the interlayer insulating film to form a self-aligned contact exposing the semiconductor substrate between the gates; And And removing the etch stop layer. The method of claim 1, wherein the forming of the gate comprises: Sequentially forming a gate insulating film, a conductive layer, and a nitride film on the semiconductor substrate on which the active region and the device isolation region are formed; And etching the nitride film and the conductive layer through a photolithography process to form a gate capped with the nitride film at an upper portion thereof. The contact forming method of claim 1, further comprising forming an oxide layer on an entire surface of the resultant product in which the nitride layer spacer is formed before the forming of the etch stop layer. 4. The method of claim 3, wherein the oxide film is formed to a thickness of 200 kPa or less through a thermal oxidation process. The method of claim 3, wherein the oxide layer is removed in the removing of the etch stop layer. The method of claim 1, wherein the etch stop layer nitride film is deposited to a thickness of 200 μm or less.