KR20030032650A - Method of forming memory device within multi nitride spacer - Google Patents
Method of forming memory device within multi nitride spacer Download PDFInfo
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- KR20030032650A KR20030032650A KR1020010064596A KR20010064596A KR20030032650A KR 20030032650 A KR20030032650 A KR 20030032650A KR 1020010064596 A KR1020010064596 A KR 1020010064596A KR 20010064596 A KR20010064596 A KR 20010064596A KR 20030032650 A KR20030032650 A KR 20030032650A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 150000004767 nitrides Chemical class 0.000 claims abstract description 50
- 125000006850 spacer group Chemical group 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 13
- 230000008569 process Effects 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000007789 gas Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 자동정렬콘택에서 누설전류를 방지하는 다층의 나이트라이드막 스페이서 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a multilayer nitride film spacer for preventing leakage current in an automatic alignment contact of a semiconductor device.
디바이스가 고집적, 고기능화 함에 따라 회로의 선폭 및 콘택의 크기는 더욱 더 미세화되는 경향이 나타나고 있다. 이에 따라 워드라인(word line)과 비트라인(bit line), 워드라인과 셀(cell) 및 비트라인과 셀 사이에 누설 전류가 발생하는 브리지(bridge)가 심화되고 있다.As devices become more integrated and more functional, the line widths and contact sizes of circuits tend to become even smaller. Accordingly, a bridge in which leakage current occurs between word lines and bit lines, word lines and cells, and bit lines and cells is deepening.
특히 워드라인 또는 비트라인 사이에 콘택홀(contact hole)을 개방할 경우에는 사진공정시의 미스얼라인(misalign)에 의한 전기적 단락(short)에 의한 브리지가 발생할 수 있다. 따라서 워드라인 또는 비트라인 간에 콘택홀을 개방할 경우에는 자동정렬콘택(Self Aligned Contact, SAC)을 이용하고 있다. 자동정렬콘택은 콘택홀을 식각할 때, 식각저지층으로 워드라인이나 비트라인에 스페이서를 형성하여, 사진공정시 맞춤이 어긋나는 오정렬이 발생하여도 콘택홀과 워드라인 또는 비트라인 사이에 전기적 단락(short)이 생기지 않도록 하는 기술이다. 자동정렬콘택에 의하여 사진공정의 맞춤 마진(align margin)이 확대되고, 칩 사이즈의 축소가 가능하게 된다. 이러한 브리지의 특성을 개선하기 위한 스페이서는 콘택홀뿐만 아니라 도전성 라인(line)에도 형성한다.In particular, when a contact hole is opened between a word line or a bit line, a bridge may occur due to an electrical short due to misalignment during a photo process. Therefore, when opening contact holes between word lines or bit lines, self-aligned contacts (SACs) are used. When the contact hole is etched, the spacer forms a word line or a bit line as an etch stop layer to etch the contact hole, so that an electrical short circuit between the contact hole and the word line or bit line may occur even if misalignment occurs in the photo process. It is a technique to prevent the occurrence of short). The automatic alignment contact allows the alignment margin of the photo process to be enlarged and the chip size to be reduced. Spacers for improving the characteristics of such bridges are formed in conductive lines as well as contact holes.
스페이서로는 회로선폭이 큰 0.22μm 이상의 디바이스에서는 화학기상증착(Chemical Vapor Deposition, CVD) 산화막을 사용하였다. 그런데 산화막 스페이서는 디자인 룰이 0.18μm~0.13μm으로 미세화되고 텅스텐 등의 금속을비트라인이나 워드라인으로 사용함에 따라, 상기 산화막 스페이서는 나이트라이드(nitride) 스페이서로 변경하여 워드라인이나 비트라인으로 쓰이는 금속의 산화를 막는 것과 동시에 스페이서의 두께도 일정 정도 감소시킬 수 있었다.As a spacer, a chemical vapor deposition (CVD) oxide film was used in a device having a circuit width of 0.22 μm or more. However, as the oxide spacer has a design rule of 0.18 μm to 0.13 μm and uses a metal such as tungsten as a bit line or word line, the oxide spacer is changed into a nitride spacer and used as a word line or bit line. In addition to preventing the oxidation of the metal, the thickness of the spacer was also reduced to some extent.
그러나 디바이스가 미세화되어도 누설전류에 의한 비트라인과 셀에서의 브리지의 발생 때문에 스페이서로 사용하는 나이트라이드막의 두께를 감소시키는데는 한계가 있는 바, 이에 따라 미세화에 의한 콘택 크기의 감소에 의해 콘택 저항은 급격히 증가되어 디바이스의 특성은 열악해지는 문제점이 있다.However, even when the device is miniaturized, there is a limit to reducing the thickness of the nitride film used as a spacer due to the occurrence of bridges in the bit line and the cell due to leakage current. There is a problem in that the characteristics of the device are deteriorated rapidly.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 스페이서의 두께를 감소시키면서도 누설전류의 값은 작은 특성을 갖는 반도체소자 제조방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device having a characteristic of reducing the thickness of the spacer and having a small leakage current.
도 1은 본 발명에 따른 스토리지노드 콘택 감광막 형성 단면도,1 is a cross-sectional view of forming a storage node contact photoresist film according to the present invention;
도 2는 본 발명에 따른 다층의 나이트라이드막 형성 단면도,2 is a cross-sectional view of forming a multilayer nitride film according to the present invention;
도 3은 본 발명에 따른 다층의 나이트라이드막 스페이서 형성 단면도,3 is a cross-sectional view of forming a multilayer nitride film spacer according to the present invention;
도 4는 본 발명에 따른 폴리실리콘 증착 단면도,4 is a cross-sectional view of polysilicon deposition according to the present invention,
도 5는 본 발명에 따른 다층 나이트라이드막 형성 레시피(recipe)를 나타내는 개략도.5 is a schematic diagram showing a multilayer nitride film forming recipe according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
100 : 비트라인 115 : 층간절연막100: bit line 115: interlayer insulating film
140 : 다층의 나이트라이드막 150 : 폴리실리콘막140: multilayer nitride film 150: polysilicon film
상기 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은, 기판상에 도전성 라인을 형성하는 단계; 상기 도전성 라인을 포함하는 기판에 절연막을 증착하고, 평탄화하는 단계; 상기 평탄화된 절연막을 선택적 식각하여 상기 도전성 라인 사이에 콘택홀을 형성하는 단계; 및 상기 콘택홀의 측벽에 나이트라이드-옥시나이트라이드-나이트라이드로 이루어진 다층의 나이트라이드막 스페이서를 형성하는 단계를 포함한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a conductive line on the substrate; Depositing and planarizing an insulating film on a substrate including the conductive line; Selectively etching the planarized insulating layer to form contact holes between the conductive lines; And forming a multilayer nitride film spacer made of nitride-oxynitride-nitride on the sidewall of the contact hole.
또한, 상기 목적을 달성하기 위한 본 발명의 반도체 집적회로의 스페이서는 나이트라이드-옥시나이트라이드-나이트라이드로 이루어진 다층의 나이트라이드막인 것을 특징으로 한다.In addition, the spacer of the semiconductor integrated circuit of the present invention for achieving the above object is characterized in that the multilayer nitride film made of nitride-oxynitride-nitride.
본 발명은 나이트라이드막 중간에 옥시나이트라이드막을 형성하여 나이트라이드막 내부에 옥시나이트라이드가 있는 다층의 나이트라이드막을 형성하여 나이트라이드막의 두께를 감소시키면서도 나이트라이드막의 내부에 존재하는 옥시나이트라이드에 의하여 누설전류의 특성은 양호하게 된다.According to the present invention, an oxynitride film is formed in the middle of the nitride film to form a multilayer nitride film having oxynitride inside the nitride film, thereby reducing the thickness of the nitride film, but by oxynitride present in the nitride film. The characteristic of the leakage current becomes good.
상술한 목적, 특징들 및 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일실시예를 상세히 설명한다.The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 실시예는 전하저장전극의 폴리실리콘 플러그 형성을 위해서 층간절연막(비트라인과 하부전극사이에 존재하는 산화막)을 평탄화 시킨 후 스토리지노드 콘택을 형성하고, 비트라인과 스토리지노드 콘택간의 자동정렬콘택(Self Aligned Contact, SAC)의 누설전류 발생을 억제하기 위해 콘택 내부에 다층의 나이트라이드막 스페이서를 형성한다. 즉, 하나의 레시피(recipe)안에서 나이트라이드막이 증착된 후 O2가스를 튜브 내부에 플로우(flow)시켜 증착된 나이트라이드막을 옥시나이트라이드화 시키거나 또는 옥시나이트라이드막을 증착하고, 다시 나이트라이드막을 증착하여 나이트라이드-옥시나이트라이드-나이트라이드(nitride-oxynitride-nitride)의 다층의 나이트라이드막을 형성한다. 다음으로 기판을 전면적으로 식각하여 다층의 나이트라이드막의 스페이서를 형성하여 비트라인과 하부저장전극과의 누설전류를 억제시키는 자동정렬콘택(Self Aligned Contact, SAC)을 형성하는 것을 특징으로 한다. 이하 도면과 함께 설명한다.An embodiment of the present invention is to planarize the interlayer insulating film (an oxide film between the bit line and the lower electrode) to form a polysilicon plug of the charge storage electrode, to form a storage node contact, and to automatically arrange between the bit line and the storage node contact. In order to suppress leakage current of a self aligned contact (SAC), a multilayer nitride film spacer is formed inside the contact. That is, after the nitride film is deposited in one recipe, O 2 gas is flowed into the tube to oxynitride the deposited nitride film or to deposit an oxynitride film, and then the nitride film is By depositing, a multilayer nitride film of nitride-oxynitride-nitride is formed. Next, the substrate is entirely etched to form spacers of a multilayer nitride film, thereby forming a self-aligned contact (SAC) that suppresses leakage current between the bit line and the lower storage electrode. It demonstrates with drawing below.
도 1 내지 도 4에는 도시되어 있지 않지만 도면 하부에는 공정이 완료된 트랜지스터, 소자분리막 및 층간절연막 등이 형성되어져 있다.Although not shown in FIGS. 1 to 4, transistors, device isolation films, and interlayer insulating films, which have been processed, are formed in the lower portion of the drawing.
도 1은 본 발명에 따른 스토리지노드 콘택 감광막 형성한 후의 단면도이다.1 is a cross-sectional view after forming the storage node contact photoresist film according to the present invention.
하드마스크(105)를 사용하여 비트라인(100)을 형성하고, 식각저지막으로 비트라인 스페이서(110)을 형성 후에 층간절연막(115)을 증착하고 평탄화시킨다.The bit line 100 is formed using the hard mask 105, and the interlayer insulating layer 115 is deposited and planarized after the bit line spacer 110 is formed of the etch stop layer.
다음으로 스토리지노드 콘택을 형성하기 위하여 감광막 패턴(120)을 형성한다.Next, the photoresist pattern 120 is formed to form a storage node contact.
도 2는 본 발명에 따른 다층의 나이트라이드막(140) 형성한 후의 단면도이다.2 is a cross-sectional view after the multilayer nitride film 140 is formed according to the present invention.
상기 감광막 패턴(120)을 배리어(barrier)로 하여 스토리지노드 콘택(145)을 형성하고, 기판 전면에 나이트라이드막(125)을 증착한다. 나이트라이드막을 형성하는데 있어서 사용하는 가스로는 NH3와 DCS(SiH2Cl2)를 사용하며, 또는 상기 가스에 N2가스를 포함하여 사용한다. 나이트라이드막을 형성하는데 있어서 증착온도는 600℃ 내지 800℃의 온도범위로 하며, 압력은 1Torr이하로 LPCVD(Low Pressure hemical Vapor Deposition)로 증착한다.The storage node contact 145 is formed using the photoresist pattern 120 as a barrier, and the nitride layer 125 is deposited on the entire surface of the substrate. As a gas used in forming the nitride film, NH 3 and DCS (SiH 2 Cl 2 ) are used, or N 2 gas is included in the gas. In forming the nitride film, the deposition temperature is in the temperature range of 600 ° C. to 800 ° C., and the pressure is deposited by low pressure hemical vapor deposition (LPCVD) at 1 Torr or less.
다음으로 옥시나이트라이드막(130)을 형성하는데, 형성하는 방법으로는 일부 나이트라이드막을 산화시키는 방법 또는 옥시나이트라이드막을 증착하는 방법이 있다.Next, the oxynitride film 130 is formed, and the forming method may be a method of oxidizing some nitride films or a method of depositing an oxynitride film.
산화시키는 방법은 700℃ 이상의 온도에서 습식 또는 건식산화의 방법에 의하여 O2가스를 튜브 내부에 플로우(flow)시켜 증착된 일부 나이트라이드막을 옥시나이트라이드화하여 나이트라이드막을 산화시킨다.The oxidizing method oxidizes the nitride film by oxynitriding some nitride films deposited by flowing O 2 gas into the tube by a wet or dry oxidation method at a temperature of 700 ° C. or higher.
옥시나이트라이드막을 증착하는 방법은 650℃ 이상의 온도에서 NH3, DCS(SiH2Cl2) 또는 O2가스를 반응시켜 증착한다.The method of depositing an oxynitride film is deposited by reacting NH 3 , DCS (SiH 2 Cl 2 ) or O 2 gas at a temperature of 650 ° C. or higher.
다음으로 나이트라이드막(135)을 증착하여 나이트라이드-옥시나이트라이드-나이트라이드(nitride-oxynitride-nitride)의 다층의 나이트라이드막(140)을 형성한다.Next, the nitride film 135 is deposited to form a nitride film 140 having a multilayer of nitride-oxynitride-nitride.
도 3은 본 발명에 따른 나이트라이드막 스페이서(140a) 형성 후의 단면도이다.3 is a cross-sectional view after formation of the nitride film spacer 140a according to the present invention.
상기 다층의 나이트라이드막(140)을 에치백하여 스토리지노드 콘택(145)안에 나이트라이드(125a)-옥시나이트라이드(130a)-나이트라이드(135a)로 이루어진 스페이서를 형성한다.The multilayer nitride layer 140 is etched back to form a spacer including nitride 125a-oxynitride 130a and nitride 135a in the storage node contact 145.
도 4는 본 발명에 따른 폴리실리콘(150)을 증착한 후의 단면도이다.4 is a cross-sectional view after depositing the polysilicon 150 according to the present invention.
상기 나이트라이드막 스페이서를 형성한 후에는 BOE(Buffered Oxide Etcher)를 사용하여 콘택 계면을 세정하고, 폴리실리콘을 증착한다. 상기 폴리실리콘을 에치백하여 폴리실리콘 플러그를 형성하고, 이후 캐패시터, 층간절연막, 금속배선 공정 등을 실시하여 반도체소자를 완성한다.After the nitride film spacer is formed, the contact interface is cleaned using BOE (Buffered Oxide Etcher) to deposit polysilicon. The polysilicon is etched back to form a polysilicon plug, and then a capacitor, an interlayer insulating film, and a metal wiring process are performed to complete the semiconductor device.
도 5는 본 발명에 따른 다층의 나이트라이드막 형성 레시피(recipe)를 나타내는 개략도이다.5 is a schematic diagram showing a multilayer nitride film formation recipe according to the present invention.
카세트에 적재된 웨이퍼를 보트(boat)에 적재하여, 공정이 진행될 고온의 반응로에 보트를 일정 속도로 이동시켜 준다. 반응로에서 나이트라이드막을 증착하고, 산소 플로우를 시켜 일정 부분의 나이트라이드막을 옥시나이트라이드막으로 변화시키거나 또는 옥시나이트라이드막을 증착하고, 다시 나이트라이드막을 증착하여 다층의 나이트라이드막을 형성한다. 바람직하게는 상기 다층의 나이트라이드막은 인시츄(in-situ)로 진행한다.The wafer loaded on the cassette is loaded in a boat, and the boat is moved at a constant speed to a high temperature reactor where the process is to proceed. A nitride film is deposited in the reactor, oxygen flow is used to change a portion of the nitride film into an oxynitride film, or an oxynitride film is deposited, and the nitride film is further deposited to form a multilayer nitride film. Preferably, the multilayer nitride film proceeds in-situ.
상술한 다층의 나이트라이드막은 콘택홀의 스페이서의 형성뿐만 아니라 비트라인, 워드라인 또는 금속 배선라인과 같은 도전성 라인의 스페이서로서도 사용할 수 있다.The multilayer nitride film described above can be used not only for forming spacers of contact holes but also for spacers of conductive lines such as bit lines, word lines, or metal wiring lines.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어진 본 발명은, 스토리지노드 콘택을 형성할 때, 콘택 마스크공정에서 미스얼라인이 발생할 경우, 비트라인과 스토리지노드간에 누설전류가 발생하는 것을 극복할 수 있기 때문에 공정여유 확보와 수율을 향상할 수 있는 효과가 있다.According to the present invention as described above, when the storage node contact is formed, when a misalignment occurs in the contact mask process, leakage current is generated between the bit line and the storage node. There is an effect that can be improved.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100801727B1 (en) * | 2002-03-13 | 2008-02-11 | 주식회사 하이닉스반도체 | Method for forming contact of semiconductor device |
| US7772108B2 (en) | 2004-06-25 | 2010-08-10 | Samsung Electronics Co., Ltd. | Interconnection structures for semiconductor devices and methods of forming the same |
| US7871921B2 (en) | 2004-06-25 | 2011-01-18 | Samsung Electronics Co., Ltd. | Methods of forming interconnection structures for semiconductor devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100801727B1 (en) * | 2002-03-13 | 2008-02-11 | 주식회사 하이닉스반도체 | Method for forming contact of semiconductor device |
| US7772108B2 (en) | 2004-06-25 | 2010-08-10 | Samsung Electronics Co., Ltd. | Interconnection structures for semiconductor devices and methods of forming the same |
| US7871921B2 (en) | 2004-06-25 | 2011-01-18 | Samsung Electronics Co., Ltd. | Methods of forming interconnection structures for semiconductor devices |
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