KR20020058521A - Method for Fabricating of Semiconductor Device - Google Patents
Method for Fabricating of Semiconductor Device Download PDFInfo
- Publication number
- KR20020058521A KR20020058521A KR1020000086630A KR20000086630A KR20020058521A KR 20020058521 A KR20020058521 A KR 20020058521A KR 1020000086630 A KR1020000086630 A KR 1020000086630A KR 20000086630 A KR20000086630 A KR 20000086630A KR 20020058521 A KR20020058521 A KR 20020058521A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern density
- semiconductor device
- region
- pattern
- dummy pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000013461 design Methods 0.000 claims abstract description 8
- 230000005641 tunneling Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 식각 속도의 균일도를 향상시키어 터널링 전류를 줄이므로써 디바이스(Device)의 전기적 특성을 향상시키기 위한 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for improving the electrical characteristics of the device by improving the uniformity of the etching rate to reduce the tunneling current.
최근, 디자인 룰(Design Rule)의 축소와 저전압 구동 칩 개발의 요구에 따라서 게이트 산화막의 두께가 감소하는 추세이다.In recent years, the thickness of the gate oxide film has been reduced in accordance with the reduction of the design rule and the demand for the development of a low voltage driving chip.
따라서, 반도체 제조 공정시 사용되는 플라즈마에 의한 차징 데미지(Charging Damage)는 얇아진 게이트 산화막의 손상 문제와 관련되어 이슈(Issue)화되고 있다.Therefore, charging damage caused by plasma used in the semiconductor manufacturing process is becoming an issue related to a problem of thinned gate oxide.
플라즈마에서 유발되는 차지(Charge)의 콜렉터(Collector) 내지 안테나(Antenna) 역할은 폴리 라인(Poly Line) 또는 메탈 라인(Metal Line)이 하기 때문에 이들이 플라즈마에 노출되는 공정에서는 차징 데미지(Charging Damage) 문제를 심각하게 고려해야 한다.The charge collector (Collector) or antenna (Antenna) role in the plasma is played by a poly line or a metal line, so the charging damage problem in the process of exposure to the plasma Should be taken seriously.
폴리/메탈 라인(13) 형성 공정에서 유발되는 플라즈마 야기 데미지(Plasma Induced Damage)는 도 1a 내지 도 1b에 도시된 전자 쉐이딩(Shading) 효과에 기인한 이온 주입 전류 모델로서 설명된다.Plasma Induced Damage caused in the poly / metal line 13 forming process is described as an ion implantation current model due to the electron shading effect shown in FIGS. 1A-1B.
상기 폴리/메탈 라인(13) 식각 공정시 게이트 산화막(12)에 주입되는 전류의 양은 도 2에 도시된 바와 같이, 메인(Main) 식각 공정에서 오버(over) 식각 공정으로 넘어가는 시기에 가장 크게 증가한다.As illustrated in FIG. 2, the amount of current injected into the gate oxide layer 12 during the poly / metal line 13 etching process is the greatest at the time when the process is shifted from the main etching process to the over etching process. Increases.
이는 도 3에 도시된 바와 같이, 메인 식각 공정이 끝나는 시점에서 패턴 밀도가 낮은 영역의 폴리/메탈 라인(13)이 거의 제거되는 반면, 패턴 밀도가 높은 영역의 폴리/메탈 라인(13)은 남아있기 때문이다.As shown in FIG. 3, at the end of the main etching process, the poly / metal line 13 of the region having a low pattern density is almost removed, while the poly / metal line 13 of the region having a high pattern density remains. Because there is.
그리고, 상기 남아있는 폴리/메탈 라인(13)이 전하 콜렉터 역할을 하게 되어 패턴 밀도가 높은 영역의 이온 전류가 증가하게 된다.In addition, the remaining poly / metal lines 13 serve as charge collectors, thereby increasing ion current in a region having a high pattern density.
다시 말해서, 패턴 밀도가 낮은 영역에서는 이온 전류(Ii)와 전자 전류(Ie)가동일한 반면에 패턴 밀도가 높은 영역에서는 상기 폴리/메탈 라인(13)이 전하 콜렉터 역할을 함에 따라서 이온 전류가 증가되어 이온 전류(Ii)가 전자 전류(Ie)보다 크게 되므로 패턴 밀도가 높은 영역과 패턴 밀도가 낮은 영역간에 이온 전류의 차이가 발생되게 된다.In other words, the ion current (I i ) and the electron current (I e ) are the same in the region of low pattern density, whereas the poly / metal line 13 acts as a charge collector in the region of high pattern density. Since the ion current I i is larger than the electron current I e , the difference in the ion current occurs between the region having a high pattern density and the region having a low pattern density.
그리고, 상기 패턴 밀도가 높은 영역과 패턴 밀도가 낮은 영역간의 이온 전류(Ionic Current)의 차이는 상기 게이트 산화막(12)에 주입되는 이온을 터널링(Tunneling)하는 구동력(Driving Force)으로 작용하게 된다.The difference in the ion current between the region having a high pattern density and the region having a low pattern density serves as a driving force for tunneling ions injected into the gate oxide layer 12.
즉, 상기 이온 전류 차이로 인하여 상기 패턴 밀도가 높은 반도체 기판(11)과 패턴 밀도가 낮은 반도체 기판(11)간에 전압차이가 발생하게 되며, 상기 전압차로 인하여 대전된 이온의 터널링(Tunneling)이 발생하게 되는 것이다.That is, a voltage difference occurs between the semiconductor substrate 11 having a high pattern density and the semiconductor substrate 11 having a low pattern density due to the ion current difference, and tunneling of charged ions occurs due to the voltage difference. Will be done.
이와 같은 현상을 최소화하기 위해서는 식각이 진행되는 동안에 패턴 밀도가 높은 지역과 패턴 밀도가 낮은 지역간의 메탈이 균일하게 제거되어야 하지만, 디자인 룰 축소에 따른 종횡비 증가는 패턴의 조밀도에 따른 식각 속도 불균형 즉, 마이크로 로딩 이펙트(Micro Loading Effect)를 가중시키고 있는 실정이다.In order to minimize this phenomenon, metals between areas with high pattern density and areas with low pattern density should be uniformly removed during the etching process.However, the increase in aspect ratio due to the reduction of the design rule results in an unbalanced etching rate due to the density of the pattern. In this case, the micro loading effect is being increased.
그러나, 상기와 같은 종래의 반도체 소자의 제조방법은 디자인 룰이 축소됨에 따라서 종횡비가 증가되어 패턴의 조밀도에 따른 식각 속도 불균형을 가중시키므로 터널링 전류가 증가되어 소자의 특성이 열화되는 문제점이 있다.However, the conventional method of manufacturing a semiconductor device as described above has a problem that the aspect ratio is increased as the design rule is reduced, thereby increasing the etching rate imbalance according to the density of the pattern, thereby increasing the tunneling current and deteriorating the characteristics of the device.
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 패턴 밀도가 낮은 영역에 더미 패턴을 삽입하여 터널링 전류를 줄이므로써 소자의 전기적 특성을 향상시키기에 적합한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device suitable for improving the electrical characteristics of the device by reducing the tunneling current by inserting a dummy pattern in a region having a low pattern density to solve the above problems. There is this.
도 1a 내지 도 1b는 전자 쉐이딩에 의한 이온 주입 전류 모델을 나타낸 도면1A to 1B are diagrams illustrating an ion implantation current model by electron shading
도 2는 메탈 식각 공정이 진행되는 동안에 게이트 절연막에 주입되는 전하의 양을 나타낸 그래프2 is a graph showing the amount of charge injected into a gate insulating film during a metal etching process
도 3은 패턴 밀도에 따른 식각량의 차이를 나타내기 위하여 식각 공정중에 촬영한 단면 사진Figure 3 is a cross-sectional photograph taken during the etching process to show the difference in the amount of etching according to the pattern density
도 4는 메탈 식각이 진행되는 동안 엔드 포인트 신호를 나타낸 그래프4 is a graph showing an endpoint signal during metal etching
도 5는 라인 폭에 따른 임계치수를 나타낸 도면5 is a diagram illustrating a threshold dimension according to a line width.
도 6은 본 발명의 실시예에 따른 반도체 소자의 평면도6 is a plan view of a semiconductor device according to an embodiment of the present invention.
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은 플라즈마를 이용한 폴리/메탈 라인 형성 공정에 있어서, 패턴 밀도에 따른 식각 속도 차이를 줄이기 위하여 패턴 밀도가 낮은 영역에 더미 패턴을 형성함을 특징으로 한다.In the method of manufacturing a semiconductor device of the present invention for achieving the above object, in the poly / metal line forming process using plasma, a dummy pattern is formed in a region having a low pattern density in order to reduce the etching rate difference according to the pattern density. It is characterized by.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 4는 메탈 식각 공정 동안의 엔드 포인트 신호를 나타낸다.4 shows an endpoint signal during a metal etch process.
도 4에서 엔드 포인트 타임은 88초이며, 통상적으로, 68 ∼ 88초구간의 초반부에서는 패턴 밀도가 낮은 영역과 패턴 밀도가 높은 영역의 메탈 라인이 모두 남아있는데 반하여 후반부에서는 패턴 밀도가 높은 영역에만 메탈 라인이 남게 된다.In FIG. 4, the endpoint time is 88 seconds, and in the early part of the 68-88 second period, all the metal lines in the region with the low pattern density and the region with the high pattern density remain, whereas in the latter part, only the region with the high pattern density is used. The line remains.
따라서, 이온 주입 전류는 상기 엔드 포인트 타임에서 최대가 되게 된다.Thus, the ion implantation current is maximized at the end point time.
본 발명에서는 패턴 밀도가 낮은 영역의 주변에 더미 패턴을 삽입하여 칩 내부에서의 패턴 밀도의 불균형을 맞춤으로써 패턴간의 불균형적인 메탈 제거 시간을 줄이고자 한다.In the present invention, by imposing a dummy pattern around the region having a low pattern density, the imbalance of the pattern density in the chip is reduced to reduce the unbalanced metal removal time between the patterns.
더미 패턴의 삽입 규칙은 라인 폭에 따른 임계치수를 나타낸 도면인 도 5의 결과를 바탕으로 한다.The insertion rule of the dummy pattern is based on the result of FIG. 5, which is a diagram showing a threshold dimension according to the line width.
도 5는 라인 폭이 0.5㎛일 때, 스페이스를 0.4㎛∼5㎛까지 나눈 것으로, 1.0㎛ 스페이스까지는 프로세스(Process)의 식각 바이어스에 미치는 영향이 10%미만임을 보여준다.5 shows that when the line width is 0.5 μm, the space is divided by 0.4 μm to 5 μm, and the influence on the etching bias of the process is less than 10% up to the 1.0 μm space.
따라서, 본 발명에서는 패턴간의 스페이스가 최소 디자인 룰의 2배미만 되도록 더미 패턴을 삽입한다.Therefore, in the present invention, the dummy pattern is inserted so that the space between the patterns is less than twice the minimum design rule.
도 6은 0.18㎛ 로직 소자에서 디자인 룰(최소 L/S =0.23㎛/0.23㎛)을 기준으로 더미 패턴을 삽입한 예를 나타낸 것으로, 패턴간의 거리가 최소 디자인 룰의 2배인 0.46㎛ 미만이 되도록 형성하였다.6 illustrates an example of inserting a dummy pattern based on a design rule (minimum L / S = 0.23 μm / 0.23 μm) in a 0.18 μm logic element, such that the distance between the patterns is less than 0.46 μm, which is twice the minimum design rule. Formed.
상기와 같은 본 발명의 반도체 소자의 제조방법은 더미 패턴을 삽입하여 패턴간의 밀도 차이를 줄이어 식각 불균형으로 인한 터널링 전류를 줄일 수 있으므로 소자의 특성을 향상시킬 수 있는 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above can reduce the density difference between the patterns by inserting the dummy pattern, thereby reducing the tunneling current due to the etching imbalance, thereby improving the characteristics of the device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000086630A KR20020058521A (en) | 2000-12-30 | 2000-12-30 | Method for Fabricating of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000086630A KR20020058521A (en) | 2000-12-30 | 2000-12-30 | Method for Fabricating of Semiconductor Device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020058521A true KR20020058521A (en) | 2002-07-12 |
Family
ID=27689615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000086630A KR20020058521A (en) | 2000-12-30 | 2000-12-30 | Method for Fabricating of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020058521A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100847844B1 (en) * | 2007-08-10 | 2008-07-23 | 주식회사 동부하이텍 | Method of designing a dummy pattern for a semiconductor device |
| KR20160122894A (en) * | 2015-04-14 | 2016-10-25 | 삼성디스플레이 주식회사 | Thin film transistor substrate, display apparatus comprising the same, method for manufacturing thin film transistor substrate, and method for manufacturing display apparatus |
-
2000
- 2000-12-30 KR KR1020000086630A patent/KR20020058521A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100847844B1 (en) * | 2007-08-10 | 2008-07-23 | 주식회사 동부하이텍 | Method of designing a dummy pattern for a semiconductor device |
| US8117582B2 (en) | 2007-08-10 | 2012-02-14 | Dongbu Hitek Co., Ltd. | Method for placing dummy patterns in a semiconductor device layout |
| KR20160122894A (en) * | 2015-04-14 | 2016-10-25 | 삼성디스플레이 주식회사 | Thin film transistor substrate, display apparatus comprising the same, method for manufacturing thin film transistor substrate, and method for manufacturing display apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5610091A (en) | Method for manufacturing a non-volatile memory cell | |
| US6753242B2 (en) | Integrated circuit device and method therefor | |
| JP2004214510A (en) | Nonvolatile semiconductor memory and its manufacturing method | |
| KR20020058521A (en) | Method for Fabricating of Semiconductor Device | |
| KR100244402B1 (en) | Method of forming a trench isolation in a semiconductor device | |
| KR20060075442A (en) | Method for fabricating flash memory device | |
| KR20020076440A (en) | method for etching using plasma | |
| KR100237007B1 (en) | Fabrication method of flash memory cell | |
| KR100248155B1 (en) | Method for forming align key of field region | |
| KR20020050918A (en) | Method for Fabricating of Flash Memory Device | |
| KR100274355B1 (en) | Method of forming a word line in a flash memory device | |
| KR100290476B1 (en) | Method of manufacturing a split gate flash memory device | |
| KR100213224B1 (en) | Method for preventing deterioration of gate oxide using polysilicon layer for gate electrode | |
| KR100211650B1 (en) | Manufacturing method of semiconductor device | |
| KR960002071B1 (en) | Contact forming method of semiconductor device | |
| KR100349348B1 (en) | Method of etching a silicon layer | |
| KR100209719B1 (en) | Manufacture of semiconductor device | |
| KR100220240B1 (en) | Forming method for contact hole of semiconductor device | |
| KR100324325B1 (en) | Manufacturing method for mostransistor for electro static discharge | |
| KR0144163B1 (en) | Ipyromcel and preparation method thereof | |
| KR100218358B1 (en) | Manufacturing method of flash memory cell | |
| KR100305214B1 (en) | Method of manufacturing a flash memory cell | |
| JP3783240B2 (en) | Manufacturing method of flash memory | |
| KR930008079B1 (en) | Method of fabricating for eprom | |
| KR20070036203A (en) | Method for manufacturing recess gate in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |