KR930008079B1 - Method of fabricating for eprom - Google Patents

Method of fabricating for eprom Download PDF

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Publication number
KR930008079B1
KR930008079B1 KR1019910000107A KR910000107A KR930008079B1 KR 930008079 B1 KR930008079 B1 KR 930008079B1 KR 1019910000107 A KR1019910000107 A KR 1019910000107A KR 910000107 A KR910000107 A KR 910000107A KR 930008079 B1 KR930008079 B1 KR 930008079B1
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South Korea
Prior art keywords
forming
gate
oxide film
trench
drain
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KR1019910000107A
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Korean (ko)
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KR920015580A (en
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김종호
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금성일렉트론 주식회사
문정환
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Priority to KR1019910000107A priority Critical patent/KR930008079B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

An EPROM cell with a trench structure is prepared by (1) forming P/R on substrate selectively and ion implanting with high energy to form a source and a drain, (2) ion implanting for channel after forming an oxide film and a gate trench by etching the region except the source/drain, (3) forming a floating gate in the trench by forming an oxide film and a polysilicon film, and etching them, (4) forming a selective gate on the floating gate by forming an oxide and a polysilicon film, and etching, (5) forming a metal after forming an oxide film and a contact hole.

Description

트렌치 구조를 갖는 이피롬셀의 제조방법Method for producing epiromecelle having a trench structure

제 1 도는 종래 이피롬셀의 단면도.1 is a cross-sectional view of a conventional epiromel cell.

제 2 도는 종래 이피롬셀을 이용한 메모리 회로도.2 is a memory circuit diagram using a conventional epirom cell.

제 3 도는 본 발명의 공정단면도.3 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : P/R1 substrate 2 P / R

3, 5, 9 : 산화막 4 : 트렌치3, 5, 9: oxide film 4: trench

5, 6, 7 : 폴리실리콘 6a : 플로팅 게이트5, 6, 7: polysilicon 6a: floating gate

8 : 셀렉트게이트 10 : 메탈8: select gate 10: metal

본 발명은 트렌치 구조를 갖는 이피롬(Electrical Programmable Read Only Memory)셀의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing an epitaxial (Electrical Programmable Read Only Memory) cell having a trench structure.

종래의 이피롬은 제 1 도에 도시된 바와같이 스택게이트를 이용한 것으로 기판(1)상에 셀렉트(Select)게이트(8)와 플로우딩(Floating)게이트(6a)등의 2개의 게이트로 구성되어 있으며 기판(1)과 게이트(6a)(8)사이에는 절연을 위한 산화막(11)이 형성되어 있다.As shown in FIG. 1, the conventional epipyrom is formed by using a stack gate, which is composed of two gates, such as a select gate 8 and a floating gate 6a, on the substrate 1. An oxide film 11 for insulation is formed between the substrate 1 and the gates 6a and 8.

상기와 같은 종래 이피롬에 있어서는 셀렉트게이트(8)와 드레인(12) 사이에 25V의 고전압을 인가하면 채널에서 발생된 전자가 약 1000Å의 산화막(11)을 통하여 플로우딩 게이트(6a)로 옮겨지게 되었다.In the conventional epipyrom as described above, when a high voltage of 25 V is applied between the select gate 8 and the drain 12, electrons generated in the channel are transferred to the floating gate 6a through the oxide film 11 of about 1000 kV. It became.

그리고 이 전자에 의해 채널은 더욱 포지티브가 되어 전도성이 떨어지게 되어 결국 축전된 플로팅게이트(6a)쪽의 드레쉬홀드(Threshold)전압이 축전되지 않은 플로딩게이트(6a)쪽의 드레쉬홀드 전압보다 높게 되어 정상적인 셀렉트 게이트 전압으로는 채널을 형성시키지 못하게 되었다.The electrons cause the channel to become more positive and thus become less conductive, so that the threshold voltage on the floating gate 6a side is higher than the threshold voltage on the floating gate 6a side. As a result, a channel cannot be formed with a normal select gate voltage.

따라서, 축전된 플로당게이트(6a)를 가진 셀에는 셀렉트게이트(8)에 Vcc(약 5V)가 가해져도 채널이 형성되지 않고 축전되지 않은 플로팅게이트(6a)는 셀렉트게이트(8)에 Vcc가 가해지면 채널이 형성된다.Therefore, even if Vcc (approximately 5V) is applied to the select gate 8 to the cell having the stored flow gate 6a, no channel is formed and the non-powered floating gate 6a has Vcc applied to the select gate 8. When applied, a channel is formed.

그러나, 상기와 같은 종래기술에 있어서는 프로그래밍을 하기위하여 게이트(13)와 드레인(12)에 약 25V의 고전압을 걸어주어야 하므로 채널에서 어밸런치브렉다운(Avalanche Breakdown)이 발생하여 제품에 이상이 발생하기 쉬우며, 스택게이트를 사용함으로써 게이트(13)와 드레인(12) 및 소오스(14)의 토포로지(Topology)가 나빠져 메탈라인의 굴곡으로 인한 크랙(Crack)이 발생하게 되는 결점이 있었다.However, according to the related art, a high voltage of about 25 V is applied to the gate 13 and the drain 12 in order to program, and thus an avalanche breakdown occurs in the channel, causing an abnormality in the product. Easy to use, there is a defect that the topology of the gate 13, the drain 12, and the source 14 is degraded by using the stack gate, so that cracks due to the bending of the metal line are generated.

본 발명은 이와같은 종래의 결점을 해결하기 위한 것으로 기판에 트렌치를 형성하고 이 트렌치내에 게이트 부분을 형성하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional drawback, and an object thereof is to form a trench in a substrate and form a gate portion in the trench.

이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제 3 도에 의하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to FIG. 3.

먼저(a)와 같이 기판(1)위에 P/R(2)을 형성하여 선택적 식각을 하고 소오스와 드레인을 형성하기 위해 고에너지로 이온을 주입한다. 다음에 (b)와 같이 산화막(3)을 형성하고 소오스와 드레인을 제외한 부분을 식각하여 오픈시킨다.First, as shown in (a), P / R (2) is formed on the substrate 1 to selectively etch and implant ions with high energy to form a source and a drain. Next, as shown in (b), the oxide film 3 is formed, and portions other than the source and the drain are etched and opened.

그리고 (c)와 같이 트렌치(4)를 형성하고 (d)와 같이 채널형식을 위해 Bol온을 주입한다. 이어서 (e)와 같이 플로팅게이트를 형성하기 위해 산화막(5)을 형성하고 (f)와 같이 폴리실리콘(6)을 형성한 후 (g)와 같이 식각하여 트렌치내에만 폴리실리콘(6)이 남게하므로 플로팅게이트(6a)를 형성한다.Then, as shown in (c), the trench 4 is formed, and as shown in (d), Bol-on is injected for the channel type. Subsequently, an oxide film 5 is formed to form a floating gate as shown in (e), a polysilicon 6 is formed as shown in (f), and then etched as shown in (g) to leave polysilicon 6 only in the trench. Therefore, the floating gate 6a is formed.

다음에 (h)와 같이 셀렉트게이트를 형성하기 위하여 산화막(7)을 형성하고 (i)와 같이 이 산화막(7)위에 폴리실리콘을 형성하여 식각하므로 셀렉트게이트(8)를 형성한다.Next, an oxide film 7 is formed to form a select gate as shown in (h), and polysilicon is formed on the oxide film 7 and etched as shown in (i) to form a select gate 8.

이후 (j)와 같이 산화막(9)을 형성하고 콘택을 오픈시킨 상태에서 메탈(10)을 입혀 이피롬셀을 완성한다. 이상에서 설명한 바와같은 본 발명에 의하면 기존의 스택게이트 대신 트렌치게이트를 형성하여 게이트와 소오스 및 드레인 사이의 높은 차를 없앰으로 토포로지를 개선할 수 있으며, 게이트와 소오스가 트렌치게이트 측면에 형성되어 있어 기존과 같이 약 25V를 셀렉트게이트(8)와 드레인사이에 인가하여 채널에서의 전자이동을 만들지 않아도 더 낮은 전압으로 플로팅게이트(6a)에 축전이 가능한 장점을 갖는다.Thereafter, the oxide film 9 is formed as shown in (j), and the epitaxial cells are completed by coating the metal 10 in a state in which the contact is opened. According to the present invention as described above, it is possible to improve the topology by removing the high difference between the gate, the source and the drain by forming the trench gate instead of the conventional stack gate, and the gate and the source are formed on the trench gate side. As described above, about 25V is applied between the select gate 8 and the drain, thereby making it possible to accumulate the floating gate 6a at a lower voltage without making electron movement in the channel.

Claims (2)

기판위에 P/R을 선택적으로 형성하고 소오스와 드레인 형성을 위해 고에너지로 이온을 주입하는 공정과, 산화막을 형성하고 소오스와 드레인 이외의 부분만 식각하여 게이트 트렌치를 형성한후 채널형성을 위해 이온을 주입하는 공정과, 산화막을 형성하고 폴리실리콘을 형성한 후 에치하여 트렌치내에 플로팅게이트를 형성하는 공정과, 산화막을 형성하고 폴리실리콘을 형성한 후 에치하여 상기 플로팅 게이트위에 셀렉트게이트를 형성하는 공정과, 산화막을 형성하고 콘택홀 형성후 메탈을 형성하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 트렌치구조를 갖는 이피롬셀의 제조방법.Selectively forming P / R on the substrate and implanting ions with high energy to form the source and drain, forming an oxide film, etching only portions other than the source and drain to form gate trenches, and then forming ions for channel formation. Implanting, forming an oxide film and forming polysilicon and then etching to form a floating gate in the trench, forming an oxide film and forming polysilicon and etching to form a select gate on the floating gate And a step of forming an oxide film, and then forming a metal after contact hole formation, in order. 제 1 항에 있어서, 소오스와 드레인이 트렌치내의 게이트 측면에 형성됨을 특징으로 하는 트렌치구조를 갖는 이피롬셀의 제조방법.The method of claim 1, wherein the source and the drain are formed on the gate side of the trench.
KR1019910000107A 1991-01-07 1991-01-07 Method of fabricating for eprom KR930008079B1 (en)

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KR930008079B1 true KR930008079B1 (en) 1993-08-25

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