KR20020058279A - Method for manufacturing a transistor for test pattern - Google Patents

Abstract

PURPOSE: A method for manufacturing transistors for a test pattern is provided to simplify manufacturing processes and to reduce resistance between a channel and a contact by forming a polysilicon layer under pads. CONSTITUTION: A gate oxide(45) and a gate electrode(47) having a hard mask(49) are sequentially formed on a semiconductor substrate(41). An LDD(Lightly Doped Drain) region(51) is formed in the semiconductor substrate. An insulating spacer(53) is formed at both sidewalls of the gate electrode(47). A conductive layer(55) is formed at a predetermined region as a body pad, a source pad and a drain pad. The conductive layer are etched-back by using the hard mask(49) as an etch stopper. An interlayer dielectric having contact holes for the pads is formed on the resultant structure.

Description

Method for manufacturing a transistor for test pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a test pattern transistor, and in particular, a source pad, a drain pad, and a body (Pad) to accurately measure operating characteristics of a MOS transistor including only a lightly doped drain (LDD) region. The present invention relates to a transistor for a test pattern and a method of manufacturing the same, forming a polycrystalline silicon layer under the pad to improve the economics of device manufacturing, device yield and reliability.

In general, a transistor for a test pattern is formed in a peripheral region to fabricate a transistor and measure and evaluate its characteristics.

In the test pattern transistor, the transistor included in the semiconductor device is evaluated by measuring the operation current, a threshold voltage, etc. of the transistor according to process conditions.

1 is a layout diagram illustrating a test pattern transistor according to a conventional example, and FIGS. 2A to 2E are cross-sectional views illustrating a method of manufacturing a transistor according to a conventional example on the line I-I of FIG. 1.

As shown in FIG. 1, the transistor for a test pattern according to the related art includes a gate electrode 17 positioned at a portion of the active region, a first source pad 33 positioned at both sides of the gate electrode 17, and a first transistor. It consists of a first drain pad 35 and a body pad 31 located on one side of the first source pad 33.

In the method of manufacturing a test pattern transistor according to a conventional example, as shown in FIG. 2A, an oxide film, a polycrystalline silicon layer, and a hard mask are formed on a p-type semiconductor substrate 11 having an element isolation layer 13 formed in an element isolation region. Hard mask) layer 19 and the first photosensitive film are formed sequentially.

And selectively exposing and developing the first photoresist film so as to remain only at the site where the gate electrode is to be formed, and then using the selectively exposed and developed first photoresist film as a mask, the hard mask layer 19, the polycrystalline silicon layer, and the oxide film After etching to form the gate oxide layer 15 and the gate electrode 17, the first photoresist layer is removed.

As shown in FIG. 2B, a second photoresist film is coated on the entire surface including the gate electrode 17, and the second photoresist film is selectively exposed and developed to remove only the portion where the transistor is to be formed.

In addition, a lightly doped drain (LDD) region 21 is formed by implanting and driving-in low-concentration n-type impurity ions onto the entire surface using the selectively exposed and developed second photoresist layer as a mask. The second photosensitive film is removed.

As shown in FIG. 2C, a nitride film is formed on the entire surface, and the nitride film is etched back to form a nitride film spacer 23 on the sidewall of the gate electrode 17.

As shown in FIG. 2D, a third photoresist film is applied to the entire surface, and the third photoresist film is selectively exposed and developed to be removed only to a body pad contact.

Thereafter, a high concentration of p-type impurity ions is implanted and drive-in using the selectively exposed and developed third photoresist film to form a p-type impurity region 27, and then the third photosensitive film is removed.

As shown in FIG. 2E, the interlayer insulating film 29 and the fourth photoresist film are sequentially formed on the entire surface, and the fourth photoresist film is removed only at a portion where the body pad contact, the first source pad contact, and the first drain pad contact are to be formed. And optionally exposure and development.

Then, the interlayer insulating layer 29 is selectively etched using the selectively exposed and developed fourth photoresist layer to form a contact hole, and then the fourth photoresist layer is removed.

Subsequently, a metal layer and a fifth photoresist film are sequentially formed on the entire surface, and the fifth photoresist film is selectively exposed and developed to be removed only at a portion where the body pad, the first source pad, and the first drain pad are to be formed.

The metal layer is selectively etched using the selectively exposed and developed fifth photoresist layer to form a body pad 31, a first source pad 33, and a first drain pad 35. Remove the photoresist.

3 is a layout diagram illustrating a test pattern transistor according to another conventional example, and FIGS. 4A to 4E are process cross-sectional views illustrating a method of manufacturing a transistor according to another conventional example on line II-II of FIG. 3.

According to another conventional example, a test pattern transistor includes a gate electrode 17 positioned at a portion of an active region, and the first source pad 33 on both sides of the gate electrode 17, as shown in FIG. 3. A body pad positioned on one side of the second source pad 33a and the second drain pad 35a and the second source pad 33a that is located closer to the gate electrode 17 than the first drain pad 35. 31).

According to another conventional method of manufacturing a transistor for a test pattern, as shown in FIG. 4A, an oxide film, a polycrystalline silicon layer, and a hard mask layer are formed on a p-type semiconductor substrate 11 having an element isolation layer 13 formed in an element isolation region. 19 and the first photosensitive film are formed sequentially.

And selectively exposing and developing the first photoresist film so as to remain only at the site where the gate electrode is to be formed, and then using the selectively exposed and developed first photoresist film as a mask, the hard mask layer 19, the polycrystalline silicon layer, and the oxide film After etching to form the gate oxide layer 15 and the gate electrode 17, the first photoresist layer is removed.

As shown in FIG. 4B, a second photoresist film is coated on the entire surface including the gate electrode 17, and the second photoresist film is selectively exposed and developed to remove only the portion where the transistor is to be formed.

After the LDD region 21 is formed by implanting and driving low concentration n-type impurity ions onto the entire surface using the selectively exposed and developed second photoresist film, the second photoresist film is removed.

As shown in FIG. 4C, a nitride film is formed on the entire surface, and the nitride film is etched back to form a nitride film spacer 23 on the sidewall of the gate electrode 17.

As shown in FIG. 4D, a third photoresist film is applied to the entire surface, and the third photoresist film is selectively exposed and developed to be removed only in the body pad contact.

Thereafter, a high concentration of p-type impurity ions is implanted and drive-in using the selectively exposed and developed third photoresist film to form a p-type impurity region 27, and then the third photosensitive film is removed.

As shown in FIG. 4E, the interlayer insulating film 29 and the fourth photoresist film are sequentially formed on the entire surface, and the fourth photoresist film is removed only at a portion where the body pad contact, the second source pad contact, and the second drain pad contact are to be formed. And optionally exposure and development.

Then, the interlayer insulating layer 29 is selectively etched using the selectively exposed and developed fourth photoresist layer to form a contact hole, and then the fourth photoresist layer is removed.

Subsequently, a metal layer and a fifth photoresist film are sequentially formed on the entire surface, and the fifth photoresist film is selectively exposed and developed to be removed only at a portion where the body pad, the second source pad, and the second drain pad are to be formed.

The metal layer is selectively etched using the selectively exposed and developed fifth photoresist layer to form a body pad 31, a second source pad 33a, and a second drain pad 35a. Remove the photoresist.

Here, the second source pad 33a and the second drain pad 35a may be wider than the first source pad 33 and the first drain pad 35 in the width of the gate electrode 17. That is, they are formed closer to the gate electrode 17 than the first source pad 33 and the first drain pad 35, and are separated from each other by the hard mask layer 19.

The conventional method for manufacturing a transistor for a test pattern has the following problems.

First, in a test pattern transistor of a DRAM cell forming a source / drain region using only the LDD region, since a high concentration source / drain region is not formed, the resistance between the channel and the contact is large and an error occurs when measuring the operating characteristics of the transistor.

Second, in the transistor for a test pattern of a DRAM cell formed closer to the gate electrode than the source pad and the drain pad of the first case and formed with a source pad and a drain pad separated from each other by a hard mask layer, the source pad or the drain Since the distance between the pad and the gate electrode is reduced, the resistance between the channel and the contact is prevented, but the alignment between the source pad or the drain pad and the gate electrode is difficult, resulting in an error when measuring the operating characteristics of the transistor, and the source pad or the drain. There is a need for a new mask for forming pads, which lowers the economics of device fabrication.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and thus a polycrystalline silicon layer is formed below the source pad, the drain pad, and the body pad, thereby simplifying the process and preventing a test pattern transistor from increasing in resistance between the channel and the contact. The purpose is to provide.

1 is a layout diagram illustrating a test pattern transistor according to a conventional example

2A to 2E are cross-sectional views illustrating a method of manufacturing a transistor according to a conventional example on the line I-I of FIG. 1.

3 is a layout diagram illustrating a test pattern transistor according to another conventional example.

4A to 4E are cross-sectional views illustrating a method of manufacturing a transistor according to another conventional example on a line II-II of FIG. 3.

5 is a layout diagram illustrating a test pattern transistor according to an exemplary embodiment of the present invention.

6A through 6E are cross-sectional views illustrating a method of manufacturing a test pattern transistor according to an exemplary embodiment of the present invention on a line III-III of FIG. 5.

<Description of Symbols for Main Parts of Drawings>

11, 41: semiconductor substrate 13, 43: device isolation film

15, 45: gate oxide film 17, 47: gate electrode

19, 49: hard mask layer 21, 51: LDD region

23, 53: nitride film spacer 55: second polycrystalline silicon layer

27: p-type impurity region 29, 57: interlayer insulating film

59: body pad 61: source pad

63: drain pad

In the method of manufacturing a test pattern transistor of the present invention, forming a word line having a hard mask layer on a semiconductor substrate of a first conductivity type comprises forming a LDD region of a second conductivity type in a surface of a semiconductor substrate on both sides of the word line. Forming an insulating layer spacer on the sidewalls of the word line, forming a conductive layer in a region defined as a body pad, a source pad, and a drain pad on the semiconductor substrate, and forming the hard mask layer as an etch endpoint. Etching the entire surface, forming an interlayer insulating film including a body pad contact hole, a source pad contact hole, and a drain pad contact hole formed on the conductive layer, and forming the contact hole and source for the body pad. Forming a body pad, a source pad and a drain pad in the pad contact hole and the drain pad contact hole, respectively And it characterized by including yirueojim.

A preferred embodiment of the method of manufacturing a test pattern transistor according to the present invention as described above will be described in detail with reference to the accompanying drawings.

5 is a layout diagram illustrating a test pattern transistor according to an exemplary embodiment of the present invention, and FIGS. 6A to 6E illustrate a method of manufacturing a test pattern transistor according to an exemplary embodiment of the present invention on line III-III of FIG. 5. It is a process cross section.

In the transistor for a test pattern according to an exemplary embodiment of the present invention, as shown in FIG. 5, a gate electrode 47 located at a portion of an active region, a source pad 61 located at both sides of the gate electrode 47, and a drain pad are provided. 63 and a body pad 59 positioned at one side of the source pad 61 and a second polycrystalline silicon layer positioned at lower portions of the body pad 59, the source pad 61, and the drain pad 63. It consists of 55.

In the method of manufacturing a test pattern transistor according to an exemplary embodiment of the present invention, as shown in FIG. 6A, an oxide film, a first polycrystalline silicon layer, and an oxide film are formed on a p-type semiconductor substrate 41 having an isolation layer 43 formed thereon. The hard mask layer 49 and the first photosensitive film are sequentially formed.

And selectively exposing and developing the first photoresist film so as to remain only at a portion where the gate electrode is to be formed, and then using the selectively exposed and developed first photoresist film as a mask, the hard mask layer 49, the first polycrystalline silicon layer, and After the oxide film is etched to form the gate oxide film 45 and the gate electrode 47, the first photosensitive film is removed.

As shown in FIG. 6B, a second photoresist film is coated on the entire surface including the gate electrode 47, and the second photoresist film is selectively exposed and developed to remove only the portion where the transistor is to be formed.

The LDD region 51 is formed by implanting and driving-in low concentration n-type impurity ions onto the entire surface using the selectively exposed and developed second photosensitive film as a mask, and then removing the second photosensitive film.

As shown in FIG. 6C, a nitride film is formed on the entire surface, and the nitride film is etched back to form a nitride film spacer 53 on the sidewall of the gate electrode 47.

As shown in FIG. 6D, a second polycrystalline silicon layer 55 doped with a high concentration of n-type impurities and a third photosensitive film (not shown) are sequentially formed on the entire surface.

And selectively exposing and developing the third photoresist film so as to remain only in a predetermined area of the body pad contact, the source pad contact, and the drain pad contact, respectively, and then, using the selectively exposed and developed third photoresist film as a mask, the second polycrystalline silicon. After the layer 55 is selectively etched, the third photoresist layer is removed.

Subsequently, the second polycrystalline silicon layer 55 is entirely etched using the chemical mechanical polishing method as the hard mask layer 49 as an etching end point.

Here, the pn diodes of the semiconductor substrate 41 and the second polycrystalline silicon layer 55 are generated at the site where the body pad is to be formed by the formation of the second polycrystalline silicon layer 55, and the voltage is used during the test. The pn diode is in forward operation to allow body testing.

In addition, an undoped polycrystalline silicon layer may be formed in place of the second polycrystalline silicon layer 55.

In this case, when the undoped polycrystalline silicon layer is formed, a high concentration of n-type impurity is ion-implanted into the polycrystalline silicon layer in a region defined as a source pad contact and a drain pad contact after performing the entire surface etching process. High concentrations of p-type impurities are ion implanted into the polycrystalline silicon layer in the predetermined region.

As shown in FIG. 6E, an interlayer insulating film 57 and a fourth photoresist film are sequentially formed on the front surface, and the fourth photoresist film is selectively removed so as to be removed only in a region predetermined as a body pad contact, a first source pad contact, and a first drain pad contact. Exposure and development.

Then, the interlayer insulating layer 57 is selectively etched using the selectively exposed and developed fourth photoresist layer to form a contact hole, and then the fourth photoresist layer is removed.

Subsequently, a metal layer and a fifth photoresist film are sequentially formed on the front surface, and the fifth photoresist film is selectively exposed and developed so as to be removed only in a predetermined area of the body pad, the source pad, and the drain pad.

The metal layer is selectively etched using the selectively exposed and developed fifth photoresist layer to form a body pad 59, a source pad 61, and a drain pad 63, and then the fifth photoresist layer is removed. .

In the method of manufacturing a test pattern transistor of the present invention, a polycrystalline silicon layer is formed under a source pad, a drain pad, and a body pad in order to accurately measure the operating characteristics of a MOS transistor having only an LDD region. It is effective in preventing the increase in resistance of the liver and improving the economics of device manufacturing and device yield and reliability.

Claims (3)

Forming a word line having a hard mask layer on the first conductive semiconductor substrate; Forming an LDD region of a second conductivity type in a surface of a semiconductor substrate on both sides of the word line; Forming an insulating film spacer on the sidewall of the word line; Forming a conductive layer on a region defined as a body pad, a source pad, and a drain pad on the semiconductor substrate; Etching the conductive layer through the hard mask layer as an etching endpoint; Forming an interlayer insulating film on the entire surface having a body pad contact hole, a source pad contact hole, and a drain pad contact hole formed on the conductive layer; And forming a body pad, a source pad, and a drain pad in the body pad contact hole, the source pad contact hole, and the drain pad contact hole, respectively. The method of claim 1, And the conductive layer is formed of a second polycrystalline silicon layer doped with a high concentration of n-type impurities under p-type semiconductor substrate conditions. The method of claim 1, Polycrystalline silicon in which the conductive layer is ion implanted with a high concentration of n-type impurity into a region defined as the source pad contact and a drain pad contact under a p-type semiconductor substrate, and a high concentration of p-type impurity is implanted into a region designated as the body pad contact. A method of manufacturing a transistor, characterized in that formed in layers.