KR20020048414A - RAID controller system and method with ATA emulation host interface - Google Patents

Abstract

The RAID storage device controller 70 provides a host interface 56 for interfacing the controller to a host system bus. The host interface is isolated from attached storage devices such as, for example, IDE disk drives, so that the actual attached drives are not limited to the number or interface protocol. Various device ports may be implemented, and various RAID strategies such as level 3 and level 5 may be used, for example. In all cases, the host interface provides a standard, uniform interface to the host, i.e., ATA interfaces 82, 84, and 86, and preferably provides a dual channel ATA interface. The host interface emulates an ATA single or dual channel interface, and emulates one or two attached IDE devices per channel regardless of the actual number of devices physically connected to the controller. Thus, five or seven IDE drives can be deployed to RAID level 5, without changing the standard BIOS in the PCI host device. Thus, the RAID controller is transparent to the standard dual channel ATA controller board.

Description

RAID controller system and method with AT emulation host interface

The first IBM PCs and compatible devices had only floppy disk drives for mass storage. Subsequent XT and AT models included adapters for the connection of 5.25 "fixed disks (non-removable) for mass data storage devices. These original adapters used read signals and pre-compensated write signals (pre- Most low-level control signals have been provided for drives that include data isolation circuits for compensated write signals, including incorporating these functions in the adapter avoided the duplication of a pair of drivers accessed only one at a time. The 5M bit read / write channel on the adapter has made it impossible to attach faster drivers as technology advances.

Moving the "real time" characteristics of the controller into the drive solved this problem. Integrated Drive Electronics or IED drives integrate all the controls and data channels needed to read or write the drive and transfer data between the local buffer and the media. Manufacturers may choose a data rate. A new interface, AT Attachment with Packet Interface Extension (ATA / ATAP1-4) (IBM AT Attachment Interface), has been defined for the connection of data storage devices to a host system. The first IDE interfaces consisted of address decoding and buffering between the ISA bus and the ATA cable connector. The interface protocol used programmed input and output instructions to access the registers of the IDE device. The data transfer scheme used input string and output string instructions of the host processor throttled at the transfer rates of the attached drives. These transmission rates amounted to 16 megabytes per second in the latest revision of the specification. This is the transfer rate between the buffer on the storage device and the memory on the ISA bus. The transmission rates between the medium and the buffer are lower.

With the advent of the PCI bus, Intel has released the PCI IDE Controller Specification (Revision 1.0, 3/4/94), which provides a standard mapping of existing ISA bus-based host interfaces to the PCI bus. The standard discloses a dual IDE channel controller. A pair of devices of master and slave could be attached to each of the channels. For data transfer, the device was still accessed as a PCI bus target.

Intel has also published the Programming Interface for Bus Master IDE Controller, Revision 1.0, 5/16/94. This document defines a standard for integrating DMA devices into IDE channels. The bus mastering interface allows the IDE channel to transfer data to or from the system memory as a bus master (PCI BUS Initiator) over the PCI bus. The peak transfer rate for a 32bit / 32MHz PCI bus is 133 megabytes per second.

The revision of the ATA specification defined a new transmission mode, Ultra DMA. Existing transmission rate improvements have been achieved by tightening the setup and maintaining the time requirements for data transmission on the cable. At 16 megabytes per second, the read transfer rate was greatly limited by round trips that issue read strobes, access data, and return data. The Ultra DMA protocol initially retained the electrical properties of all signals and cables and simply redefines the functions of the three signals to provide a new protocol. In this protocol, the strobe signal providing data timing is sent from the same end as the data, ie by the controller for writing and the device for reading. In this configuration, the transmission rate is limited only by the cable skew for a single transition of the cable. The first UDMA devices doubled the programmed IO transfer rates to 33 megabytes per second. Subsequent revisions multiplied the initial UDMA transfer rate to 66 megabytes per second, but required the use of 80 conductor ribbon cables with alternating signals and ground conductors. The current version supports transfer rates of 100 megabytes per second. Currently, the ATA parallel interface is being replaced with a high speed serial link, but first, the parallel speed increase may be made once more.

problem

A typical personal computer consists of a motherboard designed around a chipset that includes a processor, a DRAM interface, various input / output adapters, and a BIOS ROM. IO adapters generally include an IDE interface. Current versions of IDE controllers consist of a pair of IDE ports, each of which can interface with a pair of IDE storage devices. These devices typically include one or more IDE hard disks and CD ROM, DVD ROM or CD WORM drives. The basic input output system or BIOS is a program used to boot a PC and provide low level IO routines to the adapters on the motherboard. Virtually all of these PCs can be booted and run from an IDE hard disk using the motherboard BIOS.

Increasingly, personal computers are being deployed for server or workstation use in the small office / home office (SOHO) market. Historically, hard disks with a small computer system interface (SCSI) have provided some performance gains for applications with more requirements. Recently, however, in more than 85% of all drives manufactured as IDE drives, SCSI drives tend to be configured using the same media and read / write heads, with little or no performance gain and significantly increased cost. There is this. Another popular alternative is Redundant Array Of Inexpensive Disks (RAID) as proposed by Patterson (D. Patterson et al., "Case for Redundant Array of Low Cost Disks (RAID)", Univ.Cal. Report No. UCB / CSD87 / 391, December 1987). RAID systems focus on both reliability and performance aspects. First, reliability is achieved by storing data redundantly across two or more drives so that no data is lost if a single drive is damaged. Secondly, due to the aggregate performance of the array, improved performance is obtained over the performance of a single drive. Different sections of dually stored data may be read from both drives simultaneously. In addition, data may be written in strips across all available drives so that the aggregate transfer rate can be realized when the data is reread. RAID array controllers are described in more detail in the inventor's US Pat. No. 6,018,778.

Unfortunately, there are drawbacks to the many RAID solutions available. Local intelligence and the use of SCSI disk drives are a feature of a class of RAID solutions. This class exhibits high performance, although very expensive for both drives and controllers. Another popular RAID solution class is characterized by the lack of any local intelligence or buffering and the use of IDE drives. This is essentially a software solution. All the software needed to control the set of drives to maintain redundancy or to stripe data must all be run on the host system, which greatly increases the disk drive overhead on the system bus and the processor. Thus, the increased overhead yields the benefits of RAID at the expense of reduced system performance. All of these solutions share additional problems. These RAID controllers are not directly supported by the BIOS on the motherboard. Additional software drivers are needed. These drivers may vary depending on the functionality of the operating system, for example Windows, Windows NT, UNIX, LINUX, etc., which adds additional burden to controller manufacturers, OEMs, marketing groups and system integrators. Brings about.

Thus, there remains a need for a RAID storage controller that does not require special software to run on the host processor, but does not require additional software drives or changes to the BIOS. The RAID controller, which does not require any changes to the BIOS, "plug-and-play" with virtually any standard, off-the-shelf computer that implements an ATA compliant interface. Has the advantage of compatibility. The RAID controller is transparent to the host and can be used to place multiple storage devices (but not limited to four) in any combination of device interfaces, RAID mirroring without adding overhead to the host. ), Stripping and so on. Such a RAID controller provides RAID functionality to all PC users at a low cost and in a very simple installation.

Related Applications

This application is a sequential application claiming priority in US Provisional Application No. 60 / 156,001, filed September 22, 1999.

Technical field

The present invention relates to computer data storage device controllers, and more particularly to a RAID controller having a host interface that emulates ATA standard controllers and attached IDE devices.

1 is a simplified block diagram of a conventional ATA dual channel controller application showing physical and software / register views.

2A and 2B are simplified block diagrams of a RAID controller with ATA port emulation according to the present invention.

3 is a high level block diagram of a preferred commercial embodiment of a RAID controller with ATA port emulation.

4 illustrates in more detail an implementation of an ATA register file of the controller of FIG.

The present invention uses a standard IDE controller and IDE drive to realize a RAID controller that is compatible with all operating systems booted and run on a given PC motherboard. This achieves this compatibility by emulating a drive attached with a standard controller. For example, some systems may require a pair of drives in RAID 1, or may require a "mirror" configuration for reliability. When connected to the controller described in the present invention, the BIOS will be a single highly reliable drive. Also, the same system may require an array of three drives configured according to either RAID 3 or RAID 5 architecture. This provides twice the transfer rate of any one of the three drives with high reliability. In addition, in the present invention, the array of these three drives will appear in the BIOS as a single drive having twice the capacity of any one of the three drives and exhibiting twice the transfer rate with high reliability. In some cases, RAID is transparent to existing drives in the BIOS.

The controller of the present invention emulates a standard two-channel IDE controller. Like a standard controller, it is logically connected to the PCI bus. It may be physically integrated on the motherboard, possibly within the motherboard chipset, or placed on a plug-in card in a PCI slot. This may emulate all four devices that may be attached to a standard controller. Each of these logic devices provides a possible interface to an array of physical devices attached to a controller. Although this embodiment provides ATA ports for attachment of physical devices, other forms of interfaces or combinations of interfaces may be used.

Additional objects and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments described with reference to the accompanying drawings.

The top of FIG. 1A illustrates a typical prior art application of an ATA controller 10 of a personal computer providing an interface between the system bus 12 and the storage devices 14. System bus 12 is a PCI bus. As long as it is logically attached to the PCI bus, the ATA controller is typically integrated within the motherboard chipset. In a given application, an additional or alternative controller may be pluggably connected to one of the PCI bus slots on the motherboard (not shown). The PCI bus provides a configuration mechanism in which unique addresses are assigned to each of the controllers. Conventional controller 10 provides two channels terminated in a pair of connectors 16, 18, identified as primary and secondary IDE connectors. Each of the channels supports a pair of storage devices that share a connector and a cable. For example, in FIG. 1, the secondary channel cable 19 is connected to the master storage device 20 and the slave storage device 22. Other pairs of drives are similarly connected to the primary channel cable 24. Thus, the two-channel controller 10 supports all four devices as shown in FIG.

The bottom of FIG. 1B shows the programming interface of the IDE controller and drives as seen from the PCI bus. The physical address for each block is well known in the art and is assigned through the PCI bus configuration space of the controller as described in the Intel PCI IDE controller specification document mentioned above. Another aforementioned Intel document, Programming Interface for Bus Master IDE Controller, describes a programming interface for a bus master IDE controller. Prior to standardization of this mechanism, storage device data is typically delivered via programmed I / O where the loads and stores needed for data transfer are executed by the system processor. Although the programmed I / O mechanism is still supported, the bus master interface allows the ATA controller to transfer data through direct access of system memory, ie DMA. The bus master IDE controller document defines a 16-byte block of registers supporting a pair of bus master controllers, one of which is for the primary ATA channel and one for the secondary ATA channel. This register block is physically part of the controller. It is shown to be divided into two parts 30, 32 which are associated with each channel one by one.

The ATA specification defines a programming interface for storage devices. This interface consists of two register blocks, namely a command block and a control block. An instruction block is an eight-byte block of byte-wide registers. The control block is a 4-byte block of byte-width registers. All details for implementing these registers are disclosed in the ATA specification.

The right side of FIG. 1 shows four sets of command and control register blocks, with one set corresponding to each of four attached storage devices. For example, a set of register blocks 36 consists of an instruction block 38 and a corresponding control block 40. These registers are the physical part of the corresponding storage devices shown in the upper half of FIG. Thus, register set 36 (primary channel) is located in master storage device 25. If no storage device is attached, the command and control register blocks will not appear in the programming interface.

The ATA specification also defines the protocols supported by storage devices. In general, the access instruction and all related parameters are loaded into registers of the instruction block. The storage device then executes the command. For device recording, the record data is first requested. For programmed I / O operations, the host processor reads data from system memory and writes to a buffer in a device (not shown) using a portion of the instruction block as a 16-bit window in the buffer. For bus master DMA operation, the ATA controller accesses data directly from system memory based on the structure of the bus master controller register block for that channel. The storage device then accesses a storage medium that transfers data between the medium and its local buffer. For media reading, the data in the local buffer is then transferred to system memory using either bus master DMA or programmed I / O as described above. Finally, the storage device informs the host system of the completion through the ATA controller through polling of the status register or by interrupt.

When powered on, personal computers execute code that is physically stored on the motherboard in nonvolatile memory. This basic input / output system or BIOS code loads the personal computer's operating system from an ATA storage device attached to the ATA controller and provides low-level I / O system drivers for such storage devices.

The present invention emulates the ATA controller shown in FIG. 1 and described above and is fully compatible at the programming level. Referring to FIG. 2, FIG. 2A is a block diagram of a controller according to the present invention, which may be configured, for example, as a RAID controller. The left side of the controller block 50 is attached to the PCI bus instead of the standard dual channel ATA controller, emulating one to four attached ATA storage devices. The emulation of ATA storage devices, which will be described in more detail below, separates the host interface of the controller from the physical device interface, allowing for greater freedom in the number and type of device interfaces. For example, an application of the present invention may implement X SCSI ports and / or YATA ports, where X and Y are by no means limited to four logical drives present in the host system. 2 is an example implementation of N + 1 ATA ports numbered from 0 to N-1.

2B illustrates the programming interface of the present invention. Host interface 56 includes all register blocks visible from the PCI bus of the standard ATA controller, i.e. dual channel bus master controller block 58, 60 and four sets of command and control register blocks 62, 64, 66. , 68). Host interface block 56 emulates the registers of the ATA controller and ATA storage devices to the level required to support the ATA specification protocols.

Block 70 of FIG. 2B shows the main components of controller block 50. In addition to the host interface block 56, the controller 70 includes a RAM buffer cache 72, a DMA channel 74 and a processor 80, as described below. The controller block 70 further includes a plurality of ATA port interfaces, such as, for example, the interfaces 82, 84, 86. Each ATA port interface provides standard interface access to IDE-type storage devices such as disk drives. As described above, each storage device is equipped with an instruction and control register block. These are shown, for example, as command register block 90 and control block 92, all of which are associated with a single device, i.e., the master drive, which is connected to the ATA port interface 82, standard connector It is connected to the cable 96. The controller block 70 can be configured to include any number of ATA ports while still providing a standard dual channel controller interface 56 on the host PCI bus 12.

A detailed block diagram of a preferred embodiment of the present invention is shown in FIG. The system is implemented as an Application Specific Integrated Circuit (ASIC) in a 0.18 micron COMS process. The device is logically divided into four modules, each of which has an associated port to the outside of the device.

The host interface 100 is installed around the PCI core 104 from indium silicon. The CS6464AF is a soft-core (a synthesized Verilog source for certain applications) that supports both 32-bit and 64-bit PCI buses at 33 MHz or 66 MHz PCI bus clock rates. The core supports both master and target operations. Target portion 106 provides access to the ATA compatibility register files described above. The master function 108 is used to emulate the bus master DMA portion of the ATA controller. The PCI core includes a configuration space that emulates the configuration space 110 of the dual ported ATA controller.

DRAM interface block 120 supports SDRAM 122 that is externally connected. A 64-bit wide, 100 MHz single data rate port 124 supports a peak transfer rate of 800 megabytes per second. Locally, the DRAM interface is accessed to or from the PCI bus via the host interface 100, to or from disk drives via the drive interface 130, and by the local processor of the processor block 150. Is shared by.

Driver interface block 130 provides five ATA ports (eg, 134), each of which may support master and slave drives. Each port supports programmed input / output (PIO) at transfer rates up to 16 megabytes per second, while Ultra DMA transmits at transfer rates up to 100 megabytes per second.

A processor block is installed around the EZ4102 TinyRISC core 160 from the LSI logic. This processor is a variant of the MIPS processor. At power up, the processor loads code from external flash memory that is accessed through expansion bus port 166. This code is sent to the SRAM block 170 in the processor block. The processor 160 configures each of the other modules and may access PCI bus, SDRAM or ATA drives through these modules. In general, system transfer rates are improved by not requiring a processor to process the data. The processor coordinates data movement between the DSRAM and the drive by configuring the DMA engines 136, 146 to load or unload the FIFO 148 between them in these blocks. In the same way, the DMA engines 172, 102 of the DRAM interface and the host interface are configured to load or unload the FIFO 174 between these blocks to coordinate the transfers between the PCI bus targets and the SDRAM.

4 shows details of the ATA register file implementation. The registers are all dual ported and may be accessed from the PCI bus by the host system or local processor 160. As can be seen from the PCI bus, each ATA channel has two registers of blocks associated with it. Instruction block 208 is an 8-byte range of byte width registers. Control block 210 is a 4-byte range in which only a single location is used. As mentioned above, a single ATA port may be used to access a pair of devices attached to a common cable. Each device has its own command and control register blocks. The devices are physically configured to have jumpers to designate one as a master and the other as a slave. A particular device is selected for access by writing a byte of data to the device head register at address offset 6 of the instruction block. If bit 4 is selected, the slave device is selected and the master is deselected for subsequent operations. If the same register is written with bit 4 cleared, the master device will be selected and the slave will be deselected. In order to emulate this operation in the present invention, both master and slave register sets are implemented. Additionally, a single bit slave register 230 is provided to write the most recent bit 4 write to the device head register. The slave register controls read multiplexing and write address decoding from the PCI bus so that the appropriate pair of register blocks are accessed based on the most recent device selection.

Upon power up or subsequent reset, the ATA devices are initially busy. The busy state may be detected by reading the status register at address offset 7 of the instruction block, or by reading the surrogate status register block of the control block. While the device is busy, none of the other registers may be accessed. In order to emulate this operation in the present invention, a single bit busy register 232 is provided. This register is set by reset from the PCI bus, by writing to the soft reset bit of the device control register of the control block, or when the command register is written to address offset 7 of the command register block. The local processor may clear the busy register.

Each ATA device may request an interrupt request from the host system when interrupts are enabled in the device. To emulate this operation, single bit interrupt request 234 and interrupt enable 236 registers are provided to both master and slave devices. Interrupt enable is controlled through the device control register of each device. Each device may request an interrupt request from the host system to send data or to return completion status. In the present invention, the interrupt request may be set or cleared by the local processor. In addition, the interrupt request is cleared by reading the device's status register (but not the surrogate status register) as described in the protocols of the ATA specification. Interrupt request and interrupt enable states for master and slave devices are maintained independently so that proper operation is maintained when the host changes device selection.

Command and control register files for the master and slave devices, and slave, busy and interrupt "side effects" are all duplicated for the secondary channel. Command and control register file blocks for all four devices are all linearly mapped to the address space of the local processor.

The shared dual channel bus master control block 250 may be accessed from the PCI bus or by a local processor.

According to the ATA protocol, the device is selected and all the necessary parameters for a given command are loaded into the command register file, and then the command itself is loaded into the register at offset 7. As mentioned above, this sets the channel busy. Busy's rising edge causes an interrupt to the local processor, which responds by interpreting the command and its parameters. Most instructions are remapped to accesses of the attached physical device array. These accesses can be used to implement any of the common RAID protocols, including but not limited to RAID levels 0, 1, 3, and 5. The local processor has the option to read more data than requested. Additional data is SDRAM cached as a predecessor of subsequent reads. The local processor may be arranged to transfer data between the host system and the SDRAM using either programmed IO or DMA as requested by the instruction.

Briefly summarized, the invention includes a RAID storage device controller that provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from attached storage devices that are, for example, IDE disk drives, so the actual attached drives are not limited in number or interface protocol. Various device ports may be implemented, and various RAID strategies may be used, for example, level 3 and level 5. In all cases, the host interface provides a standard uniform interface to the host, that is, an ATA interface, and preferably a dual channel ATA interface. The host interface emulates an ATA single or dual channel interface and emulates one or two attached IDE devices per channel regardless of the number of actual devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in a RAID level 5 protocol without changing the standard BIOS of the PCI host machine. Thus, the RAID controller is transparent to the standard dual channel ATA controller board.

It will be apparent to those skilled in the art that various changes may be made in the details of the embodiments of the invention described above without departing from the background principles of the invention. Accordingly, the scope of the invention should be determined only by the claims that follow.

Claims (20)

In the storage device controller: A host interface for interfacing the controller to a host system bus, emulating a standard IDE channel, and also for emulating an IDE device as connected to an IDE channel; And At least one physical interface for connecting the storage device controller to a physical storage device. The method of claim 1, At least one physical interface implements an ATA port for connecting an ATA-compatible storage device to the controller. The method of claim 1, The host interface emulates at least a primary channel and a secondary channel. The method of claim 3, wherein The host interface emulates a single IDE device attached to each of the primary and secondary channels. The method of claim 3, wherein Said host interface emulates both a master IDE storage device and a slave IDE storage device, said master and slave IDE storage devices being attached to one of said primary and secondary channels. The method of claim 3, wherein And means for emulating a bus master DMA controller of a standard dual ported IDE controller. The method of claim 1, The host interface emulates a single IDE device attached to the IDE channel. The method of claim 1, The host interface emulates both a master IDE storage device and a slave IDE storage device attached to the IDE channel. The method of claim 1, And means for emulating a bus master DMA controller of a standard dual ported IDE controller. For a RAID storage device controller: A host interface for interfacing the controller to a host system bus and emulating at least one ATA controller channel; At least two physical interfaces for connecting the storage device controller to a plurality of storage devices; And A local processor mounted to the controller for controlling physical storage device access operations, The host interface further emulates at least one IDE device as connected to an emulated ATA controller channel by implementing IDE-compliant command and control register blocks. The method of claim 10, And means for emulating a bus master DMA controller of a standard dual ported IDE controller. The method of claim 10, A buffer memory for buffering data transfers between the host system bus and the connected storage devices; And And a DMA engine arranged to transfer data between the host interface and the buffer memory. The method of claim 12, And a DMA engine arranged to transfer data between the buffer memory and the port interfaces. The method of claim 10, And the host interface emulates both a primary ATA channel and a secondary ATA channel. The method of claim 14, And the host interface emulates a single IDE device attached to each of the primary and secondary channels. The method of claim 14, And the host interface emulates both a master IDE storage device and a slave IDE storage device attached to at least one of the primary and secondary channels. The method of claim 10, The host interface emulates both a master IDE device and a slave IDE device connected to the IDE channel. The method of claim 10, And the host interface emulates a single IDE device attached to the IDE channel. The method of claim 10, And the host interface emulates both a master IDE storage device and a slave IDE storage device attached to the IDE channel. To interface a RAID storage device controller to a PCI bus host without modifying existing host BIOS software: Emulating, at the controller, an ATA controller interfaced to the host; At the controller, further emulating an IDE storage device as if connected to the ATA controller; Providing at least two physical port interfaces for connecting a physical storage device to the controller; And The physical storage device such that the storage device controller appears to the host as an IDE device connected via an ATA interface, regardless of the actual number of physical storage devices and interface types actually connected to the physical port interfaces of the controller. Disconnecting the host interface of the controller from the PCI bus host.