CN100447731C

CN100447731C - Redundant storage virtualization computer system

Info

Publication number: CN100447731C
Application number: CNB2006100036494A
Authority: CN
Inventors: 周德成; 黄威舜
Original assignee: INFORTREND Inc
Current assignee: INFORTREND Inc; Infortrend Technology Inc
Priority date: 2005-01-13
Filing date: 2006-01-09
Publication date: 2008-12-31
Anticipated expiration: 2026-01-09
Also published as: CN1804778A

Abstract

A redundant storage virtualization computer system is provided. The redundant storage virtualization computer system comprises a host entity for issuing an IO request, a redundant storage virtualization controller set coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage space to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller set. The redundant storage virtualization controller set comprises a first and a second storage virtualization controller both coupled to the host entity, the storage virtualization controllers communicate therebetween via a PCI-Express interconnect. In the redundant storage virtualization controller set, a storage virtualization controller will take over the functionality originally performed by the alternate storage virtualization controller when the alternate storage virtualization controller is not on line.

Description

Redundant storage virtualization computer system

Technical field

The present invention relates to a kind of redundant storage virtualization computer system (redundant storagevirtualization computer system), particularly a kind of local bus (local bus) that utilizes is as the redundant storage virtualization computer system that links between two storage virtualization controllers.

Background technology

So-called Storage Virtualization (storage virtualization) is a kind of technology with the entity stores space virtualization, it is with physical storage devices (PSD, physical storage devices) different sections are combined into the logical memory bank (logical storage entity) that can use for a host computer system access-be called " logical medium unit " (LMU, logical media unit) at this.This technology is mainly used in disk array (RAID) Storage Virtualization, through the technology of disk array thus, less physical storage devices can be combined into that capacity is big, fault tolerant, dynamical logical medium unit.

The fundamental purpose of storage virtualization controller (SVC, storage virtualization controller) is the visible logical medium of combination reflection (map) the formation one host computer system unit with each section of entity stores medium.Going into (IO) request by the output that this host computer system is sent can be earlier by analysis and decipher after receiving, and the output that relevant operation and data can be compiled into physical storage devices goes into to ask.This process can be indirectly, for example (as: write-back (write-back)) got, postpones in utilization soon, usefulness and other operating characteristic are strengthened in expection (anticipate) (as: reading (read-ahead) earlier), the operations such as (group) of trooping, thus a main frame to export into request might not be directly to export into request corresponding to physical storage devices in man-to-man mode.

Outside (or can be described as stand alone type (stand-alone)) storage virtualization controller is a kind of storage virtualization controller that is connected in host computer system via output/input interface, and it can be connected to the device that is positioned at the host computer system outside, generally speaking, the external storage virtualization controller normally is independent of main frame and operates.

Even with a pair of storage virtualization controller be configured to a redundant right mainspring be for break down at single storage virtualization controller or the situation that lost efficacy under, main frame still can interruptedly not carried out data access work continuously, this be can utilize in these storage virtualization controllers add a function so that one of them controller generation obstacle or fully under the situation of anergy another controller can take over its work and realize.

The configuration that the redundant storage virtualization controller is right be divided into two classes, the first kind is active-standby (active-standby), in this pattern, one of them storage virtualization controller (being commonly referred to as main storage virtualization controller) is exported into request all of all the logical medium unit in the Storage Virtualization subsystem and is presented, management and processing, and another storage virtualization controller (generally being called less important storage virtualization controller) will only be to be ready (stand by), and when main storage virtualization controller generation obstacle or anergy, take over main storage virtualization controller at any time.Second kind is active-aggressive mode (active-active), and in this pattern, these two storage virtualization controllers are gone into request to the output of the various logic media units in this Storage Virtualization subsystem simultaneously and presented, manage and handle.In active-aggressive mode, above-mentioned two storage virtualization controllers are all prepared to hinder (malfunction) for some reason and situation lower linking tube the other side of causing taking place obstacle or anergy at another storage virtualization controller always.Initiatively-aggressive mode, usefulness preferably is provided usually, because the resource of two storage virtualization controller (for example: central processing unit (CPU, central processing unit) time, internal bus frequency range ... etc.) compare the more output of can loading with single storage virtualization controller and go into the request service.

No matter be active-passive pattern or active-aggressive mode so, a basic function of redundant storage virtualization computer system is exactly when a storage virtualization controller situation occurred, another storage virtualization controller is taken over the work of the storage virtualization controller of (Take Over) situation occurred, for example: continue to finish the data in the access direct access storage device.Therefore want energy construction redundant storage virtualization computer system, at first must set up communication channel (ICC between a controller between its storage virtualization controller, inter-controller communications channel), be able to transmission information by this communication channel; Moreover, each storage virtualization controller also must be known the present job information of its companion's storage virtualization controller at any time, that is to say that its data almost must be synchronous and consistent between two controllers, so could when its companion's situation occurred, be taken over its work and realize the effect of redundancy.

And for setting up this part of communication channel between controller, generally be to adopt fiber channel arbitration cycles (FC-AL) or small computer system interface (SCSI at present, parallel small computer systeminterface) or the sequence advanced technology access interface (SATA, serial advanced technologyattachment) communication link such as, the principal element that adopts these bindings are to be that these link the long distance of the support that is had and can external cable and be beneficial to characteristic such as online between two autonomous devices.

See also Fig. 1, mainly show the calcspar of the storage virtualization controller of a kind of existing redundant storage virtualization system.Wherein, be to have a redundant manipulator communication (RCC, redundant controller communication) to link controller 136 in first storage virtualization controller 100, in order to the communication channel ICC between the foundation and second storage virtualization controller 100 '.

Because two controllers 100, communication channel ICC between 100 ' adopts fiber channel arbitration cycles (FC-AL) or communication link such as SCSI or SATA, different with the local bus (local bus) that circuit adopted in the controller, therefore, in these controllers, be bound to such an extent that be provided with one and be connected controller 136 with the RCC of this ICC outside binding interface or buffering as the conversion internal bus at communication channel (ICC) two ends between this controller, therefore make integrated circuit phase shape complexity, cost is also high.

Moreover, must know its companion's (another storage virtualization controller) present job information at any time and keep data sync and consistent problem between two external storage virtualization controllers solving each storage virtualization controller, in principle when the data of storage virtualization controller change to some extent, this variation must allow its companion know, two storage virtualization controllers almost can be kept synchronously, and then one during the storage virtualization controller situation occurred, and another storage virtualization controller is able to fully successfully take under the situation that does not almost have the data time difference.Therefore, data transmission system on communication channel ICC is quite frequent in some cases, the workload that may increase the weight of central processing unit in the storage virtualization controller undoubtedly, make its usefulness significantly be affected, therefore, the data transmission of how handling on the communication channel ICC also becomes a very important problem.

Summary of the invention

Fundamental purpose of the present invention is to provide a kind of redundant storage virtualization computer system of being simplified circuit, reducing cost.

The present invention discloses a kind of computer system, includes: a main frame is used for sending output and goes into request; One group of redundant storage virtualization controller, be to be used to carry out output go into operation and go into request with the output that the response main frame sends, it includes one first and one second storage virtualization controller that is coupled to main frame, between this first and second storage virtualization controller is to utilize a local bus (local bus) to communicate; And a group object memory storage, be coupled to these storage virtualization controllers, be to be used to provide this computer system stores space; Wherein, when the first storage virtualization controller situation occurred, second storage virtualization controller will automatically be taken over the original function of carrying out of first storage virtualization controller of situation occurred.

The present invention also discloses a kind of Storage Virtualization subsystem, include: one group of redundant storage virtualization controller, be to be used to carry out output go into operation and go into request with the output that responds a main frame and send, it includes one first and one second storage virtualization controller that is used for being coupled to main frame, between this first and second storage virtualization controller is to utilize a local bus (local bus) to communicate; And a group object memory storage, be coupled to these storage virtualization controllers, be to be used to provide the computer system stores space; Wherein, when the first storage virtualization controller situation occurred, then second storage virtualization controller will automatically be taken over the original function of carrying out of first storage virtualization controller of situation occurred.

According to the characteristic of embodiment, first and second storage virtualization controller is to be positioned at same circuit board in aforementioned computer system of the present invention or the Storage Virtualization subsystem.According to the characteristic of embodiment, to connect the mode of two storage virtualization controllers be to be external cable or backboard to local bus in aforementioned computer system of the present invention or the Storage Virtualization subsystem.

According to the characteristic of embodiment, local bus is that perimeter component links (PCI) bus, perimeter component links expansion (PCI-X) bus or perimeter component links quick (PCI-Express) bus in aforementioned computer system of the present invention or the Storage Virtualization subsystem.Characteristic according to embodiment, first and second storage virtualization controller respectively comprises a local bus interface in aforementioned computer system of the present invention or the Storage Virtualization subsystem, in order to set up the local bus communication channel between first and second storage virtualization controller.

Characteristic according to embodiment, aforesaid local bus interface is each positioned at a central processing unit chipset in aforementioned computer system of the present invention or the Storage Virtualization subsystem, and utilize at least one pin of two central processing unit chipsets to set make that wherein a local bus interface goes to change its operator scheme, so that set up online between the local bus interface of two storage virtualization controllers.

Characteristic according to embodiment, be to utilize software to fill in the register of an aforementioned wherein local bus interface and make this local bus interface go to change operator scheme in aforementioned computer system of the present invention or the Storage Virtualization subsystem, so that set up online between the local bus interface of these storage virtualization controllers.

According to the characteristic of embodiment, aforesaid local bus interface has more the feature that intersection links in aforementioned computer system of the present invention or the Storage Virtualization subsystem.

Characteristic according to embodiment, aforementioned wherein at least one local bus interface is carried out an automatic transfer machine system in aforementioned computer system of the present invention or the Storage Virtualization subsystem, be the operator scheme that the feature that utilize to intersect links is come translation interface, so that can set up online between first and second storage virtualization controller.

In addition, the present invention discloses a kind of storage virtualization controller, includes: a central processing circuit, and go into operation in order to execution output and go into request, and can utilize a local bus to be coupled to another storage virtualization controller with the output that responds a main frame; At least one I/O device links controller, is coupled to central processing circuit; At least one host side I/O device port, be arranged on aforementioned at least one I/O device link controller one in, be used for being coupled to main frame; At least one device end I/O device port, be arranged on aforementioned at least one I/O device link controller one in, be used for being coupled at least one physical storage devices; And an internal memory, be to be connected in central processing circuit, be to be used for cushioning the data that are transmitted between main frame and the physical storage devices by central processing circuit.

According to the characteristic of embodiment, in the aforementioned storage virtualization controller of the present invention, central processing circuit includes a central processing unit and a central processing unit chipset.This central processing unit chipset is in order to as the interface between this central processing unit and other electronic package, and include: one first local bus interface is to be coupled to this another storage virtualization controller via this local bus; One inner main bus is as the communication link between each main electronic package in this central processing unit chipset, in order to communications and liaison data-signal and control signal betwixt; One central processing unit interface is in order to be coupled to the main bus of this central processing unit and this inside, as the communication interface between this central processing unit and other electronic package; One Memory Controller Hub, in order to be coupled to the main bus of this internal memory and this inside, when this Memory Controller Hub receives the data that transmitted by the main bus in this inside, can be in this internal memory with these data storage, the data in this internal memory also are sent to the main bus in this inside by this Memory Controller Hub; And at least one second local bus interface, link controller and the main bus in this inside, the communication interface of the two in order to be coupled to this I/O device as this.

Characteristic according to embodiment, in the aforementioned storage virtualization controller of the present invention, aforesaid central processing unit chipset more comprises a register, this register belongs to first local bus interface, and a storage space is planned that definition writes as this central processing unit and transmits data and give the usefulness of another storage virtualization controller relevant information in the register.

According to the characteristic of embodiment, in the aforementioned storage virtualization controller of the present invention, aforementioned register is to be positioned among the register array that first local bus interface or is positioned at this central processing unit chipset.

According to the characteristic of embodiment, in the aforementioned storage virtualization controller of the present invention, aforesaid first local bus interface is that perimeter component links quick bus interface, perimeter component links expansion bus interface or perimeter component links bus interface.

Characteristic according to embodiment, in the aforementioned storage virtualization controller of the present invention, be to utilize the pin of aforementioned central processing unit chipset to set to make aforesaid first local bus interface go to change its operator scheme, so that corresponding with another storage virtualization controller and set up to each other online.

Characteristic according to embodiment, in the aforementioned storage virtualization controller of the present invention, be to utilize software to fill in a register of aforesaid first local bus interface and make the local bus interface of winning go to change operator scheme, so that corresponding with another storage virtualization controller and set up to each other online.

According to the characteristic of embodiment, in the aforementioned storage virtualization controller of the present invention, aforesaid first local bus interface has more the feature that intersection links.

Characteristic according to embodiment, in the aforementioned storage virtualization controller of the present invention, aforesaid first local bus interface is to carry out an automatic transfer machine system, be the operator scheme that the feature that utilize to intersect links is come translation interface, so that corresponding with another storage virtualization controller and set up to each other online.

The present invention further discloses a kind of method of setting up the communication channel between the storage virtualization controller, may further comprise the steps: storage virtualization controller is by comprising the information of the information of its operator scheme as the local bus interface transmission one of communication channel end between controller; In the storage virtualization controller at least one compares to judge whether to set up this operation mode information received and oneself operator scheme online when receiving the operation mode information of another this storage virtualization controller by local bus interface; If it is online that judgement can be set up, then set up the communication channel between two storage virtualization controllers, and if be judged as can't set up online, then at least one in the storage virtualization controller will be changed the operator scheme of local bus interface, so that corresponding, and then set up each other online with the operator scheme of the local bus interface of another this storage virtualization controller.

According to the characteristic of embodiment, local bus interface is the PCI-Express bus interface in the aforementioned method of the present invention.

Characteristic according to embodiment, local bus is to have the feature that intersection links in the aforementioned method of the present invention, and online for setting up when this comparison judged result, then storage virtualization controller is an operator scheme of utilizing this feature of intersecting binding to come the converts communications interface.

Characteristic according to embodiment, in the aforementioned method of the present invention, relatively judged result is for setting up in the performed step in online back, include one and bring mechanism together, so that the operator scheme of the communication interface at communication channel two ends corresponds to each other between these storage virtualization controllers, and set up online.

According to the characteristic of embodiment, aforementioned match mechanism is may further comprise the steps in the aforementioned method of the present invention: a selected at random timing critical parameters value then starts timing; If before the time reaches this critical value, receive the new operation mode information of the other side and show that it has changed operator scheme, then finish bring together and set up online; If when the time reaches this critical value, and do not receive the information that the other side's operator scheme has changed, then carry out this conversion operations mode step, and transmission one contains new operational mode status information to the other side after converting; And whether the operator scheme kenel that rejudges between the two is inequality, if inequality then brining together finished and set up online, if identical, then re-executes this match mechanism, brings together up to this and finishes.

Characteristic according to embodiment, more may further comprise the steps in the step of the performed conversion operations pattern of aforementioned match mechanism in the aforementioned method of the present invention: if when carrying out the conversion operations pattern, receive the operation mode information that the other side transmits, then end conversion and keep the operator scheme that originally set.

According to the characteristic of embodiment, be that relatively whether the other side's operator scheme is different with the preceding operator scheme of conversion own earlier before aforementioned termination is changed in the aforementioned method of the present invention, if just carry out steps such as this termination conversion, otherwise then continue to carry out conversion.

The present invention more one goes on foot a kind of method of carrying out data transmission in a computer system between storage virtualization controller of exposure again, and comprise following steps: the discrete data (scattered data) that the central processing unit of A. one storage virtualization controller is defeated by another storage virtualization controller according to the Data Transport Protocol form (data-transfer-protocol format) of a predefined to tendency to develop is set up at least one corresponding discrete gathering table (SG-list); B. the central processing unit address that will deposit discrete gathering table writes a register; And C. one local bus interface is according to reading discrete gathering table in address to an internal memory that writes in the register, and this discrete data is read in a discrete indicated address of aggregate data (scatter-gather data) in the foundation table to internal memory, and transmit this discrete data by a local bus and give another storage virtualization controller.

According to the characteristic of embodiment, local bus is that perimeter component links bus, perimeter component links expansion bus or perimeter component links quick bus in the aforementioned method of the present invention.

According to the characteristic of embodiment, after the address that central processing unit will be deposited discrete gathering table write register, register was that address information is sent to local bus interface, and triggers local bus interface and carry out this step C. in the aforementioned method of the present invention.

According to the characteristic of embodiment, in the aforementioned method of the present invention, central processing unit is that the address that will deposit discrete gathering table writes the storage space that is defined in the register as the particular address that writes the usefulness of depositing discrete gathering table address.

According to the characteristic of embodiment, the Data Transport Protocol form of discrete gathering table is to comprise following field in the aforementioned method of the present invention: data bulk field in the table, in order to the number of the discrete aggregate data that includes in the indicating gauge; The source origing address field (OAF) is failed its stored internal memory start address of discrete data in order to indicate every tendency to develop; Data length field is in order to indicate the length of the defeated discrete data of this every tendency to develop; And the target origing address field (OAF), in order to the destination address of indicating the transmitting discrete data to desire to deposit.

Characteristic according to embodiment, local bus interface is carried out and be may further comprise the steps among the step C. of aforementioned method of the present invention: read according to the control information that information that central processing unit sent will disperse to the internal memory in the gathering table header, according to the quantity of this discrete aggregate data down read in regular turn this quantity should discrete aggregate data control information; And according to the source origing address field (OAF) in each discrete data that is read and the indication of discrete data length field content, read this discrete data one by one, and every discrete data is transferred to another storage virtualization controller together with the target start address of this discrete data by local bus.

According to the characteristic of embodiment, the discrete data that local bus interface read in the aforementioned method of the present invention is to be temporary in an impact damper earlier, just transfers out together with the target start address thereafter.

According to the characteristic of embodiment, local bus interface can read discrete data in batches and transmit in response to the actual capacity of impact damper when reading and transmit discrete data in the aforementioned method of the present invention.

According to the characteristic of embodiment, comprise more in the aforementioned method of the present invention that the local bus interface of another storage virtualization controller receives discrete data and target start address, discrete data is stored in the step in the internal memory of destination address.

Characteristic according to embodiment, the Data Transport Protocol form of discrete gathering table more comprises a data direction field in the aforementioned method of the present invention, write or read operation in order to the indication execution, make local bus interface carry out corresponding accessing operation according to this field contents.

According to the characteristic of embodiment, in the aforementioned method of the present invention step C. after this local bus interface executes the step that reads discrete gathering table content, more include: the content according to the data direction field is carried out corresponding writing or read operation; If content is designated as the execution write operation, then carries out the aforementioned follow-up discrete gathering of foundation and show each field and read this discrete data and transmitting discrete data step to this another storage virtualization controller; If read operation is carried out in content indication, in the gathering table that then will disperse at least the part field contents be transferred to another storage virtualization controller by local bus; And after receiving this discrete data that another storage virtualization controller passes, deposit in the internal memory according to the corresponding target start address of discrete data again.

According to the characteristic of embodiment, the central processing unit chipset in the aforementioned method of the present invention is to give another storage virtualization controller with whole discrete gathering table content delivery.

Characteristic according to embodiment, after more comprising the discrete gathering table content of central processing unit chipset reception of another storage virtualization controller in the aforementioned method of the present invention, the indication of basis source origing address field (OAF) and data length field content, read every discrete data in regular turn, and the step of passback discrete data.

Characteristic according to embodiment, the Data Transport Protocol form of discrete gathering table more comprises following field in the aforementioned method of the present invention: first break field, whether in order to set in finishing this table after the listed data transmission, the central processing unit chipset need produce a look-at-me and notify central processing unit; And second break field, in order to set another storage virtualization controller after receiving discrete data and finishing corresponding operation, produce a look-at-me.

According to the characteristic of embodiment, the step C. in the aforementioned method of the present invention more includes: the central processing unit chipset sends the aforementioned second break field content to another storage virtualization controller; And the central processing unit chipset is in finishing discrete gathering table after the indicated data transmission, determines whether producing the action of a look-at-me to central processing unit according to the indication of first break field.

Characteristic according to embodiment, the Data Transport Protocol form of discrete gathering table more comprises next discrete field of assembling table address in the aforementioned method of the present invention, show stored memory address in order to deposit next discrete gathering, to indicate the central processing unit chipset after finishing the indicated data transmission of a discrete gathering table content, can be according to the discrete content of assembling the field of table address of this next one, read next discrete gathering table, and then interlock continues to handle.

Characteristic according to embodiment, include systems organization in the aforementioned method of the present invention and be set with the numerical value that an expression does not have next discrete gathering table existence, when the discrete content of assembling the table address field of this next one is this numerical value, show that promptly not having other discrete gathering table of existence needs interlock to handle.

According to the characteristic of embodiment, not have the numerical value that next discrete gathering table exists be to be 0 in aforesaid expression in the aforementioned method of the present invention.

According to the characteristic of embodiment, in the aforementioned method of the present invention, between steps A and B, more may further comprise the steps: check whether have the discrete gathering table that still has been untreated; If have, then carry out an interlock program, be that newly-established discrete gathering table and the aforementioned discrete gathering table that still has been untreated are produced interlock; And otherwise, execution in step B.

Characteristic according to embodiment, in the aforementioned method of the present invention, more may further comprise the steps before the interlock program carrying out: central processing unit sends out one and suspends request and give local bus interface, suspends the relevant action that transfers data to another storing virtual words controller in order to request; And receive this time-out when local bus interface and ask, be to carry out one to suspend mechanism, and after finishing time-out mechanism, reply a time-out approval and give central processing unit; And more may further comprise the steps after carrying out the interlock program: central processing unit notice local bus interface is removed halted state; And receive this releasing when local bus interface and notify, be the action that recovery is suspended, continue execution and handle the transmission data.

Characteristic according to embodiment; the aforesaid mechanism of suspending is finished for the discrete data that will handle and is transmitted the reading of suspending thereafter the back of each discrete data and transmit action in the aforementioned method of the present invention, and the processing that continues can be recovered when suspending in order to cancellation in the record breakpoint.

According to the characteristic of embodiment, the aforesaid mechanism of suspending is all finished for all discrete datas in the discrete data table that will handle and is transmitted the back and suspend the action that enters next discrete gathering table in the aforementioned method of the present invention.

According to the characteristic of embodiment, aforesaid interlock program is to comprise in the aforementioned method of the present invention: central processing unit reads the next discrete interior address date of table address field of assembling in the discrete gathering table that is stored in the register; Central processing unit judges according to the address in the register that is read whether local bus interface has the discrete gathering table that need continue and handle thereafter; If judged result is the discrete gathering table that need not to continue and handle, then changing the field contents of depositing next discrete gathering table address in the register is the start address of depositing newly-established first discrete gathering table; And if judged result is to have the discrete gathering table that must continue and handle, then change these discrete gathering tables that still have been untreated one deposit the next discrete field contents of assembling table address, change it into deposit this newly-established first discrete gathering table start address, and the next discrete table address field contents of assembling of depositing of last person in the newly-established discrete gathering table is set that to deposit the next gathering table address field contents that disperses consistent with before change not these of the aforementioned discrete gathering table that still has been untreated.According to the characteristic of embodiment, one of the aforementioned discrete gathering table that still has been untreated are meant when this local bus interface is suspended mechanism in the aforementioned method of the present invention, are stored in the discrete gathering table in the register.

According to the characteristic of embodiment, one of the aforementioned discrete gathering table that still has been untreated last discrete gathering table that is meant in the discrete gathering table of these interlocks that still have been untreated in the aforementioned method of the present invention.

Characteristic according to embodiment, comprise in the aforementioned method of the present invention that setting up a record has the table of all discrete gathering memory addresss that table is deposited, use the discrete gathering of still being untreated of depositing the field contents of next discrete gathering table address to show stored memory address for the change of central processing unit inquiry desire.Characteristic according to embodiment, central processing unit reads the discrete table address field contents of assembling of the next one that is stored in the discrete gathering table in this address according to the discrete table address information of assembling of the next one in the register that is read in the aforementioned method of the present invention, repeat it in regular turn, up to reading till central processing unit desire change deposits the discrete gathering table that still has been untreated of the next discrete field contents of assembling table address.

According to the characteristic of embodiment, when central processing unit need be transferred the discrete gathering table of having set up, be to carry out may further comprise the steps: check the discrete gathering table that has been untreated at present in the aforementioned method of the present invention; And judge whether its discrete gathering table that is intended to transfer belongs among the discrete gathering table that still has been untreated, if then transfer, otherwise, do not transfer.

According to the characteristic of embodiment, be to utilize central processing unit to read to be stored in the next discrete address date of assembling in the table address field in the interior discrete gathering table of register in the aforementioned method of the present invention, to know the present progress of data transmission.

Characteristic according to embodiment, aforementioned method of the present invention more may further comprise the steps before transferring finally: central processing unit sends out one and suspends request to local bus interface, suspends the relevant action that transfers data to another storage virtualization controller in order to request; And receive this time-out when local bus interface and ask, be to carry out one to suspend mechanism, and after finishing time-out mechanism, reply a time-out approval and give central processing unit; And more may further comprise the steps after transferring: central processing unit notice local bus interface is removed halted state; And receive this releasing when local bus interface and notify, be the action that recovery is suspended, continue execution and handle the transmission data.

The present invention further discloses another kind of method of carrying out data transmission in computer system between storage virtualization controller again again, comprises following steps: the central processing unit of a storage virtualization controller is to send a data transfer request to a central processing unit chipset; One first local bus interface in the central processing unit chipset is request to be changeed pass to another storage virtualization controller; And one second local bus interface in the central processing unit chipset of another storage virtualization controller is carried out corresponding processing after receiving request.

According to the characteristic of embodiment, local bus is that perimeter component links bus interface, perimeter component links expansion bus interface or perimeter component links quick bus interface in the aforementioned method of the present invention.

According to the characteristic of embodiment, the step that the central processing unit in the aforementioned method of the present invention sends data transfer request comprises: central processing unit transmits data transfer request to the central processing unit interface in the central processing unit chipset; The central processing unit interface is placed on the main bus in inside in the central processing unit chipset with data transfer request; And read this data transfer request by first local bus interface.

Characteristic according to embodiment, data transfer request is to comprise that one writes data in the aforementioned method of the present invention, an and target start address, this target start address is for writing the memory address that this writes data in order to indication, and this another storage virtualization controller carried out, and corresponding processing system comprises: according to this target start address this is write in the data write memory.

According to the characteristic of embodiment, the data transfer request content includes a discriminant information in the aforementioned method of the present invention, first local bus interface is differentiated and is read this data transfer request.

Characteristic according to embodiment, include in the aforementioned method of the present invention: storage virtualization controller is that the physical memory address of another storage virtualization controller of definition is represented with a virtual memory address form, make with its own physical memory address own and can not repeat, and this discriminant information is to be a memory address, and this memory address is also represented with this virtual memory address form.

According to the characteristic of embodiment, be to adopt the mode of the physical memory address of directly continuing own to remove the defining virtual memory address in the aforementioned method of the present invention.

According to the characteristic of embodiment, data transfer request is to comprise a memory address in the aforementioned method of the present invention, and this memory address is to represent with virtual memory address, with as this discriminant information.

According to the characteristic of embodiment, comprise in the aforementioned method of the present invention that the first or second local bus interface interface is to carry out the step that aforementioned memory address is converted to corresponding physical memory address.

According to the characteristic of embodiment, data transfer request is to comprise access instruction in the aforementioned method of the present invention, writes or read operation in order to indication.

According to the characteristic of embodiment, the corresponding processing that another storage virtualization controller carried out in the aforementioned method of the present invention is to comprise that second sets up local bus interface and separate access instruction in the read request to carry out indicated corresponding operation.

Characteristic according to embodiment, data transfer request is more to comprise a data length in the aforementioned method of the present invention, and a Data Source start address, and corresponding processing that another storage virtualization controller carries out is meant according to this Data Source start address and data length reading of data and data are returned to first local bus interface to the internal memory.

According to the characteristic of embodiment, more include in the aforementioned method of the present invention: receiving after the passback data of another storage virtualization controller it is to send central processing unit to when first local bus interface.

Description of drawings

Fig. 1 is the calcspar of a traditional redundant external storage virtualization controller.

Fig. 2 is the calcspar according to a storage virtualization computer system of the present invention.

Fig. 3 is the calcspar according to a storage virtualization controller of the present invention.

Fig. 4 is the calcspar of an embodiment of the central processing circuit shown in Fig. 3.

Fig. 5 is the calcspar of an embodiment of the central processing element group/coordination engine shown in Fig. 4.

Fig. 6 is the process flow diagram of a Storage Virtualization subsystem automatic transfer machine system.

Fig. 7 is a kind of process flow diagram of monolateral automatic transfer machine system.

Fig. 8 is the process flow diagram of storage virtualization controller end in the another kind of automatic transfer machine system.

Fig. 9 is foundation a kind of process flow diagram that carries out data transferring method of the present invention.

Figure 10 is a kind of scatter-gather sheet format.

Figure 11 carries out the hypothesis example that data transmit.

Figure 12 carries out the hypothesis example that data transmit for another.

Figure 13 is again a hypothesis example of carrying out the data transmission.

Figure 14 is another hypothesis example of carrying out the data transmission.

Figure 15 carries out the process flow diagram that data transmit for another kind of central processing unit.

Figure 16 is an embodiment process flow diagram of the insertion or the interlock program that continues among Figure 15.

Figure 17 is another embodiment process flow diagram of the insertion or the interlock program that continues among Figure 15.

Figure 18 is the process flow diagram of transmission small amount of data between a storage virtualization controller of the present invention.

Embodiment

Along with development in science and technology, local bus (local bus) links (PCI from perimeter component, peripheralcomponent interconnect) bus develops perimeter component and link to expand (PCI-X, peripheralcomponent interconnect extended) bus, and perimeter component links quick (PCI-Express) bus.

And being different from other local bus part, PCI-Express is, it has been broken through in the past local bus and can not or conditionally go up backguy in backboard (backplane), with and all restrictions such as the distance that can transmit of electrical specification is limited, the PCI-Express interface not only can externally be pulled line, carry out on-line communication in the cable mode, and its electrical specification also can make transmission range reach 7 meters far away.

See also Fig. 2, Fig. 2 is the block schematic diagram for one embodiment of the invention, and this system includes a main frame 10 and a Storage Virtualization subsystem 20 (SVS, redundant storagevirtualization subsystem).Storage Virtualization subsystem 20 include one group of storage virtualization controller (comprise first and second storage virtualization controller (SVC1, SVC2) 200,200 ', with a plurality of physical storage devices 420.Wherein storage virtualization controller 200, and 200 ' can be a disk array controller or a JBOD emulator.

Though only have a main frame 10 and a Storage Virtualization subsystem 20 to interconnect shown in Fig. 2, can connect a Storage Virtualization subsystem 20 with a plurality of main frames 10 during practical application, or a plurality of Storage Virtualization subsystems 20 of a main frame 10 connections, or a plurality of main frame 10 connects a plurality of Storage Virtualization subsystems 20.Main frame 10 can be a host computer, and as a server system, workstation, personal computer system or other correlation computer etc., and main frame 10 also can be another storage virtualization controller.

This Storage Virtualization subsystem is sent out structure, and two storage virtualization controllers 200 are provided with communication channel ICC between a controller between 200 ', be used for intercoursing information.And communication channel ICC is PCI-Express between this controller, in this enforcement profit, adopt the reason of PCI-Express mainly be PCI-Express its except that also can walk the backboard can external cable transmission and support than events of feature such as the defeated distances of teletransmission, therefore be comparatively suitable with regard to the design of adopting the external storage virtualization controller, when making one storage virtualization controller generation problem (as: trouble or failure), can send out storage virtualization controller in another normal operation still provides under the state of service, and this storage virtualization controller that problem takes place is keeped in repair or replaces.Right the present invention should not be subject to this, sends out design according to controller, and the local bus that circuit is adopted in all controllers is all applicable, for example: be positioned at the design of same circuit board with regard to two controllers, can adopt PCI or PCI-X etc.

In one embodiment, the 420 formation one physical storage devices arrays 400 capable of being combined of all physical storage devices in this Storage Virtualization subsystem 20.

Fig. 3 is for being connected to an embodiment calcspar of the storage virtualization controller 200,200 ' of main frame 10 and physical storage devices array 400 among the present invention.Herein, be to be example explanation with first storage virtualization controller (SVC1) 200, so in fact, second storage virtualization controller 200 ' also identical it.Among this embodiment, first storage virtualization controller (SVC1) 200 includes a host side I/O device and links controller 220, a central processing circuit (CPC, central processing circuit) 240, one internal memory 280 and device end I/O device binding controller 300.Though describe with the function square that separates herein, when practical application, part even whole function squares (functional block) all can be incorporated on the one chip.

The host side I/O device links controller 220 and is connected to main frame 10 and central processing circuit 240, be used as interface and buffering between first storage virtualization controller (SVC1) 200 and the main frame 10, it can receive the output transmitted by main frame 10 and go into request and related data, and with its conversion and/or video to central processing circuit 240.The host side I/O device links controller 220 can include the host side port that one or more is used for being coupled to main frame 10.Mentioned herein and the type of port can support fabric for: fiber channel and link (fibre channel supporting fabric), point-to-point binding, dissipating public loop links and/or dedicated circuit is linked to target pattern, operate in the small computer system interface arranged side by side (SCSI arranged side by side of target pattern, parallel small computer system interface), support internet SCSI (iSCSI, internet SCSI) agreement and operate in the Ethernet of target pattern, operate in the additional SCSI (SAS of sequence of target pattern, serial-attached SCSI), and the sequence advanced technology that operates in target pattern accesses interface (SATA, serial advancedt echnologyattachment).

It is between 400 of central processing circuit 240 and physical storage devices arrays that the device end I/O device links controller 300, is used as the interface and the buffering of 400 of storage virtualization controller 200 and physical storage devices arrays.The device end I/O device links controller 300 and receives the output of being imported into by central processing circuit 240 and goes into request and related data, and with its reflection and/or be sent to physical storage devices array 400.The device end I/O device links controller 300 can include the device end port that one or more is used for being coupled to physical storage devices array 400.Mentioned herein and the type of port be that the coupled system physical storage devices that adopts can be FC-AL, SCSI, the additional SCSI (SAS of sequence, serial-attached SCSI) and the sequence advanced technology access interface (SATA, serial advancedtechnology attachment).

Moreover, though be to be respectively equipped with corresponding I/O device with host side and device end to link controller 220,300 be example herein, but in another embodiment of the present invention, can only there be an I/O device to link controller, links in controller and make host side port that is coupled to main frame 10 and the device end port that is coupled to physical storage devices array 400 all be arranged on this I/O device.When central treatment circuit 240 receives the main frame that links controller 220 from the host side I/O device when exporting into request, central processing circuit 240 can be exported this into request and analyze, and carrying out certain operations exports into request to respond this, and, link controller 220 by first storage virtualization controller 200 via the host side I/O device and be sent to main frame 10 data and/or the report and/or the information of being asked.The output that main frame 10 is imported into is gone into after the request analysis, if what received is that the request of reading and one or more operation are performed when thinking response, central processing circuit 240 can be by inner or by obtaining the data of being asked in the internal memory 280 or by these two kinds of modes, and these data are sent to main frame 10.If the data of being asked can't obtain or not be present in internal memory 280 in inside, this request of reading will link controller 300 via the device end I/O device and be sent to physical storage devices array 400, these data of asking will be sent to internal memory 280 by physical storage devices array 400 then, link controller 220 via the host side I/O device more afterwards and be sent to main frame 10.When the request that writes (write request) of importing into when being conveyed to central processing circuit 240 by main frame 10, after one or more operation is analyzed and is carried out in the request that writes, central processing circuit 240 links controller 220 by the host side I/O device and receives the data of importing into from main frame 10, and it is stored in the internal memory 280.Operate both for synchronous or asynchronous device, data all are sent to physical storage devices array 400 via central processing circuit 240.When this writes request is a write-back request (writeback request), and output is gone into to finish report (IO complete report) and can be transferred into main frame 10 earlier, and then central processing circuit 240 just can be carried out actual write operation; And be one to write request (write through request) fully when this writes request, then export and go into to finish public lecture and just be transferred into main frame 10 after writing physical storage devices array 400 in that data are actual.Internal memory 280 is to be connected in central processing circuit 240, and it is as an impact damper, is used for cushioning the data that are transmitted between main frame 10 and the physical storage devices array 400 by central processing circuit 240.During practical application, internal memory 280 can be DRAM (Dynamic Random Access Memory) (DRAM, dynamic random access memory), or more particularly, this DRAM also can be SDRAM (Synchronous dynamic random access memory) (SDRAM, synchronous dynamic random access memory).

And in the present embodiment, be the central processing circuit (not shown) that the central processing circuit 240 of first storage virtualization controller (SVC1) 200 is directly connected to second storage virtualization controller (SVC2) 200 ', i.e. construction goes out the communication channel (ICC) between first storage virtualization controller (SVC1) 200 and second storage virtualization controller (SVC2) 200 '.

In addition, it is to be coupled to physical storage devices array 400 that the device end I/O device links controller 300, and physical storage devices array 400 also is coupled to second storage virtualization controller (SVC2) 200 '.

In this structure, second storage virtualization controller (SVC2) 200 ' can attach to first storage virtualization controller (SVC1) 200, and physical storage devices array 400 can be by 200 accesses of these two storage virtualization controllers.What is more, the control/data-signal that is sent by main frame 10 can send second storage virtualization controller (SVC2) 200 to or further send one second physical storage devices array (not shown) to from central processing circuit 240.

Please continue and consult Fig. 3, in the present embodiment, can be on central processing circuit 240 an attached casing management service circuit 360 (EMS circuitry, enclosure management servicecircuitry), management circuit as ccontaining physical storage devices array 400 casings, casing management service circuit 360 is used for controlling the power supply of this physical storage devices array and carries out other management, and LCD MODULE a 350 (liquid crystal display module, LCD module), be used for the mode of operation of display subsystem.Yet Storage Virtualization subsystem 20 also has other configuration mode, for example can decide according to the function design of various different products, and casing management service casing management service circuit 360 or this LCD module 350 are omitted, or casing management service casing management service circuit 360 is incorporated in the central processing circuit 240.

See also Fig. 4, embodiment for central processing circuit 240, wherein include cpu chip group/coordination engine 244 (CPU chipset/parity engine), one central processing unit 242 (CPU), one ROM (read-only memory), 246 (ROM, read only memory) and a non-volatile random access memory 248 (NVRAM, non-volatile random access memory).Wherein this CPU 242 can be, for example, and a Power PC CPU, and ROM 246 can be a flash memory, is used for storing basic input/output (BIOS) and/or other system program, and when start, carried out operation with control subsystem.NVRAM 248 is used for storing this physical storage devices array and exports relevant information into the operation executing state, when going into to take place before operation is not finished as yet undesired power-off in order to output, does check and uses.ROM 246, and NVRAM 248, and LCD module 350 and casing management service circuit 360 all are linked to cpu chip group/coordination engine 244 via an X-bus (X-bus).Again, this NVRAM 248 is optional item, can omit in another kind of configuration of the present invention and not establish.Though and cpu chip group/coordination engine 244 describes with the function square of integrating herein, when practical application, the cpu chip group can be separated with the coordination engine and is arranged on the different chips.

Please continue and consult Fig. 4, central processing unit 242 must just be able to couple mutually with other electronic package (as internal memory 280 etc.) by this cpu chip group/coordination engine 244.

And Fig. 5 promptly shows the embodiment of cpu chip group/coordination engine 244 among a present invention.Wherein cpu chip group/coordination engine 244 includes coordination engine 260, cpu i/f 910, Memory Controller Hub 920, perimeter component links quick (PCI Express) interface 930,932,934, X-Bus interface 940, transmission control protocol and Internet Protocol (TCP/IP, transmission control protocol/internetprotocol) direct memory access (DMA, direct memory access) 980, arbitrator (Arbiter) 982, internal local bus (IL, internal local) 990 and inner main (IM, internal main) bus 950, and wherein IM bus 950 is to be connected to coordination engine 260, cpu i/f 910, Memory Controller Hub 920, PCI-E interface 930,932, on 934, in order to communications and liaison data-signal and control signal betwixt.

Link data and the control signal that controller 220 sent by the host side I/O device and enter cpu chip group/coordination engine 244 via PCI-E interface 930.The transfer rate that wherein is linked to the PCI-E interface 930 of host side I/O device binding controller 220 can be, for example, and 1.5Gbit/sec.When PCI-E interface 930 has IM bus 950 (IM Bus), these data and control signal will be transferred into Memory Controller Hub 920 or cpu i/f 910.

Receive data and the control signal that transmits by IM bus 950 when cpu i/f 910, will be sent to CPU 242 is further processed, the line of communication that cpu i/f 910 and CPU are 242 then can be, and for example, 64-bit data line and 32-bit address wire are carried out.

Be to have one to remove error code generation circuit (ECC circuit in Memory Controller Hub 920, errorcorrection code circuit) (not shown), in order to produce an ECC sign indicating number, and the mode of its generation can be, for example, the data of 8-bit with mutual exclusion or (XOR) after the computing, are produced the ECC sign indicating number of a single position.Next, Memory Controller Hub 920 is stored in data and ECC sign indicating number in the internal memory 280.This internal memory 280 can be, for example, and SDRAM.And the data in the internal memory 280 also can be sent to IM bus 950.And Memory Controller Hub 920 can be designed to, when data when internal memory 280 is sent to IM bus 950, Memory Controller Hub 920 can be revised (1-bit auto-correction) and multidigit error detection functions such as (multi-bit error detecting) automatically to one of data fill order.

Coordination engine 260 can be carried out the same bit function of a particular disk array kenel in response to the indication of CPU 242.Certainly, under some certain conditions, such as RAID0, coordination engine 260 can be turned off and not carry out same bit function.

IL bus 990 (IL Bus) is to be connected in cpu i/f 910 and other low speed device interface.

Register array 984 (Reg.array) is to be used for the state of temporary cpu chip/coordination engine 244, and controls the streams data among the IM Bus 950.In addition, 986 of function squares of a pair of UART Universal Asynchronous Receiver Transmitter (UART, universal asynchronous receiver and transmitter) are as the external interface of cpu chip/coordination engine 244, and this interface specification is RS232.

This cpu chip group/coordination engine 244 then is to link controller 300 by PCI-E interface 932 with the device end I/O device to link.

TCP/IPDMA980 then checks the function of (checksum) calculating and dma operation in order to carry out sum total.Arbitrator 982 is then in order to arbitrate the right to use of IM bus 950.

And in the present embodiment, if will be when internal memory 280 transfers data to second storage virtualization controller 200 ', after then entering PCI-E interface 934 via IM bus 950, by a PCI-E communication channel, as: external cable (cable) or backboard (backplane), can be directly with second storage virtualization controller 200 ' in PCI-E interface 934 ' couple mutually, wherein need not be as the prior art need again by any intermediate conversion buffer interface (as: redundancy communication binding controller).

When practical application, PCI-E interface 930,932 replaceables are that perimeter component links expansion (PCI-X, peripheral component interconnect extended) interface, or link the replacement of (PCI) interface with perimeter component.

And when subsystem 20 started power supply, whether the cpu chip group of each storage virtualization controller can be understood the device that is external in this controller by its each PCI-E interface and correctly set up online why and.And between two devices if will utilize the PCI-E interface to set up the PCI-E transmission channel, then the physical layer pattern (PHY-mode) of the PCI-E interface that links to each other of this two devices must operate in downstream (down stream) pattern and upstream (up stream) pattern respectively, otherwise the two can't set up the online data transmission of carrying out.

Generally speaking, storage virtualization controller is a driving component, and therefore, the PHY-mode of its PCI-E interface is set at down stream.

But, as previously mentioned, two storage virtualization controller settings are to be unanimity, that is to say, for two storage virtualization controllers, it is set up between two controllers, and the PHY-mode of the PCI-E interface of communication channel ICC all is set to down stream between controller, and thus, two controllers can't successfully be set up online at all.Be head it off, in the present embodiment, proposed a kind of changing the mechanism and made wherein that a controller can transfer up stream to, can successfully set up online transmission data.

Seeing also Fig. 6, is the process flow diagram for a kind of Storage Virtualization subsystem automatic transfer machine system.Wherein this automatic transfer machine system is to be carried out by the PCI-E interface of cpu chip group in the storage virtualization controller.

At first, two storage virtualization controllers 200,200 ' all comprises the information of its PHY-mode information respectively by PCI-E interface 934 transmissions one at communication channel ICC two ends between controller, therefore the PCI-E interface 934 of this two storage virtualization controller 200,200 ' can be received the other side's PHY-mode information (step S810);

Relatively whether the PHY-mode of the two is different and can set up online (step S820);

When if comparative result shows that for the information of another storage virtualization controller its PHY-mode is identical with oneself PHY-mode, then will utilize the characteristic change PHY-mode of the cross link of PCI-Express, and bring the PHY-mode that makes the PCI-E interface at communication channel ICC two ends between first and second storage virtualization controller together, be to operate in down stream and up stream respectively and set up online (step S830 and step S840).

The aforesaid mode of brining together can be reached by only allowing wherein the PCI-E interface of an end can change PHY-mode, just, when information that the PCI-E interface received taking place show that the PHY-mode of the other end is identical with oneself, having only wherein, the PCI-E of an end can change its PHY-mode.

Suppose that aforementioned the monolateral conversion of permission is to set to be carried out by second storage virtualization controller.During group system start-up power supply, two storage virtualization controllers all comprise the information of its PHY-mode information respectively by the PCI-E interface transmission one at communication channel ICC two ends between controller, therefore, communication channel ICC will receive the PHY-mode information that is positioned at the first storage virtualization controller PCI-E interface in the PCI-E of second storage virtualization controller interface between controller.Please cooperate and consult Fig. 7, be the process flow diagram of the second storage virtualization controller end.

Receive the PHY-mode information of the first storage virtualization controller PCI-E when the PCI-E of second storage virtualization controller interface after, pass through the PHY-mode information that is received so that judge whether to set up online (step S410, S420);

If discovering the information of another storage virtualization controller in aforementioned determining program (step S420), the PCI-E interface of second storage virtualization controller shows when its PHY-mode is identical with oneself PHY-mode, the PHY-mode that then links its storage virtualization controller of characteristic change of (cross link) by the intersection of PCI-Express, and after conversion, send new PHY-mode information, and then enter and set up in-line procedures (step S440) to first storage virtualization controller (step S430).

The PCI-E interface of communication channel ICC end is then after transmission contains its PHY-mode and is set information such as down stream between the controller of first storage virtualization controller, promptly wait for up to the PCI-E interface that receives second storage virtualization controller transmit showing that by ICC its PHY-mode is the information of up stream, set up online between two controllers according to these information contents again.

Described before combining, this embodiment this storage virtualization controller centering when the PHY-mode that the communication channel two ends are arranged is identical, only have a storage virtualization controller can utilize cross-link to change its PHY-mode, an other storage virtualization controller can't carry out any start.That is, the design of this two storage virtualization controller is inequality among this embodiment, so the IC of the cpu chip group that the two adopted will be different.

That is, aforesaid way, this controller must match use, and is normally online so that communication channel ICC therebetween is able to.

But, under some environment or situation, can expect or require to form two right upright its software and hardwares of ICC communication interface that storage virtualization controller adopted of this storage virtualization controller and want consistent.At this, another kind of automatic transfer machine system is proposed, wherein the performed flow process of PCI-E interface of setting up ICC of two storage virtualization controllers is identical, enables in response to status, and Fig. 8 shows that promptly the performed a kind of reality of storage virtualization controller end PCI-E interface makes the scheme process flow diagram.

At first, when the PCI-E of storage virtualization controller interface receives the information of another connecting end, with the state (step S510) of resolving to understand this connecting end,

Then, relatively whether this connecting end PHY-mode and self identical (step S520) if different, then directly set up in-line procedures (step S530);

If the PHY-mode of the two is identical, then enters one and brings program S540 together;

(random) selected parameter T value (timing critical value) then starts timing at first at random, whether reaches this T value (step S542) to understand;

Thereafter, if the time for before reaching this T value, receive the new PHY-mode information of the other side and show that it has changed PHY-mode (step S544), then the end bring program together, enter and set up in-line procedures (step S530);

And when slowly not receiving the information that the other side PHY-mode has changed, and the time reaches the T value, as shown in FIG., whether step S546 judgement time t has reached the T value, if t＜T, the execution in step of then going back S544, otherwise, carry out a conversion PHY-mode program (step S548), be to utilize cross-link that PHY-mode is converted to another kenel by the kenel of original setting, as: originally then transferred upstream to or transferred up stream to down stream, and contained new PHY-mode status information to the other side in converting back transmission one for down stream;

, get back to step S520, determine that between the two PHY-mode kenel is whether inequality and it is online to set up,, then enter again and bring program S540 together if identical thereafter, this moment can be more again at random random number choose setup parameter T.

Wherein, after being finished, step S548 need go back to enter the reason of step S520 again, though be to be before carrying out conversion, to have judged that both PHY-mode are identical, but because the situation generation that cross-link changes PHY-mode might take place to carry out simultaneously in two storage virtualization controllers, under this kind situation, the two still can't set up online, therefore, whether the PHY-mode that still need judge the two after converting inequality, determine to bring together finish to guarantee to set up online.And if the two takes place carries out when changing the PHY-mode situation simultaneously, because both sides can send after having changed and show new PHY-mode status information to the other side, therefore still can be by this and relatively learn via step S520 and to bring success together, therefore get and bring together once more again.

More can design in addition, carry out in the transfer process, add,, then end conversion and keep the PHY-mode that originally set and skip to the step of setting up in-line procedures (S530) if receive the PHY-mode information that the other side transmits at step S548.

Or, carry out in the transfer process at step S548, if receive the PHY-mode information that the other side transmits, then suspend conversion, whether the PHY-mode state of understanding the other side earlier is different with PHY-mode before carries out switch process S548 itself, if, then end converse routine and keep the preceding setting of conversion itself, and jump directly to step S530 and set up in-line procedures, and, then continue to finish conversion if the PHY-mode that discovers the other side is still preceding identical with own conversion.With avoid the other side finish conversion and with oneself inequality after, oneself be converted to consistent again and still can't set up the online facts with this other side.

Now lifting an example describes, at first, when subsystem starts power supply, its PCI-E interface of two storage virtualization controllers all can send out one and comprise and show that its PHY-mode is the information of mode of operation such as down stream, wherein comprises certainly in order to set up the PCI-E interface of communication channel ICC between controller.

And when the PCI-E of two storage virtualization controllers interface receives the information that the other side transmits, can resolve to understand its PHY-mode, when realizing its PHY-mode also for down stream, the two all can enter the program of brining together, picked at random one T value (supposes that first storage virtualization controller is chosen to be T1 separately, second storage virtualization controller is chosen to be T2), and pick up counting, when reaching this T value, then carry out cross-link, because the T value is a picked at random, therefore exhausted big probability, two controllers can be selected different T values, be T1 ≠ T2, and, then can be advanced into converse routine earlier a side who selectes less T value, and PHY-mode is converted to up stream, and send in conversion back include new PHY-mode information to the opposing party, and because the selected T value of the opposing party is bigger, so when receiving the information of the new PHY-mode that this other side transmits, may not reach its selected T value as yet, or just reached the T value and carrying out conversion PHY-mode program.If the former, then after receiving that the other side has been converted to the information of up stream, directly enter the in-line procedures of communication channel ICC between foundation controller between the two, if the latter, then can end to change and keep the PHY-mode of down stream originally, successfully set up communication channel ICC between controller between the two then.For example: suppose T1＜T2, then first storage virtualization controller can be introduced into converse routine, and PHY-mode is converted to up stream, and send the information that includes new PHY-mode (up stream) in the conversion back and give second storage virtualization controller, and the T2 value selected owing to second storage virtualization controller is bigger, therefore after first storage virtualization controller is finished converse routine, second storage virtualization controller be not do not begin as yet the conversion be exactly to be transformed into half, therefore second storage virtualization controller known to first storage virtualization controller still is in down stram pattern, so can think to bring together and finish and enter in-line procedures, in addition concerning second storage virtualization controller, if when receiving the information of the new PHY-mode that this first storage virtualization controller is transmitted, do not reach its selected T2 value as yet, because second storage virtualization controller is to be in down stream, also can enter in-line procedures, therefore, the two can correctly set up communication channel ICC between controller, perhaps, when second storage virtualization controller learns that in receiving the new PHY-mode information of first storage virtualization controller it changes upstream into, be just to have reached the T2 value to carry out conversion PHY-mode program, then second storage virtualization controller will be ended to change and keep the PHY-mode of down stream originally, successfully sets up communication channel ICC between controller between the two then.

And if unfortunately, both selected T values are identical, the two then may take place finishes converse routine simultaneously and transmits new PHY-mode information, that is both sides can receive that the other side PHY-mode is the information of up stream after converting, therefore identical again through the PHY-mode that relatively will learn both sides, so the two will find and bring success together, can reenter the program of brining together again, both sides are the selected T value of random number at random again, if selected T value difference just can comply with aforementioned successfully set up online.And because each time compole of coordinating to bring together is short, add owing to the T value is that random number is selected so the probability constant all selected identical T value of two controllers is almost nil, therefore, two storage virtualization controllers must tunable in a short time be one and be down stream, another is up stream, successfully sets up communication channel ICC between controller.

Please note, the operating process that first and second storage virtualization controller adopted in the present embodiment is identical (as shown in Figure 8), that is to say that the design that first storage virtualization controller is adopted is identical with this second storage virtualization controller, so present embodiment is can make between on all four two storage virtualization controllers of design successfully to set up communication channel ICC between controller.

Certainly, to utilize PCI-Express to link between two storage virtualization controllers and set up communication channel ICC between controller, change automatically and then set up the online mechanism by the PCI-E interface, also can adopt other non-mechanism of finishing voluntarily by the PCI-E interface except aforementioned.For example: (select or force) this PCI-E interface 934 becomes up stream to utilize the pin (pin) of cpu chip group/coordination engine 244 to set make; Perhaps, utilize software to fill in the register of the PCI-E interface 934 in the cpu chip group/coordination engine 244 and make the PHY-mode of (select or force) PCI-E interface 934 become up stream.But this dual mode, the former setting of must manually showing up, the latter must software detection set, and may cause last waste of time, and is therefore, more undesirable.But adopting among the embodiment of local bus interface (as pci interface) of no cross link feature with regard to of the present invention other, is comparatively suitable.

Because, storage virtualization controller can utilize the external interface that respectively links to send information to each device that is external in this controller when power initiation, and wait for response of each device, whether set up online smoothly and why each links the device that connected to understand.And in principle, total system is in design, remove the redundant storage virtualization controller to communication channel, other controller external communication channel connected is to be passive device, therefore its PHY-mode is up stream, therefore storage virtualization controller also can utilize in start and detect when respectively linking the interface on line state, when hookup mechanism also operates in down stream when learning, judges that this binding passage is to be communication channel ICC between controller.

In order to improve central processor usefulness among the storage virtualization controller, please continue and consult Fig. 9, the present invention proposes a kind of method that data transmit of carrying out, and comprising:

Central processing unit be Data Transport Protocol form (data-transfer-protocol format) according to a predefined to the data that another storage virtualization controller is given in tendency to develop, set up a corresponding discrete gathering table (Scatter-Gather (SG)-list) (step S910);

Central processing unit transmission one includes the information of depositing this SG-List address and is written to the register (register) (step S920) that belongs to this PCI-E interface of setting up communication channel between controller; And

This PCI-E interface is according to the address information of this register, read this SG-List, and to internal memory, read the defeated discrete data (scattered data) of tendency to develop, and these discrete datas are sent to another storage virtualization controller (step S930) by communication channel ICC between controller according to the content of this SG-List.

The above-mentioned register that belongs to the interface of setting up the controller communication channel can be designed to be positioned among the PCI-E interface, also can design among a register functions block (as register array).

When central processing unit carries out write activity to register, because this register is to be designed to belong to the PCI-E interface that this sets up communication channel between controller, therefore this register promptly can send this address information to the PCI-E interface that this sets up communication channel between controller, and triggers (trigger) this interface.

In one embodiment, be some specific address space in this register of planning definition, as the usefulness that writes the memory address of depositing SG-List.So design, to make when central processing unit writes the memory address of depositing this SG-List to these particular register addresses, same trigger pips such as this write activity, the engine (engine) that makes register be gone to trigger in the PCI-E interface removes to carry out the data transmission relative program.Plant mode according to this, the memory address that central processing unit only needs to deposit SG-List writes these particular register addresses and gets final product.

Seeing also Figure 10, is an embodiment who proposes relevant SG-List form among the present invention.According to this embodiment, the SG-List content includes: data bulk field (list-entry-count) in the table, in order to the number of the discrete aggregate data (SG data) that includes in the indicating gauge; Source origing address field (OAF) (Source-base-Addr) indicates every tendency to develop to fail its stored internal memory start address of discrete data; Data length field (Data-Length) indicates stored this tendency to develop of aforementioned internal memory start address to fail the length of discrete data; And target origing address field (OAF) (Destination-Base-Addr), the destination address of indicating these transmitting discrete data to desire to deposit; Or the like.

When the memory address that will deposit this SG-List when central processing unit writes register, the PCI-E interface reads out the discrete aggregate data in this SG-List according to the indicated memory address of register, and carry out start according to the discrete aggregate data in aforementioned defined each field in this SG-List, for example: after according to address information to this memory address of register that this central processing unit writes the control information in the header being read, down read the discrete aggregate data of this quantity in regular turn according to indicated quantity in the amount field in the table in the header, and the information of whole SG-List will be stored in the register, then set up of the indication of the PCI-E interface of communication channel between controller according to source origing address field (OAF) and this discrete data length field content of each discrete data, after reading this discrete data, be transferred to the PCI-E interface of setting up communication channel between controller of another storage virtualization controller in regular turn by ICC together with the target start address of this discrete data, when the PCI-E interface of setting up communication channel between controller of another storage virtualization controller is received these information, by properties is stored in these discrete datas in the destination address.

And also can comprise that in SG-List first interrupts (INT) field, whether in order to set in finishing this table after the listed data transmission, the interface of setting up communication channel between controller need produce interruption (interrupt) signal again; And second interrupt (Ints) field, finish these discrete datas and write when being stored in the corresponding destination address of each discrete data in order to whether to set destination (another storage virtualization controller), produce the central processing unit that interrupts (interrupt) signalisation self (another storage virtualization controller).

If the SG-List of system's predefined has these fields, then setting up between controller the interface of communication channel is to transmit this second break field content, so that the setting up communication channel interface between controller and must come start of another storage virtualization controller according to the setting of this field, as: 1 for producing central processing unit, 0 that the interrupt signal gives self for not producing.And this interface of setting up communication channel between controller is in finishing this SG-List after the indicated data transmission, to determine whether producing the action of an interrupt signal according to the indication of first break field of SG-List to central processing unit, as: 1 for produce, 0 for not producing.

In addition, because because factor such as spatial configuration in the internal memory, the situation that can't use single SG-List that all discrete aggregate data tabulars are entered may take place, at this moment can utilize several SG-Lists to come tabular and solve.Please consult Figure 10 again, in this preferred embodiment, still the field (Next-SG-List Addr.) that has a next SG-List address in the form of aforementioned SG-List, in order to indicate the stored memory address of next SG-List, therefore when setting up after the interface of communication channel reads the content of a certain SG-List between controller, just can know where next SG-List to be processed deposits in according to this field contents, and then get next SG-List according to this address read, make and to produce association automatically between these SG-Lists, and when no next SG-List, then this field will be set at 0, know that so promptly this SG-List is last list.Therefore, central processing unit needn't all will carry out once this SG-List storage addresses being write the action of register at each SG-List, as long as the address of first SG-List is write register, this interface of setting up communication channel between controller promptly can be finished the SG-Lists of all congeners automatically.

Please join Figure 11, show a hypothesis example.Suppose that central processing unit accepts the request that a host side is transmitted, this request relevant information and data are loose by the cpu chip component and are deposited in the internal memory everywhere, the memory address that central processing unit is deposited according to these information and dates and length etc. have produced four SG-List according to aforementioned form.

As shown in the figure, suppose that the stored address of first SG-List is 0000_0100.After setting up good these SG-Lists, CPU only need send the information that comprises address 0000_0100 and be written to be set in the cpu chip group and belong to the register that this sets up the interface of communication channel between controller, this is set up, and the PCI-E of communication channel is interfaced to the information that reads in the memory address 0000-0100 in the SG-List between controller, obtain control information and (comprise that first interrupts (INT), next SG-List address (Next-SG-List-Addr.), data bulk fields such as (list-entry-count) in the table), again according to the quantity of showing data shown in the interior data bulk field " 2 ", the information that reads in regular turn in the double-addresses such as being stored in address 0000_0110 and 0000_0120 (comprises source start address (Source-base-Addr), data length (Data-Length), target start address fields such as (Destination-Base-Addr)), and after the content of first SG-List all read in, then the start address of depositing according to the first stroke discrete data (1000_0000) reads this discrete data with length (0000_0010) to impact damper (buffer) to internal memory, the target start address of desiring to deposit together with this discrete data (A100_0000) is sent to another storage virtualization controller, aforementioned when reading and transmitting this discrete data, can this discrete data be read in batches and transmit in response to the actual capacity of impact damper.Then finish each discrete data (as: read this second discrete data to impact damper (buffer) according to the start address (1100_0000) of depositing second discrete data and data length (0000_0020) to internal memory, the target start address of desiring to deposit together with second discrete data (A200_0000) is sent to another storage virtualization controller equally) that reads and transmit thereafter in regular turn according to aforementioned manner.After finishing the reading and transmit action of all discrete datas that this first SG-List lists in, and owing to be 0 in first interruption (INT) field of this first SG-List, therefore the PCI-E interface of setting up communication channel between controller can not send interrupt signalisation central processing unit, be that 0000_0200 reads second SG-List then promptly according to next SG-List address (Next-SG-List Addr) field internal information (0000_020) to memory address, equally obtain content in this second SG-List according to aforementioned manner, and finish the transmission action of every listed in its table discrete data equally according to aforementioned manner, then read the 3rd SG-List according to Next-SG-List Addr. internal information equally, repeat to finish each SG-List so one by one, till the Next-SG-List Addr address setting in SG-List is 0000_000 (the 4th SG-List).And in this example, because having only first of the 4th SG-List to interrupt (INT) field contents is to be 1, therefore after the transmission action of finishing the 4th SG-List, the PCI-E interface of setting up communication channel between controller can produce an interrupt signal and give central processing unit, so central processing unit can learn that the data of four SG-List have finished transmission.

Utilize preceding method, when carrying out the redundant transmission data action, central processing unit only need safeguard that SG-List and transmission deposit first SG-List Addr and get final product to the cpu chip group, all actions of reading discrete data and transmitting discrete data then will be carried out by the cpu chip group, almost need not to take the working resource of central processing unit.

Moreover, set repayment according to the INT field in the SG-list after respectively transmitting data manipulation and give central processing unit in finishing when setting up between controller communication channel interface, successfully be sent to another storage virtualization controller so that central processing unit can be learnt these discrete datas, and can be abdicated the memory headroom that this deposits the SG-List that finishes transmission.Can adopt and whenever finish the mode that a SG-List promptly replys central processing unit this moment, and promptly the INT field of each SG-List all is made as 1; Or all related SG-List finish (till promptly next shown SG-List Addr address is 0000_0 in table) and just reply central processing unit, as preceding hypothesis example, have only the INT field of last SG-List to be made as 1, the INT field of other SG-List all is made as 0.The former benefit is because whenever finishing single SG-List just earlier replys, so memory headroom can be vacateed in real time, and making provides elasticity and usefulness preferably in the configuration utilization of memory space.As for adopting which kind of return method is can be by central processing unit according to system's actual state decision.

In addition, generally speaking, in redundant storage virtualization computer system, owing to must keep almost synchronous between two storage virtualization controllers, so when a storage virtualization controller must be informed another storage virtualization controller once changing, add that this IO operation in the running of common system is very complicated, the facts that therefore may continue to have new data or information need send another storage virtualization controller to takes place.

Below proposing a better implementation method, is in the aforementioned following steps that add again:

When the PCI-E interface of setting up communication channel between controller is being handled a certain SG-List, the cpu chip group is received new information or data and then is made central processing unit set up corresponding new SG-List (s) according to these information or data, the SG-List (s) that then central processing unit can be new with this insert or continue before the old SG-List that still has been untreated (s), for example: by the data in the Next-SG-List Addr. field that then will carry out in data in the Next-SG-list Addr field of a certain SG-list that still is untreated in the internal memory among the related SG-lists of change PCI-E interface well afoot or the register, change it into deposit this newly-established SG-List (s) start address, make also to produce continuous action relation between these front and back SG-List (s), make the automatic interlock of this PCI-E interface handle.

Further specify as follows, please cooperate and consult Figure 15, the cpu chip group is notified central processing unit after receiving new data and depositing this new data in internal memory, central processing unit will have been set up several related new SG-Lists (step S602) mutually to these new data.

Then central processing unit judges whether to have old SG-List (s) still be untreated (step S604), whether this step can send the Interrupt signal by the PCI-E interface of setting up communication channel between controller is learnt to central processing unit, if central authorities handle and not to receive that Interrupt signal, central processing unit are known before it does not finish transmission as yet and triggered discrete data to be transmitted.Suppose, if there is not an old SG-List that still is untreated and finishes, the start address that then will deposit newly-established SG-List (s) writes and belongs to the transmission flow process (step S606) that PCI-E interface that the register of setting up the interface of communication channel between controller sets up communication channel between controller with startup carries out new data;

And if still when being untreated already present SG-List (s), central processing unit sends out one and suspends request (Pause Req.) and give the PCI-E interface of setting up communication channel between controller, request interface time-out start (step S608) earlier.When this interface is received this request, will carry out one an opportune moment and suspend mechanism, suspend action on hand, and reply one in the time-out back and suspend approval (Pause Gnt) to central processing unit.Wherein suspending mechanism can be for example: the discrete data that will handle is finished and is transmitted the reading of suspending thereafter the back of each discrete data and transmit action; and note down when the breakpoint is suspended in order to cancellation and can recover the processing that continues, perhaps all discrete datas in the SG-List that will handle are suspended the action that enters next SG-List after all finishing and transmitting.

After receiving that suspending approval replys, central processing unit begins to insert or the interlock program (step S610) that continues, mainly be a certain still untreated SG-List among selected register or the preceding group of SG-Lists, the Next-SG-List Addr. that originally set among the Next-SG-List Addr. setting of last SG-List among the SG-Lists that newly produces and register or the chosen preceding group of still untreated SG-List is consistent, and the Next-SG-List Addr. in preceding group of chosen in register or the internal memory still untreated SG-List is changed to the stored start address of SG-Lists (depositing the address of first SG-List) of new generation, promptly finish the action of the preceding group of the SG-Lists insertion SG-List of new generation, interlock takes place and make between two groups of SG-Lists.

As the SG-List that makes new generation (s) and existed finish association between pending SG-List after, then notice is set up the PCI-E interface releasing halted state of communication channel between controller, the interface of then setting up communication channel between controller can recover the action that suspended, and continues to handle according to the automatic interlock of new association.(step S620)

It is aforementioned before central processing unit carries out two groups of SG-Lists interlocks, the reason of need to send suspending request is to be to prevent central processing unit in the change internal memory in a certain SG-List or the register in the information in the Next-SG-ListAddr. field, and this PCI-E interface of setting up communication channel between controller also reads the content of this SG-List and clashes the initiation mistake.

Below just insert or the interlock program (S610) that continues describes.See also Figure 16, be a kind of embodiment that inserts or continue the interlock program.In this embodiment, be to adopt the new SG-List (s) that produces directly to insert the SG-List mode afterwards that register is being handled.

Owing to set up the interface of communication channel between controller in the time will carrying out a certain SG-List, can obtain the content of SG-List earlier, so when status took place, central processing unit can be known whether the PCI-E interface has next SG-List to handle or next SG-List to be processed deposits in the information that where waits by reading the information of depositing in the register in the relevant Next-SG-List Addr. field.Therefore, as shown in figure 16, insert or first step of the program of the interlock that continues is at central processing unit, central processing unit reads the interior address date (step S612) of Next-SG-List Addr field among the SG-List that is handling in the register earlier, and after the Next-SG-List Addr. information that this PCI-E interface of acquisition can carry out originally, the Next-SG-List Addr. of last SG-List among its SG-Lists that directly will newly produce sets consistent with the Next-SG-List Addr. that originally set in the preceding register that reads, and the Next-SG-List Addr. in this register is changed to the stored start address of SG-Lists (depositing the address of first SG-List) of new generation, promptly finish the action of the preceding group of the SG-Lists insertion SG-List of new generation, interlock (step S614) takes place between two groups of SG-Lists and make.That is to say, the SG-Lists that newly produces directly is inserted in this interface will be followed before the SG-List pending after the SG-List that is handling originally, and after finishing the back corresponding data of the new SG-Lists that produces and transmitting, the rebound preceding group of still uncompleted SG-List (s) that can continue originally in the insertion point that continue again.Certainly, if the insertion point just is after last SG-List of preceding group of SG-List (s) (the Next-SG-List Addr. in the register that reads is 0000_000), group uncompleted SG-List (s) before then just rebound does not continue again is not because the uncompleted SG-List of group (s) exists.

With aforementioned Figure 11 is example, and please cooperates again and consult Figure 12.At first as shown in figure 11, the storage address that central processing unit is given the discrete data of another storage virtualization controller (companion) according to institute's tendency to develop establishes four SG-Lists of mutual interlock, and will contain the address information of depositing first SG-List and write register as the PCI-E interface of communication channel between controller, this interface reads this SG-List content according to the address information of register, and carries out actions such as reading and transmit data.

In addition, the cpu chip group is notified central processing unit after receiving new data again and depositing this new data in internal memory, central processing unit has been set up the new SG-Lists (please join Figure 12) of several mutual interlocks equally to these new data, so that these data can send its companion to when depositing fully, please note, as with Figure 11, though be example to produce many SG-List and many discrete datas, in fact same also may only produce a new SG-List or single discrete data content because of factors such as data volume and memory headroom configurations herein.

If set up the corresponding SG-Lists of new data when (as shown in figure 12) at central processing unit; still be untreated four SG-Lists of Figure 11 of this PCI-E interface of setting up communication channel between controller; at this moment; central processing unit sends out one and suspends request (Pause Req.) to this interface; request suspends the action that enters the next SG-List of processing earlier; when this interface is received this request; will carry out one and suspend mechanism; suspend everything on hand, and reply one and suspend approval (Pause Gnt) to central processing unit.After receiving that suspending approval replys, central processing unit begins to carry out the interlock program, and central processing unit reads the information in the relevant Next-SG-List Addr. field in the register.

Suppose that this moment, this interface was second SG-List that is handling among Figure 11, then the address information that central processing unit read will be 0000_040.Then central processing unit is set at 0000_040 with the Next-SG-List Addr. field of last SG-List among Figure 12, and change the Next-SG-List Addr. in this register into 0000_050 (the stored address of first SG-List among Figure 12), then finish the SG-List (as shown in Figure 12) that will newly produce be inserted in shown in Figure 11 second with the action between the 3rd SG-List.

And if aforementioned when receiving the time-out request that central processing unit sends, the interface of setting up communication channel between controller is just in time handled the 4th (last) SG-List among Figure 11, then the Next-SG-List Addr. in the register that central processing unit read can be 0000_000, Next-SG-List Addr. in last SG-List of new generation then shown in Figure 12 just need not change and still be set at 0000_000 and (please note, still consistent with the Next-SG-List Addr. in the register that is read), get final product and change the Next-SG-List Addr. in the register into 0000_050 (the stored address of first SG-List among Figure 12).

After finishing the interlock program; central processing unit then sends the interface that this sets up communication channel between controller that is notified to of removing halted state; interface is removed suspended mechanism; continue and suspend the preceding start of mechanism; and after handling time-out SG-List at that time; the Next-SG-List Addr. that will then be write according to its interval central processing unit removes to read first SG-List of new generation, and carries out the corresponding data of all pending SG-List (s) one by one according to the association of new generation and transmit.

See also Figure 17 again, show the embodiment of the another kind of insertion and the interlock program that continues.Different with Figure 16, the selected interlock of present embodiment insertion point is for setting up between the SG-List that the interface of communication channel still is untreated between controller (s) or afterwards.

As Figure 16, first step of inserting the program of interlock at central processing unit remains, central processing unit reads the interior address date (step S612) of Next-SG-List Addr field among the SG-List that is handling in the register, then central processing unit can judge whether the address in the register is 0000_000, to understand whether the SG-List (s) (step S616) that need continue and handle is arranged thereafter; If this address is set to 0000_000, then represent its not next SG-List that will continue and handle, so, central processing unit only needs the Next-SG-List Addr. in the register is changed into the stored address of first SG-List (step S617) of the SG-List (s) of new generation, can finish two groups of interlocks between SG-Lists.

If the Next-SG-List Addr. of this register is 0000_000, then expression has still thereafter that originally configuring to continue handles but untreated other SG-List (s), at this moment, central processing unit can select thereafter that a still untreated SG-List carries out insert action.Read the Next-SG-List Addr. in the SG-List selected in the internal memory, the Next-SG-ListAddr. of last SG-List of newly producing is set consistent with aforementioned the taker of reading, then make the Next-SG-List Addr. in the SG-List that should select in the internal memory into the new stored address of first SG-List that produces, promptly finish interlock program (step S618).

For example, last SG-List before central processing unit is selected among the group SG-Lists carries out interlock, because, the Next-SG-List Addr. of preceding last SG-List original start of group was exactly consistent (being all 0000_000) with the Next-SG-List Addr. of new last SG-List that produces originally, therefore the Next-SG-List Addr. that only needs change to organize last SG-List among the SG-Lists before this is the new stored initial memory address of SG-List (s) that produces, and promptly finishes the interlock of these two groups of SG-List.In such cases, after removing halted state, set up the PCI-E interface of communication channel between controller and before processing has transmitted, just can handle the new SG-List (s) that produces by automatic connection behind the group SG-List (s).Just adopting the new SG-List (s) that produces is the mode of preceding SG-List (s) insertion interlock afterwards of continuing.And last SG-List among the group SG-Lists before will finding, can utilize and set up a table that has a stored memory address of all SG-List, utilize this to show to inquire about and obtain, perhaps according to the Next-SG-List Addr in the register that is read, address information to this address read the Next-SG-List Addr. of the SG-List that is stored in this address, if this Next-SG-List Addr. is not 0000_000 yet, the Next-SG-List Addr. that then reads next SG-List more in regular turn downwards is till this Next-SG-ListAddr. is 0000_000.

Be example with Figure 11 and Figure 12 equally; same hypothesis is set up and is received the time-out request that central processing unit transmits when the interface of communication channel between controller proceeds to certain SG-List among Figure 11; register will be carried out and suspend mechanism, and transmit a time-out approval and give central processing unit after finishing.Then central processing unit reads the Next-SG-List Addr. in the register; if the Next-SG-List Addr. in the register is 0000_000; as: the interface of setting up communication channel between controller is being handled the 4th interior SG-List of Figure 11; then at this moment; change the Next-SG-List Addr. in the register among the SG-Lists that the desires the interlock processing as shown in figure 12 stored address of first SG-List (0000_050) by 0000_000; can be together with these two groups of SG-List interlocks; then trigger the PCI-E interface of setting up communication channel between controller and remove halted state; then the action that suspends before the mechanism that continues of this interface continues to do; and after handling three discrete datas organizing before having transmitted this in the 4th SG-List; according to the address (0000_050) in the Next-SG-List Addr. field in the register, then handle among Figure 12 new produce SG-Lists.

And be 0000_000 if Next-SG-List Addr. is non-in the register that read, for example: if handling and suspend at second SG-List shown in Figure 11 when setting up between controller communication channel interface, information in the register in the Next-SG-List Addr. field is 0000_040, thus central processing unit read this field information as can be known the PCI-E interface still be untreated but the SG-List storage addresses that then can handle is 0000_040.Then central processing unit can be according to situation or the selected desire of default insertion point.For example, selected being inserted in after last SG-List.The Next-SG-List Addr. that then can utilize central processing unit to obtain the 3rd SG-List to the 0000_0400 memory address is 0000_030, because be not 0000_000, therefore and obtain the Next-SG-List Addr. of the 4th SG-List to the 0000_0300 internal memory, because it is 0000_000, next expression does not have the SG-List of interlock, after finding this last SG-List, changing its Next-SG-List Addr. is that 0000_000 changes the stored address 0000_050 of first SG-List shown in Figure 12 into by script, make these two groups of SG-Lists produce a continuous action relation (as shown in figure 13), then notice is set up between controller communication channel interface and is removed halted state, makes that setting up between controller communication channel interface continues to finish in regular turn the corresponding data of each SG-List and transmit action.Also be exactly; setting up the action that suspends before the mechanism that continues of communication channel interface between controller continues to do; behind second SG-List before handling among the group SG-Lists; still organize the 3rd SG-List and the 4th SG-List among the SG-Lists before handling in regular turn; and after before handling, organizing last SG-List (storage address is the 4th SG-List of 0000_0300) of SG-Lists; can continue to handle back group SG-Lists automatically, send any information and need not central processing unit.

Perhaps, selected foundation between controller inserted after the next SG-List to be processed of communication channel interface.Then central processing unit also utilizes Next-SG-List Addr. (0000_040) in the register that is read, obtaining this Next-SG-List Addr. to this memory address 0000_0400 is 0000_030, this field contents is the stored address 0000_050 of first SG-List of the SG-Lists of new generation shown in Figure 12 in the change internal memory, and the Next-SG-List Addr. field of last SG-List of the SG-Lists of new generation shown in Figure 12 is inserted the aforementioned Next-SG-ListAddr. (0000_030) that reads the insert division, make these two groups of SG-Lists produce a continuous action relation (as shown in figure 14).Then same central processing unit notice is set up between controller communication channel interface and is removed halted state, makes that setting up between controller communication channel interface continues to finish in regular turn the corresponding data of each SG-List and transmit action.Also be exactly; setting up the action that suspends before the mechanism that continues of communication channel interface between controller continues to do; and originally set up between controller the communication channel interface back and will continue behind the SG-List (the 3rd SG-List among Figure 11) that handles handling; handle the SG-Lists that inserts with jumping automatically earlier; behind last SG-List (storage address is the 4th SG-List of 0000_0300) of group, send any information before then just rebound is handled again and need not central processing unit.

Certainly be chosen as the insertion point except last or a back SG-List, selected insertion point can also be pending thereafter second or the 3rd 's or the like SG-List, as long as be no more than last.As the preceding embodiment that waits, when producing the new data that needs transmission, handling the data that transmit a certain group as long as set up communication channel interface between controller, utilize aforementioned mechanism promptly can make and produce a continuous action relation between new legacy data, make central processing unit need not set up the repayment of communication channel interface between controller legacy data by the time and finished start address to the register and then triggering that writes the SG-List (s) of new data after the transmission more and set up communication channel interface between controller, set up between controller communication channel interface and promptly can handle automatically and transmit this new data.And because in theory, in the subsystem running, storage virtualization controller can constantly have data need send its companion (another storage virtualization controller) to deposit fully, just just having new data when last pen or even many data do not send the companion to as yet fully produces, therefore, with regard to aforementioned mechanism, central processing unit only need be set up and the corresponding SG-List of service data (s) and write the register of setting up communication channel interface between controller of setting up ICC with the storage address of first SG-List of being produced after the system start-up, thereafter this sets up that communication channel interface is promptly constantly reading and transmitting data between controller, to effectively significantly share the work of central processing unit, and then promote the task performance of central processing unit.

Moreover, when central processing unit needs integration or revises or delete certain SG-List (s) in generation, as the aforementioned insertion or the interlock program that continues, central processing unit can learn whether the PCI-E interface has next SG-List to handle or next SG-List to be processed deposits in the information that where waits by reading the information of depositing in the register in the relevant Next-SG-List Addr. field, just, central processing unit can be understood by this has those SG-List to set up that communication channel interface still is untreated between controller.Therefore, central processing unit can judge that whether its certain SG-List (s) that is intended to integrate or revise or delete is for setting up the still untreated SG-List of communication channel interface (s) between controller, if then central processing unit can be integrated or revise or action such as deletion this SG-List.

Certainly, when central processing unit carries out aforesaid modification or delete program, before reading the register internal information, can utilize equally and send suspend request and require to set up between controller communication channel interface and suspend earlier on hand and transmit the relevant action of redundant data, and just read action after suspending approval in receiving, to avoid continuing to carry out transmission work and the central processing unit modification or the facts that clashes of deletion action thereafter because of setting up communication channel interface between controller.And communication channel interface releasing halted state between controller is set up in same will notifying after central processing unit finishes complete the program of revising or deleting, so that it continues start.

In addition, can be at central processing unit according to actual state in conjunction with aforesaid insertion or continue interlock program and modification or delete program, for example: in a hypothesis example (Figure 13) of the above stated specification insertion or the interlock program that continues, the Next-SG-List Addr. field data of removing to change the 4th SG-List in the internal memory when central processing unit is when desiring to continue the start address of SG-List (s) of the new generation handled, can be simultaneously with according to actual needs (for example: the CPU desire is set and is set up that communication channel interface just produces interrupt signalisation CPU between controller when the SG-Lists of whole new association all finishes), go to change the setting of the Int field of this SG-List, and change this field data into 0, set up then that communication channel interface will can not send the Interrupt signal to central processing unit between controller after finishing this 4th SG-List.Or as: when making amendment this or delete program, also can be according to situation or demand at that time, utilize change not to be established Next-SG-List Addr. that communication channel interface between controller reads the SG-Lists of processing as yet and can reset association between these SG-Lists that still are untreated.

And except aforementioned transmission data to another storage virtualization controller and then deposit in the method for its internal memory, if system system is designed a storage virtualization controller can carry out access (writing/read) operation to the internal memory of another storage virtualization controller of redundant configuration the time, one data direction (Dir) field is then still arranged in this SG-List, write or read operation in order to the indication execution, for example: 1 for writing (Data Out), and 0 for reading (Data In) (seeing also Figure 10).

Thereby, the memory address that central processing unit will be deposited this SG-List writes register, the interface of setting up communication channel between controller promptly goes out the data read in this SG-List according to the address information that register transmitted, and carries out start according to the indication information in aforementioned defined each field.

If the Dir field is to be set indication to carry out write operation, then this interface is can be according to the indication of described source origing address field (OAF) and this discrete data length field content according to each discrete data of aforementioned each example, in reading this discrete data, the communication channel interface between controller of setting up of another storage virtualization controller is given in the instruction that write operation is carried out in the target start address and the indication of this discrete data, this discrete data then together by the traffic channel between controller in regular turn.

And if read operation, in one embodiment, this sets up the communication channel interface between controller of setting up that communication channel interface between controller can send this SG-List content to another storage virtualization controller, after this other end interface receives and deposits register in, indication according to source origing address field (OAF) and this discrete data length field content of each discrete data, read every discrete data in regular turn, then that discrete data is relevant with discrete data information (as: target start address, data length) communication channel interface between controller is set up in passback, and this interface deposits data in the internal memory in according to the target start address again.In another embodiment, be that non-content with whole SG-List all sends the other end to, but only transmit in the SG-List and every discrete data relevant field data, very and be to transmit every discrete data relevant field data (for example: source start address and data length) in batches, can have an indication during transmission and carry out the instruction of read operation, and after receiving the discrete data that other end passback obtains according to source start address and data length, the target start address of this discrete data of restoring.At last, with regard to the transmission of small amount of data between the storage virtualization controller, the present invention proposes the another kind of method that data transmit of carrying out, and enables more to improve the overall efficiency of storage virtualization controller.

See also Figure 18, show that another kind proposed by the invention transmits the method for data between two storage virtualization controllers.After coordinating to set up communication channel between two storage virtualization controllers (step S702), when if wherein central processor has the information that need pass to another person among the storage virtualization controller, central processing unit is directly to send data transfer request message to cpu chip group (step S704), this cpu chip group will respond this information and the information that will transmit sends another storage virtualization controller (step S706) to, and by cpu chip group of received in another storage virtualization controller and directly processing.

Please cooperate Fig. 5 again, according to this method proposed by the invention, when central processing unit 242 needs transmission information to give second storage virtualization controller, wherein a kind of reality of Data transmission transmission requests information as mode be the other end is delivered in tendency to develop for central processing unit 242 information by cpu i/f 910 to IM BUS950, and read and be sent to second storage virtualization controller 200 ' by the PCI-E interface 934 of setting up communication channel ICC between controller.In addition, (for example: PCI-E interface 934 first storage virtualization controller) receives the information that another storage virtualization controller (as second storage virtualization controller) is transmitted when a storage virtualization controller, then deliver to Memory Controller Hub 920, and then deposit in the internal memory 280 by IM BUS950.

Below proposing an embodiment further specifies.At first, setting with regard to each storage virtualization controller, is the extension that the internal memory of another storage virtualization controller of redundant configuration is considered as internal memory own.When the memory headroom of supposing first storage virtualization controller and second storage virtualization controller is all 2G, the physical memory address of each storage virtualization controller is made as 0000_0000-7FFF_FFFF, and is to be considered as 8000_0000-FFFF_FFFF with the memory address of another storage virtualization controller of redundant configuration.Be to adopt memory address with another storage virtualization controller memory address that directly continues own in this example, that is a storage virtualization controller is that another storage virtualization controller physical memory address P with redundant configuration is considered as virtual memory address 2G+P.So in fact also can adopt the non-mode that directly continues, for example: address P is considered as virtual memory address 3G+P with another storage virtualization controller physical memory, in principle as long as do not repeat with its own physical memory address own.Moreover, though herein with two storage virtualization controllers have identical storage space in save as example, but on the practice, the memory headroom difference of possibility two controllers, for example first storage virtualization controller is 2G but second storage virtualization controller is 1G, and entity or virtual memory address are also decided according to memory headroom.And according to the present invention is to set with regard to each storage virtualization controller, and the opposing party of redundant configuration some or whole internal memories can supply its access.

Suppose when a storage virtualization controller desire writes a certain data in the memory address 2100_0000 of another storage virtualization controller, then CPU242 writes this target start address (A100_0000) of object and writes data and directly transfers to cpu i/f 910, then this interface 910 with this address (A100_0000) with write data and be sent on the IM BUS950, and read by the PCI-E interface 934 that is coupled to another storage virtualization controller.Because the target start address in the information that central processing unit 910 is sent is for pointing to the virtual memory address of another storage virtualization controller, and be that PCI-E interface 934 is only arranged is the interface that is designed as linking up with another storing virtual words controller in each external interface in the cpu chip group 244, so each assembly is differentiated and only have this interface of setting up communication channel between controller can go to read and carry out data transmission.

In a present embodiment, after the PCI-E interface 934 of setting up communication channel between controller reads target start address A100_0000 and writes data, be earlier target start address A100_0000 to be converted to corresponding physical memory address 2100_0000, with write data and together send another storage virtualization controller to.And when another storage virtualization controller receives this physical memory address 2100_0000 and writes information such as data, data are write physical address 2100_0000.

And in another embodiment, this step that virtual memory address is converted to corresponding physical address is that the interface by receiving end carries out.Promptly set up communication channel between controller PCI-E interface 934 so that with this target start address A100_0000 with write data transmission to another storage virtualization controller.And read the target start address A100_0000 that the other end transmits and write information such as data when the PCI-E interface of another storage virtualization controller, be that this target start address A100_0000 (virtual memory address) is converted to corresponding physical address 2100_0000, and data are write this physical address 2100_0000.

According to present embodiment, when between two storage virtualization controllers, set up communication channel ICC, with regard to each storage virtualization controller, be that another storage virtualization controller with redundant configuration is considered as an end device, so deposit into the line access action within can having it.Thereby, except, aforementioned data are transmitted writes to outside another storage virtualization controller, also can read the interior data of internal memory of another storage virtualization controller.

When if design one storage virtualization controller is the operation that can be directly the opposing party's of redundant configuration internal memory is write and reads, then the data transfer request that central processing unit sent of storage virtualization controller must comprise access instruction, the operation that writes or read with indication.

If carry out write operation, way as described above then.And if read operation, then data transfer request is still to comprise Data Source start address and data length.Similarly, because the source start address is for pointing to the virtual memory address of another storage virtualization controller, thereby the interface of setting up communication channel between controller can read this request, and after handling, transfer to another storage virtualization controller of redundant configuration, and after the reported information of receiving another storage virtualization controller, be given to central processing unit.

When setting up in the cpu chip group that communication channel interface receives the request that is transmitted by another controller end between controller, be to separate the storage/access instruction in the read request and carry out corresponding writing or read data operation.If write operation then as described above.If read operation then will and be repaid and send the requestor to this according to source start address and data length reading of data, aforementioned whole storage/access process is to be carried out voluntarily by the cpu chip group.And write operation is general as described above, and to be converted to the step of corresponding physical memory address can be to be carried out by the interface of communication channel of setting up between controller of transmitting terminal or receiving end to virtual memory address in the data transfer request.That is, this method mainly is to adopt CPU directly to assign transmission requests to the cpu chip group, and read and it is passed to the storage virtualization controller of the other end by setting up between controller the interface of communication channel, thereby CPU need not set up corresponding SG-List to these data.

And if one when setting up the interface of communication channel between controller and receiving the data that another storage virtualization controller transmits, the process of whole data storage/access internal memory is to be carried out by this cpu chip group, need not to employ its central processing unit fully.

So, structure according to present embodiment, one storage virtualization controller is can be directly another storage virtualization controller of redundant configuration to be carried out access action, make take over its work when its damage and by the other side after, when it restores, can be directly by the memory content that reads the other side, perhaps by the other side's active transmission relevant information, enable to obtain information such as duty after understanding it and taking over and progress, and can recover to bring back the processing that continues.Itself and the internal memory of another storage virtualization controller can be considered as the extension of this internal memory own.

And because preceding method, central processing unit is not set up corresponding SG-List to data, when transmitting for small amount of data, can manifest tangible effect, because with regard to small amount of data, for example: the data of 1byte only, set up actions such as corresponding SG-List if need the data-driven transmission format protocol, the SG-Lis that central processing unit is set up in internal memory may be up to 16bytest, and this cpu chip group still need read this SG-List and comply with its contents processing, thereby just shows very uneconomical.And in a preferred embodiment, the mode of the transmission data of the aforementioned SG-List of the having characteristic of more can arranging in pairs or groups.System effectiveness makes the visual tendency to develop of storage virtualization controller send the number of data volume to decide which kind of mode of employing to transmit data and gives another storage virtualization controller, so that can reach optimization.

To sum up, redundant storage virtualization computer system proposed by the invention, communication channel between two storage virtualization controllers is directly to utilize local bus (as the PCI-Express among the embodiment) to reach, with the FC-AL that is adopted traditionally, SATA or SCSI etc. are outside to link difference fully, and compares, the present invention need not be again by a middle referral circuit, therefore, its circuit design is not only comparatively simplified, and cost is also lower.

Moreover, in order to solve that two storage virtualization controllers are all aggressive device and the online problem of communication channel that can't really make the two, in an embodiment of the present invention, be to utilize local bus interface behind system boot, can automatically send to contain the function of information such as himself interface setting state to another connecting end, by this, why each storage virtualization controller can understand its pattern of setting up communication channel interface of its another connecting end, therefore discernable whether being between the two can be set up online state, can't set up online state if be in, then enter converse routine, change the local bus interface operator scheme of at least one communication channel end, it is online that it can be set up smoothly.

And for converse routine, except proposing monolateral conversion embodiment, also propose one and bring embodiment automatically together, the mode of utilizing random number at random to choose determines a latency value, after this time reaches, carry out the translation interface operator scheme,, therefore wherein one must arrive earlier because the different facts of selected latency value must take place for the two, and change, therefore can successfully bring the operator scheme of the interface of communication channel two ends between two storage virtualization controllers together. in advance

Again, how use the formed communication channel of this local bus to transmit section data, one implementation method is proposed again, make that central processing unit only needs to set up and safeguard that tendency to develop send data corresponding SG-List according to the Data Transport Protocol form of a predefined, and the register that the storage address of first SG-List writes in the cpu chip group got final product, other reading of data that need carry out and a large amount of actions that these data are transmitted, to carry out by the interface of setting up communication channel between controller fully, therefore can effectively reduce between the redundant storage virtualization controller and extend the problem that influences central processing unit usefulness in order to keep mutual data sync and conforming requirement.And among the further again embodiment, more can make between the new data that before last data are not finished transmission, is produced and produce continuous action relation, but the interface automatic connection of setting up communication channel between controller is handled.

At last, for the usefulness that can make storage virtualization controller reaches preferableization, in the transmission of the small amount of data between the redundant storage virtualization controller, the method of the transmission information between a kind of redundant storage virtualization controller is also proposed, mainly be used in set up communication channel between two storage virtualization controllers after, adopt the interior central processing unit of controller directly to transmit the mode of solicited message to the other end by ICC, need not construction SG-List, thereby, in the small amount of data transmission, can increase system handles usefulness.

The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. computer system includes:

One main frame is used for sending output and goes into request;

One group of redundant storage virtualization controller, being used to carry out output goes into operation and goes into request with the output that responds this main frame and send, it includes one first and one second storage virtualization controller that is coupled to this main frame, this first and this second storage virtualization controller between be to utilize a local bus to communicate; And

One group object memory storage is coupled to these storage virtualization controllers, is used to provide this computer system stores space;

Wherein, when this first storage virtualization controller situation occurred, this second storage virtualization controller will automatically be taken over the original function of carrying out of first storage virtualization controller of this situation occurred;

Wherein this local bus is to adopt the mode of cable or backboard to be connected in this two to deposit virtualization controller, this first with this second storage virtualization controller respectively include a local bus interface, in order to set up the local bus communication channel between this first and second storage virtualization controller, and one by this two local bus interface is gone to change its operator scheme, so that set up online between the local interface of these storage virtualization controllers.

2. computer system as claimed in claim 1, wherein, this local bus is one of following:

Perimeter component links bus, perimeter component links expansion bus or perimeter component links quick bus.

3. computer system as claimed in claim 1, wherein, this two local bus interface is each positioned at a central processing unit chipset, and at least one the pin that utilizes this two central processing units chipset is set and is made this described one local bus interface of this two central processing units chipset go to change its operator scheme, so that set up online between the local bus interface of these storage virtualization controllers.

4. computer system as claimed in claim 1, wherein, be to utilize software to fill in one register of this two local bus interface and make described one of this two local bus interface to go to change operator scheme, so that the local bus interface of these storage virtualization controllers is set up is online.

5. computer system as claimed in claim 1, wherein, these local bus interface also have the feature that intersection links.

6. computer system as claimed in claim 5, wherein, at least one of these local bus interface carried out an automatic transfer machine system, the feature of utilizing this intersection to link is changed described one operator scheme of these local bus interface, so that can set up online between this first and second storage virtualization controller.

7. Storage Virtualization subsystem includes:

One group of redundant storage virtualization controller, being used to carry out output goes into operation and goes into request with the output that responds a main frame and send, it includes one first and one second storage virtualization controller that is used for being coupled to this main frame, this first and this second storage virtualization controller between utilize a local bus to communicate; And

One group object memory storage is coupled to these storage virtualization controllers, is used to provide this Storage Virtualization subsystem stores space;

Wherein, when this first storage virtualization controller situation occurred, then this second storage virtualization controller will automatically be taken over the original function of carrying out of first storage virtualization controller of this situation occurred;

8. subsystem as claimed in claim 7, wherein, this local bus is one of following: perimeter component links bus, perimeter component links expansion bus or perimeter component links quick bus.

9. subsystem as claimed in claim 7, wherein, this two local bus interface is each positioned at a central processing unit chipset, and at least one the pin that utilizes this two central processing units chipset is set and is made this described one local bus interface of this two central processing units chipset go to change its operator scheme, so that set up online between the local bus interface of these storage virtualization controllers.

10. subsystem as claimed in claim 7, wherein utilize software to fill in one register of this two local bus interface and make described one of this two local bus interface to go to change operator scheme, so that set up online between the local bus interface of these storage virtualization controllers.

11. subsystem as claimed in claim 7, wherein, these local bus interface also have the feature that intersection links.

12. subsystem as claimed in claim 11, wherein, at least one of these local bus interface is to carry out an automatic transfer machine system, the feature of utilizing this intersection to link is changed described one operator scheme of these local bus interface, so that can set up online between this first and second storage virtualization controller.

13. a method of setting up the communication channel between the storage virtualization controller may further comprise the steps:

These storage virtualization controllers are by comprising the information of its operator scheme as the local bus interface transmission one of communication channel end between controller;

In these storage virtualization controllers at least one compares to judge whether to set up the operation mode information of this another storage virtualization controller of being received and the operator scheme of self online when receiving the operation mode information of another this storage virtualization controller by this local bus interface;

If it is online that judgement can be set up, then directly set the communication channel of setting up between this two storage virtualization controller according to this local bus interface; And

If be judged as can't set up online, then at least one in these storage virtualization controllers will be changed the operator scheme of this local bus interface, so that corresponding, and then set up each other online with the operator scheme of this local bus interface of another this storage virtualization controller;

Be to utilize a local bus to communicate between one first and one second storage virtualization controller in these storage virtualization controllers wherein, this local bus is to adopt the mode of cable or backboard to be connected in this two to deposit virtualization controller, this first with this second storage virtualization controller respectively include this local bus interface, in order to set up the local bus communication channel between this first and second storage virtualization controller, and one by this two local bus interface is gone to change its operator scheme, so that set up online between the local interface of this storage virtualization controller.

14. method as claimed in claim 13, wherein, these local bus interface are that perimeter component links quick bus interface.

15. method as claimed in claim 13, wherein, this local bus is to have the feature that intersect to link, and online for setting up when this comparison judged result, and then this storage virtualization controller is an operator scheme of utilizing the feature of this intersection binding to come translation interface.

16. method as claimed in claim 13, wherein, when judged result relatively for setting up in the step performed after online, include one and bring mechanism together so that the operator scheme of these local bus interface corresponds to each other, and set up online.

17. method as claimed in claim 16, wherein, this match mechanism system may further comprise the steps:

A selected at random timing critical parameters value then starts timing;

If before the time reaches this critical value, receive the new operation mode information of the other side and show that it has changed operator scheme, then finish bring together and set up online;

If when the time reaches this critical value, and do not receive the information that the other side's operator scheme has changed, then carry out this conversion operations mode step, and contain new operational mode status information to the other side in converting back transmission one; And

Whether the operator scheme kenel that rejudges between the two is inequality, if inequality then brining together finished and set up online, if identical, then re-executes this match mechanism, brings together up to this and finishes.

18. method as claimed in claim 17, wherein, in this match mechanism, more may further comprise the steps in the step of this execution conversion operations pattern: if when carrying out the conversion operations pattern, receive the operation mode information that the other side transmits, then end conversion and keep the operator scheme that originally set.

19. method as claimed in claim 18 wherein, before this ends conversion, is whether the operator scheme of carrying out the other side relatively earlier is different with itself operator scheme before the conversion, if just carry out this terminations switch process, otherwise continue execution conversion.

20. a method of carrying out data transmission in a computer system between storage virtualization controller comprises following steps:

A. the central processing unit of this storage virtualization controller one discrete data of another storage virtualization controller is defeated by in tendency to develop according to the Data Transport Protocol form of a predefined is set up at least one corresponding discrete gathering table;

B. this central processing unit address that will deposit this discrete gathering table writes a register; And

C. a local bus interface writes in address to an internal memory in the register according to this and reads this discrete gathering table, this discrete data is read in a address according to indicated this discrete data of storage of discrete aggregate data in this table to this internal memory, and transmits this discrete data by a local bus and give another storage virtualization controller;

21. method as claimed in claim 20, wherein, this local bus is for one of following: perimeter component links bus, perimeter component links expansion bus and perimeter component links quick bus.

22. method as claimed in claim 20, wherein, after the address that this discrete gathering table deposited this by this central processing unit write this register, this register was that this address information is sent to this local bus interface, and triggered this local bus interface and carry out this step C.

23. method as claimed in claim 20, wherein, this central processing unit is that this address of depositing this discrete gathering table is write the storage space that is defined in this register as the particular address that writes this usefulness of depositing discrete gathering table address.

24. method as claimed in claim 20, wherein, the Data Transport Protocol form of this discrete gathering table is to comprise following field:

Data bulk field in the table is in order to the number of the discrete aggregate data that includes in the indicating gauge;

The source origing address field (OAF) is failed its stored internal memory start address of discrete data in order to indicate every tendency to develop;

Data length field is in order to indicate the length of the defeated discrete data of this every tendency to develop; And

The target origing address field (OAF) is in order to the destination address of indicating the transmitting discrete data to desire to deposit.

25. method as claimed in claim 24, wherein, among the step C, this local bus interface is carried out and be may further comprise the steps:

Read according to the control information that information that this central processing unit sent will disperse to this internal memory in the gathering table header, according to the quantity of this discrete aggregate data down read in regular turn this quantity should discrete aggregate data control information; And

According to this source origing address field (OAF) in this each discrete data that is read and the indication of this data length field content, read this discrete data one by one, and will this every discrete data be transferred to this another storage virtualization controller together with this target start address of this discrete data by this local bus.

26. method as claimed in claim 25, wherein, this discrete data that this local bus interface read is to be temporary in an impact damper earlier, just transfers out together with this target start address thereafter.

27. method as claimed in claim 26 wherein, when this local bus interface reads and transmit this discrete data at this, reads this discrete data and transmits according to the actual capacity of this impact damper in batches.

28. method as claimed in claim 25 wherein, comprises that more the local bus interface of this another storage virtualization controller receives this discrete data and this target start address, this discrete data is stored in the step in the internal memory of this destination address.

29. method as claimed in claim 25, wherein, the Data Transport Protocol form that is somebody's turn to do discrete gathering table more comprises a data direction field, carries out writing or read operation in order to indication, makes this local bus interface carry out corresponding accessing operation according to this field contents.

30. method as claimed in claim 29, wherein, at step C, execute the step that reads discrete gathering table content in this local bus interface after, more include:

Content according to this data direction field is carried out corresponding writing or read operation;

If this content is designated as the execution write operation, then carries out the discrete gathering of these follow-up foundations and show each field and read this discrete data and transmitting discrete data step to this another storage virtualization controller;

If read operation is carried out in the indication of this content, in the gathering table that then should disperse at least the part field contents be transferred to this another storage virtualization controller by this local bus; And

After receiving this discrete data that this another storage virtualization controller passes, deposit in this internal memory according to corresponding this target start address of this discrete data again.

31. method as claimed in claim 30, wherein, the chipset of this central processing unit is to give this another storage virtualization controller with this whole discrete gathering table content delivery.

32. method as claimed in claim 30, wherein, after the central processing unit chipset that more comprises this another storage virtualization controller receives these discrete gathering table contents, indication according to this source origing address field (OAF) and this data length field content, read every discrete data in regular turn, and the step that returns these discrete datas.

33. method as claimed in claim 24, wherein, the Data Transport Protocol form of this discrete gathering table more comprises following field:

First break field, whether in order to set in finishing this table after the listed data transmission, the chipset of this central processing unit need produce a look-at-me and notify this central processing unit; And

Second break field in order to set this another storage virtualization controller after receiving these discrete datas and finishing corresponding operation, produces a look-at-me.

34. method as claimed in claim 33, wherein, step C more includes:

This central processing unit chipset sends this second break field content to this another storage virtualization controller; And

The chipset of this central processing unit determines whether producing the action of a look-at-me to central processing unit according to the indication of this first break field in finishing this discrete gathering table after the indicated data transmission.

35. method as claimed in claim 24, wherein, the Data Transport Protocol form that is somebody's turn to do discrete gathering table more comprises next discrete field of assembling table address, show stored memory address in order to deposit next discrete gathering, with the chipset of indicating this central processing unit after finishing the indicated data transmission of a discrete gathering table content, according to the discrete content of assembling the field of table address of this next one, read next discrete gathering table, and then interlock continues to handle.

36. method as claimed in claim 35, wherein, more include systems organization and be set with the numerical value that an expression does not have next discrete gathering table existence, when the discrete content of assembling the table address field of this next one is this numerical value, show that promptly not having other discrete gathering table of existence needs interlock to handle.

37. method as claimed in claim 36, wherein, this numerical value is to be 0.

38. method as claimed in claim 35 more may further comprise the steps between steps A and B:

Check and whether have the discrete gathering table that still has been untreated;

If have, then carry out an interlock program, use so that newly-established discrete gathering table and the aforementioned discrete gathering table that still has been untreated produce interlock; And

Otherwise, execution in step B.

39. method as claimed in claim 38, wherein:

Carry out more may further comprise the steps before the interlock program at this:

This central processing unit sends out one and suspends request to this local bus interface, suspends the relevant action that transfers data to this another storage virtualization controller in order to request; And

Receiving this time-out request when this local bus interface, is to carry out one to suspend mechanism, and after finishing this time-out mechanism, answer one suspends approval and gives this central processing unit; And

After carrying out the interlock program, this more may further comprise the steps:

This central processing unit notifies this local bus interface to remove halted state; And

Receiving this releasing notice when this local bus interface, is the action that recovery is suspended, and continues to carry out to handle and transmits data.

40. method as claimed in claim 39, wherein, this time-out mechanism is the discrete data of handling to be finished the reading of suspending thereafter the transmission back of each discrete data transmit action, and notes down and recover to continue processing when the breakpoint is suspended in order to cancellation.

41. method as claimed in claim 39, wherein, this time-out mechanism is that all discrete datas in the discrete data table that will handle are all finished the action that transmission back time-out enters next discrete gathering table.

42. method as claimed in claim 38, wherein, this interlock program comprises:

This central processing unit reads the next discrete address date of assembling in the table address field in the discrete gathering table that is stored in this register;

This central processing unit judges according to the address in this register that is read whether this local bus interface has the discrete gathering table that need continue and handle thereafter;

If judged result is the discrete gathering table that need not to continue and handle, then changing the field contents of depositing next discrete gathering table address in this register is the start address of depositing this newly-established first discrete gathering table; And

If judged result is to have the discrete gathering table that must continue and handle, then change one the field contents of depositing next discrete gathering table address of these discrete gathering tables that still have been untreated, change it into deposit this newly-established first discrete gathering table start address, and the next discrete table address field contents of assembling of depositing of last sets that to deposit the next gathering table address field contents that disperses consistent with one of the aforementioned discrete gathering table that still has been untreated before change not this in will this newly-established discrete gathering table.

43. method as claimed in claim 42, wherein, one of the discrete gathering table that this still has been untreated is meant when this local bus interface is suspended mechanism, is stored in the discrete gathering table in the register.

44. method as claimed in claim 42, wherein, last discrete gathering table that is meant in the discrete gathering table of these interlocks that still have been untreated of the discrete gathering table that this still has been untreated.

45. method as claimed in claim 42, wherein, comprise that more setting up a record has the table of all discrete gathering memory addresss that table is deposited, use and inquire about the discrete gathering of still being untreated that this desire change deposits the field contents of next discrete gathering table address for this central processing unit and show stored memory address.

46. method as claimed in claim 42, wherein, this central processing unit system reads the discrete table address field contents of assembling of the next one that is stored in the discrete gathering table in this address according to the discrete table address information of assembling of the next one in this register that is read to this address, repeat it in regular turn, up to reading till desire change of this central processing unit institute deposits the discrete gathering table that still has been untreated of the next discrete field contents of assembling table address.

47. method as claimed in claim 20 wherein, when this central processing unit need be transferred these discrete gathering tables of having set up, is to carry out may further comprise the steps:

Check the discrete gathering table that has been untreated at present; And

Judge whether its discrete gathering table that is intended to transfer belongs among these discrete gathering tables that still have been untreated, if then transfer, otherwise, do not transfer.

48. method as claimed in claim 47 wherein, is to utilize this central processing unit to read to be stored in the address date in the next discrete gathering table address field in the interior gathering table that should disperse of this register, to know the present progress of data transmission.

49. method as claimed in claim 47, wherein

Before transferring, more may further comprise the steps:

After transferring, more may further comprise the steps:

50. transmit the method for data in the computer system between storage virtualization controller, include following steps:

The central processing unit of one storage virtualization controller is to send a data transfer request to a central processing unit chipset;

One first local bus interface in this central processing unit chipset is this request to be changeed pass to another storage virtualization controller; And

One second local bus interface of this another storage virtualization controller will be carried out corresponding processing after receiving this request;

51. method as claimed in claim 50, wherein, these local bus interface are for one of following: perimeter component links bus interface, perimeter component links expansion bus interface and perimeter component links quick bus interface.

52. method as claimed in claim 50, wherein, the step that this central processing unit sends data transfer request comprises:

This central processing unit transmits this data transfer request to the central processing unit interface in this central processing unit chipset;

This central processing unit interface is placed on the main bus in inside in this central processing unit chipset with this data transfer request; And

Read this data transfer request by this first local bus interface.

53. method as claimed in claim 50, wherein, this data transfer request content is to include a discriminant information, this first local bus interface is differentiated and is read this data transfer request.

54. method as claimed in claim 53, wherein, more include: this storage virtualization controller is that the physical memory address of this another storage virtualization controller of definition is represented with a virtual memory address form, make with its own physical memory address own and can not repeat, and this discriminant information is to be a memory address, and this memory address is also represented with this virtual memory address form.

55. method as claimed in claim 54 wherein, is to adopt the mode of the physical memory address of directly continuing own to go to define this virtual memory address.

56. method as claimed in claim 54 comprises that more in this first and second local bus interface is to carry out the step that this memory address is converted to corresponding physical memory address.

57. method as claimed in claim 50, wherein, this data transfer request is to comprise access instruction, carries out one of following operation in order to indication: write and read.

58. method as claimed in claim 57, wherein, the corresponding processing that this another storage virtualization controller carried out is to comprise that this access instruction that this second local bus interface is separated in the read request indicates corresponding operation to carry out this.

59. as claim 50 or 57 described methods, wherein, this data transfer request is to comprise that one writes data, an and target start address, this target start address is to write the memory address that this writes data in order to indication, and this another storage virtualization controller to carry out this corresponding processing be to comprise: according to this target start address this is write in the data write memory.

60. method as claimed in claim 59, wherein, this data transfer request more comprises a data length, and a Data Source start address, and corresponding processing that this another storage virtualization controller carries out is meant according to this Data Source start address and this data length reading of data and these data are returned to this first local bus interface to this internal memory.

61. method as claimed in claim 60 more includes: receiving after the passback data of this another storage virtualization controller it is to send central processing unit to when this first local bus interface.