CN1391672A

CN1391672A - Raid controller system and method with ATA emulation host interface

Info

Publication number: CN1391672A
Application number: CN00815961A
Authority: CN
Inventors: M·C·斯托洛维茨
Original assignee: NetCell Corp
Current assignee: NetCell Corp
Priority date: 1999-09-22
Filing date: 2000-09-21
Publication date: 2003-01-15
Anticipated expiration: 2020-09-21
Also published as: KR100441189B1; CA2385492C; CN1222876C; CA2385492A1; KR20020048414A; TW476030B; WO2001022221A1; JP2003510683A; EP1236106A4; AU7714700A; EP1236106A1; HK1050935A1

Abstract

A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g., level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Description

Raid controller system and method with ATA emulation host interface

Related application

The application is the continuation of the U.S. Provisional Application No.60/156001 that proposed on September 22nd, 1999 and requires its rights and interests.

Technical field

The present invention relates to the computer data storage device controller, specifically, relate to a kind of RAID controller, have the host interface of the IDE equipment of simulating the ATA standard controller and being connected.

Background of invention

First IBM PC and compatible have only floppy disk to be used for the high capacity storage.XT subsequently and AT model comprise the adapter of the 5.25 inches shaft collars (non-dismounting) that are used to be connected mass data storage.These initial adapters provide the most of rudimentary control signal that is used for driver, comprising the data separation circuit that is used for read signal and precompensation write signal.In adapter, comprised these functions and avoided duplicating a pair of driver, wherein driver of an access once.Unfortunately, the read/write channel of 5MB does not allow along with the improvement of technology connection speed driver faster in the adapter.

By " in real time " mode of controller is introduced driver, solved this problem.Integrated drive electronics, promptly the IDE driver combines and reads or writes driver required whole controls and data channel, transmits data between local buffer and medium.Data rate can be selected by manufacturer.For being connected of data storage device and host computer system, defined a kind of new interface, i.e. ATA (AT Attachment Packet Interface (ATA/ATAP14)) (IBM AT Attachment Packet Interface) with packet interface expansion.First ide interface has only comprised address decoder and the buffering between isa bus and the ATA cable connector.Interface protocol has adopted program control input and output to instruct the register of access IDE equipment.Data transmission has adopted the input string and the instruction of output string of primary processor, the transfer rate of regulating the driver that is connected.In the standard of nearer version, these transfer rates reach 16MBPS.This is the transfer rate between the storer of the impact damper of memory device and isa bus.Transfer rate between medium and the impact damper is then much lower.

Along with the appearance of pci bus, Intel Company has issued PCI IDE document (PCI IDE controller technology standard, revised edition 1.0,3/4/94), before it provides based on the mapping of the host interface of isa bus to pci bus.This standard to describe a kind of pair of IDE channel controller.A pair of equipment, promptly main equipment and slave unit can be connected to each channel.For data transmission, this equipment can also be carried out access as the pci bus target.

Intel Company has also issued bus master controller IDE document (DLL (dynamic link library) of bus master controller IDE controller, revised edition 1.0,5/16/94).The document has defined in the IDE channel standard in conjunction with dma device.The bus master interface allows the IDE channel to transmit data by pci bus to system storage or from system storage, as bus master controller (pci bus starter).The peak transfer rate that is transferred to 32/33MHz pci bus is 133MBPS.

The revised edition of ATA standard has defined a kind of new transmission mode, i.e. Ultra DMA.By tightening the setting and the retention time requirement of data transmission in the cable, the transfer rate before having improved.When 16MBPS, greatly limited by the round trip that sends read strobe, access data and these data of loopback and to have read transfer rate.Ultra DMA agreement has kept the electrical specification of all signals and cable at first, and the function that has just redefined three kinds of signals wherein is providing new agreement.In this agreement, providing data strobe signal regularly to transmit, that is: for writing, undertaken by controller, and, then undertaken by equipment for reading as data from same end.In this configuration, transfer rate just is subjected to the restriction that the cable list shifts the cable skew of (single transition).The one UDMA equipment makes program control IO transfer rate be multiplied to 33MBPS.Revised edition subsequently makes initial UDMA transfer rate be multiplied to 66MBPS, but requires to use 80 flat cables with alternating signal and ground connection web member.Present version is supported the transfer rate of 100MBPS.A kind of trend is arranged at present, replace the ATA parallel interface with high speed serialization link exactly, but may at first can issue the parallel interface of more increases and line speed.

Problem

It is the mainboard that the center is designed that common personal computer comprises with the chipset, comprises processor, DRAM interface, various input/output adapter and BIOS ROM.The IO adapter generally includes ide interface.The characteristic of the IDE controller of current version has been a pair of IDE port, and each port all can be connected with a pair of IDE memory device.These equipment generally include one or more IDE hard disks and CD ROM, DVD ROM or CD WORM driver.Basic Input or Output System (BIOS), promptly BIOS is a kind of program, is used for guiding PC and provides rudimentary IO routine for the adapter on the mainboard.All these PC can use mainboard BIOS from channeling conduct of IDE hard disk and operation basically.

In using, the server in market, small office/family office (SOHO) or workstation disposed increasing personal computer.In history, the hard disk with small computer system interface (SCSI) provides some performance gains for more strict application.But in today, along with the driver more than 85% is made the IDE driver, the SCSI driver also trends towards adopting same medium and read/write head to build, and has seldom or does not have performance gain and greatly increased cost.Another kind of popular selection scheme is, adopt Redundant Array of Inexpensive Disc (RAID), it at first by Patterson suggestion (people's " situation of Redundant Array of Inexpensive Disc (RAID) " literary composition such as D.Patterson (and Univ.Cal.Report No.UCB/CSD87/391, Dec.1987).The RAID system is devoted to reliability and these two aspects of performance.At first, with the redundant fashion storage data,, thereby realize reliability by two or more drivers so that can obliterated data when the single driver fault.Secondly, with respect to single driver, because the set performance of this array has realized the performance increase.The different piece of the data that store with redundant fashion can read from two drivers simultaneously.In addition, data can write with the form of data strip, and wherein, data strip when readback data, can realize gathering transfer rate through all available drivers.In U.S. Patent No. 6018778 of the present invention, the RAID array control unit is further specified.

Unfortunately, there are some defectives in existing several RAID solution.The local intelligence of SCSI disk drive uses the feature of representing a class RAID solution with reaching.This class solution has been showed high-performance, though the cost of driver and controller is high.Another kind of popular RAID solution is characterised in that uses the IDE driver but shortage local intelligence or buffering.This mainly is a software solution.Control a plurality of drivers so that keep redundant or the required software of data slivering all must be moved in host computer system, greatly increased disc driver expense in processor and system bus.Like this, the RAID benefit is to cause that with the system overhead owing to described increase the cost that system performance descends realizes.These two kinds of solutions all have an additional problem.These RAID controllers do not have directly to be supported by the BIOS of mainboard.Require extra software driver.These drivers may change to some extent with the function of operating system, and described operating system for example has Windows, WindowsNT, UNIX, LINUX etc., thereby bring extra burden for controller manufacturer, OEM, market group and system integrator.

Therefore, still need a kind of raid storage devices controller, it does not need special software to carry out in primary processor, and does not need extra software driver or BIOS is changed.The RAID controller that does not need BIOS is changed has the following advantages usually: have the compatibility of " plug and play " with all ready-made computing machines of realizing that ATA comply with the standard of interface in fact.The RAID controller is transparent to main frame, and can dispose a plurality of memory devices (being not limited to four) with the combination in any of equipment interface, and can realize RAID mirror image, slivering etc., and does not increase expense to main frame.This RAID controller is installed to bring all pc users the RAID function with low-cost and very easy.

Summary of the invention

The present invention realizes a kind of RAID controller, it and all operations system compatible, and described operating system can be used standard IDE controller and channeling conduct and the operation on given PC mainboard of IDE driver.Realize described compatibility by the mock standard controller with the driver that is connected.For example, for reliability, can in RAID1 or " mirror image " configuration, require a pair of driver for fixed system.When being connected to controller of the present invention, BIOS will see single driver very reliably.This system also can require the array of three drivers, is configured to RAID3 or RAID5 configuration.This will provide the wherein any one transfer rate that doubles three drivers, have high reliability simultaneously.Similarly, in the present invention, for BIOS, the array of this three drivers appears to and is single driver, informs the wherein any one capacity that doubles these three drivers, and shows the transfer rate that twice is arranged, and has high reliability.Under any circumstance, RAID is transparent for existing driver among the BIOS.

Controller mock standard two channel id E controllers of the present invention.As standard controller, it logically is connected to pci bus.It may reside on the mainboard physically, may be integrated in the board chip set, perhaps is present in the plug-in type card of PCI groove.It can simulate all four equipment that can be connected to standard controller.Each of these logical device all provides the possible interface to the array of the physical equipment that is connected to described controller.Though the connection that present embodiment provides ata port to be used for phisical drive, the interface of other type or combination of interfaces all can be used.

By below in conjunction with the detailed description of accompanying drawing to most preferred embodiment, other purpose of the present invention and advantage will be obvious.

Summary of drawings

Fig. 1 is the simplified block diagram that prior art ATA double-channel controller is used, and physics and software/register view is described.

Fig. 2 is a kind of according to the simplified block diagram with RAID controller of ata port emulation of the present invention.

Fig. 3 is the high-rise simplified block diagram of a kind of present best business embodiment of the RAID controller with ata port emulation.

Fig. 4 is a kind of realization of the ATA register file of the controller of key diagram 3 in more detail.

Most preferred embodiment describes in detail

The first half of Fig. 1 has illustrated that the typical prior art of ATA controller 10 is used in the personal computer, and it provides the interface between system bus 12 and the memory device 14.System bus 12 is pci buss.When logically being connected to pci bus, the ATA controller is integrated in the board chip set usually.For given application, other or additional controller can be inserted into one of them of pci bus slot (not shown) on the mainboard.Pci bus provides configuration mechanism, by this mechanism, unique address can be assigned to each controller.Typical control device 10 provides two channels, and they are terminated at a pair of

connector

16 and 18 that is designated basic, less important IDE connector respectively.Each secondary channel will be supported the memory device of a pair of shared connector and cable.For example, in Fig. 1, secondary channel cable 19 is connected to master control memory device 20 and from memory device 22.Another similarly is connected to primary channel cable 24 to driver.Like this, these two channel controllers 10 are supported four equipment altogether, as shown in Figure 1.

The DLL (dynamic link library) and the driver of the IDE controller that the explanation of the latter half of Fig. 1 is seen from the angle of pci bus.The physical address of each piece comes assignment by the pci bus configuration space of controller, and is such just as known in the industry, and is described in the Intel PCI IDE controller specification documents of quoting in front.Another Intel document of quoting from previously " DLL (dynamic link library) of bus master IE controller " has illustrated the DLL (dynamic link library) of bus master IDE controller.Before this machine-processed standardization, storage device data is normally transmitted by program control I/O, and wherein, data transmission is required be written into and store by system processor carried out.Though still support program control I/O mechanism, yet bus master interface allows the ATA controller by the direct access system storage, promptly by DMA, transmits data.Bus master IDE controller document has defined 16 block of bytes of register, and it supports a pair of bus master controller, and one is used for basic ATA channel, and one then is used for less important ATA channel.This block of registers is the ingredient of controller physically.As shown in the figure, it is divided into two

parts

30 and 32, one parts and each channels associated.

The ATA normalized definition store the DLL (dynamic link library) of storage equipment.This interface comprises two block of registers: command block and controll block.Command block is eight block of bytes of byte wide register.Controll block is the nybble piece of byte wide register.All of these registers realize that details all is published in the ATA standard.

The right side of Fig. 1 illustrates four group commands and control register piece, and group is corresponding to one of them of four memory devices that connected.For example, one group of block of registers 36 comprises command block 38 and corresponding controll block 40.These registers are the ingredient of the respective storage devices shown in Fig. 1 the first half physically.Like this, registers group 36 (primary channel) just is arranged in main storage device 25.If do not connect a given memory device, then its order and control register piece will can not appear in the DLL (dynamic link library).

The ATA standard has also defined the agreement that memory device is supported.In general, access command and all correlation parameters are loaded in the register of command block.Memory device will be carried out this order.Write for equipment, it will at first ask to write data.For program control I/O operation, primary processor will be from system storage reading of data, and use a part of command block as 16 bit window, described data are write impact damper (not shown) in this equipment.For bus master dma operation, the ATA controller will be according to the configuration of the bus master controller block of registers of channel, directly access data from system storage.Then access medium of memory device is transmitted data between medium and local buffer thereof.Read for medium, utilize above-mentioned program control I/O or bus master DMA, give system storage the data transmission in the local buffer.At last, memory device will interrupt by the ATA controller or by status register poll or employing, finish to host computer system indication operation.

When powering on, personal computer is carried out and physically is stored in the code in the nonvolatile memory on the mainboard.Basic Input or Output System (BIOS), promptly bios code loads PC operating system from the ATA memory device that is connected to the ATA controller, and provides rudimentary I/O system driver for such memory device.

The present invention simulates shown in Figure 1 and aforesaid ATA controller, and compatible fully at programming layer with it.Below with reference to Fig. 2, the first half of Fig. 2 is the block scheme according to controller of the present invention, and it can be configured to for example RAID controller.The left side of controller block 50 replaces standard double-channel ATA controller and is connected to pci bus, and simulates one to four ATA memory device that is connected.The emulation of the ATA memory device that will describe in detail below separates the host interface of controller with the physics equipment interface, sizable degree of freedom is being provided aspect device interface types that provide and the number of ports.For example, application of the present invention can realize X scsi port and/or Y ata port, and wherein, X and Y never are limited to four logical drives that occur in the host computer system.Fig. 2 is the example that realizes being numbered 0 to N-1 N+1 ata port.

The latter half of Fig. 2 illustrates DLL (dynamic link library) of the present invention.Host interface 56 realizes from visible all block of registers of angle of the pci bus of standard A TA controller: double-channel bus master controller piece 58,60 and four group # are respectively 62,64,66 and 68 order and control register piece.The register of host interface block 56 simulation ATA controllers and ATA memory device, simulation is to the layer of supporting that the ATA specification protocol is required.

The primary clustering of the piece 70 explanation controller blocks 50 of Fig. 2 lower part.Except host interface block 56, controller 70 also comprises RAM buffering cache memory 72, dma channel 74 and processor 80, will further specify below.Controller block 70 also comprises a plurality of ata port interfaces, and for example interface 82,84 and 86.Each ata port interface all provides standard interface to connect to the IDE types of storage devices such as disk drive.As previously described, each memory device comprises order and control register piece on mainboard.For example, they are described as command register piece 90 and controller block 92, the two is all related with individual equipment, and is promptly related with master driver, and they are connected with ata port interface 82, AN connector cable 96.Controller block 70 can be configured to comprise the ata port of any requirement, still provides standard double-channel control unit interface 56 to main frame pci bus 12 simultaneously.

Fig. 3 illustrates the more detailed block diagram of the present most preferred embodiment of the present invention.This system realizes as the CMOS technology of special IC (ASIC) with 0.18 micron.Described equipment logically is divided into four modules, and each module has the relevant port to device external.

Host interface 100 serves as that make with indium silicon on the basis with PCI core 104.CS6464AF is soft core (for the synthetic Verilog source of application-specific), and it supports 32 and 64 two kinds of pci buss, and pci bus clock speed is 33MHZ or 66MHZ.This core is supported main operation and object run.Target signature (target feature) 106 provides the access to the compatible register file of foregoing ATA.Main ability (master capability) 108 is used for simulating the bus master DMA feature of ATA controller.The PCI core comprises the configuration space of the configuration space 110 of simulated dual port ATA controller.

DRAM interface block 120 is supported the outside SDRAM 122 that connects.64 bit wides, the single data rate port one 24 of 100MHZ are supported the peak transfer rate of 800MBPS.In this locality, by through host interface 100 to or transmit from pci bus, by through driver interface 130 to or transmit from disk drive, can share the DRAM interface, and carry out access by the native processor in the processor piece 150.

Driver interface piece 130 provides five ata ports, and for example 134, each port all can be supported to advocate peace from driver.Each port support reaches the program control input and output (PIO) of 16MBPS transfer rate and the Ultra DMA that reaches the 100MBPS transfer rate.

The processor piece is made by the LSI logical circuit around EZ4102 TinyRISC core 160.This processor is the variant of MIPS processor.When powering on, processor loads code from the outside short-access storage 162 that carries out access by expansion bus port one 66.This code is transferred to the SRAM piece 170 in the processor piece.Other each modules of processor 160 configuration, and by these modules, it can the access pci bus, SDRAM or ATA driver.In general, do not come deal with data by requiring processor, system transmissions speed is enhanced.Processor loads or unloads therebetween FIFO 148 by disposing DMA engine 136,146 in these pieces, and the data of coordinating between driver and the DSRAM transmit.Similarly, it comes FIFO 174 between these pieces of loading or unloading by the DMA engine 172,102 in configuration DRAM interface and the host interface, coordinates the transmission between SDRAM and the pci bus target.

Fig. 4 illustrates that the ATA register file realizes details.Register all is a dual-port, and can carry out access from pci bus by host computer system or by native processor 160.From the angle of pci bus, each ATA channel has relative two block of registers.Command block 208 is Eight characters adjusting ranges of byte wide register.Controll block 210 is nybble scopes, wherein only uses single storage unit.As previously mentioned, single ata port can be used for a pair of driver that is connected to common cable of access.Each equipment all has its oneself order and control register piece.Equipment has disposed wire jumper physically so that one of them is appointed as the master, and with another be appointed as from.By with in the equipment title register of a byte data with address offset amount six write command pieces, select a specific equipment to be used for access.If statement is position four,, selects slave unit and cancel the selection main equipment then for subsequently operation.If same register is write, its meta four is eliminated, and then selects main equipment, and slave unit is selected in cancellation.In order to simulate this behavior in the present invention, realize advocating peace from registers group.In addition, provide single-bit from register 230, it writes down the position four of nearest write device title register.Read multiplexing and write address decoding from register controlled from pci bus, thereby will come the suitable block of registers of access right according to nearest choice of equipment.

When powering on or after resetting, ATA equipment is initially busy.By the status register of address offset seven in the reading order piece, or read stand-by state block of registers in the controll block, can detect busy condition.When device busy, there is not other the register can be by access.In order to simulate this behavior in the present invention, provide individual bit busy register 232.By resetting,, perhaps when the address offset seven write command registers of command register piece, this register is set by to the writing of the warm reset bit in the device control register of controll block from pci bus.Native processor can be removed busy register.

If allowed to interrupt in equipment, then each ATA equipment can be declared interrupt request to host computer system.In order to simulate this behavior, for the slave unit of advocating peace provides individual bit interrupt request 234 and interrupts allowing 236 registers.Controlling interruption by the device control register of each equipment allows.Each equipment can be declared interrupt request to host computer system, so that transmit data or return completion status.In the present invention, interrupt request can be provided with or be removed by native processor.By the status register (but not being the stand-by state register) of fetch equipment, also interrupt request is removed, as described in the agreement of ATA standard.Advocate peace slave unit interrupt request and interrupt enable state and can keep independently, thereby when main frame changes choice of equipment, can obtain suitable behavior.

For secondary channel, the order of the slave unit of advocating peace and control register file and from, busy, interrupt " edge effect " and all be replicated.The order of all four equipment and control register blocks of files all are mapped in the address space of native processor linearly.

The double-channel bus master controller piece of sharing 250 can carry out access from pci bus or by native processor.

According to the ATA agreement, selection equipment, all required parameters of given order all are loaded onto the command register file, should order itself also be written into described register with side-play amount seven subsequently.As mentioned above, this will be provided with channel for busy.Busy rising edge causes the interruption to native processor, and native processor will respond by explaining this order and parameter thereof.Most of orders will be remapped to connect the access of physical equipment array.These accesses can be used for realizing any public RAID agreement, include, but are not limited to RAID0,1,3 and 5.Native processor has the option that reads more than the data of being asked.Additional data is stored among the SDRAM in advance in order to reading subsequently.Native processor can use program control IO or DMA to be arranged in data transmission between SDRAM and the host computer system by order request.

In a word, the present invention includes the raid storage devices controller, host interface is provided, be used for controller is connected with host system bus.Host interface with for example as the IDE disk drive the isolation of company memory device, make the driver of actual connection not be subjected to the restriction of quantity or interface protocol.The various device port can be realized, and various RAID strategies, for example RAID3 and RAID5 can be used.In all cases, host interface provides the standard unified interface to main frame, i.e. ata interface, preferably double-channel ata interface.Host interface simulation ATA single channel interface or double-channel interface, and simulate one or two the IDE equipment that each channel connects, and regardless of physically with the actual quantity of this controller connection device.For example, so just five or seven IDE drivers can be in RAID5, disposed, and the standard BIOS in the host pci need not be changed.Like this, the RAID controller is transparent for the double-channel ATA controller board of standard.

Those skilled in the art under the situation that does not break away from cardinal rule of the present invention, can carry out many changes with clear to the above embodiment of the present invention details.Therefore, scope of the present invention should be defined by appended claim.

Claims

1. storage device controller, it comprises:

Host interface is used for described controller is connected with host system bus, described host interface mock standard IDE channel, and simulation is like the IDE equipment that is connected to described IDE channel; And

At least one physical interface is used for described storage device controller is connected with physical storage device.

2. storage device controller as claimed in claim 1, it is characterized in that described physical interface wherein at least one realizes being used for ata port the ATA compatible storage device is connected to described controller.

3. storage device controller as claimed in claim 1 is characterized in that described host interface simulates at least one primary channel and secondary channel.

4. storage device controller as claimed in claim 3 is characterized in that described host interface simulation is connected to the single IDE equipment of each described fundamental sum secondary channel.

5. storage device controller as claimed in claim 3 is characterized in that described host interface is simulated main IDE memory device and from the IDE memory device, described main IDE memory device and be connected to one of them of described fundamental sum secondary channel from the IDE memory device.

6. storage device controller as claimed in claim 3 is characterized in that also comprising the device of the bus master's dma controller that is used for mock standard dual-port IDE controller.

7. storage device controller as claimed in claim 1 is characterized in that described host interface simulation is connected to the single IDE equipment of described IDE channel.

8. storage device controller as claimed in claim 1 is characterized in that the simulation of described host interface is connected to the main IDE memory device of described IDE channel and from the IDE memory device.

9. storage device controller as claimed in claim 1 is characterized in that also comprising the device of the bus master's dma controller that is used for mock standard dual-port IDE controller.

10. raid storage devices controller, it comprises:

Host interface is used for described controller is connected with host system bus, and described host interface is simulated at least one ATA controller channel;

Described host interface also by realizing that IDE complies with order and control register piece, is simulated like at least one the IDE equipment that is connected to described emulation ATA controller channel;

At least two physical interfaces are used for described storage device controller is connected to a plurality of memory devices; And

Native processor in the described controller is used to control the physical storage device accessing operation.

11. raid storage devices controller as claimed in claim 10 is characterized in that also comprising the device of the bus master's dma controller that is used for mock standard dual-port IDE controller.

12. raid storage devices controller as claimed in claim 10 is characterized in that also comprising: memory buffer is used for the data transmission between the memory device of described host system bus of buffer memory and described connection; And the DMA engine, it is arranged to transmit data between described host interface and described memory buffer.

13. raid storage devices controller as claimed in claim 12 is characterized in that comprising the DMA engine, it is arranged to transmit data between described memory buffer and port interface.

14. raid storage devices controller as claimed in claim 10 is characterized in that described host interface simulates basic ATA channel and less important ATA channel.

15. raid storage devices controller as claimed in claim 14 is characterized in that described host interface simulation is connected to the single IDE equipment of each described fundamental sum secondary channel.

16. raid storage devices controller as claimed in claim 14, it is characterized in that described host interface is simulated main IDE memory device and from the IDE memory device, described main IDE memory device and from the IDE memory device be connected to described fundamental sum secondary channel wherein at least one.

17. raid storage devices controller as claimed in claim 10 is characterized in that the simulation of described host interface is connected to the main IDE equipment of described IDE channel and from IDE equipment.

18. raid storage devices controller as claimed in claim 10 is characterized in that described host interface simulation is connected to the single IDE equipment of described IDE channel.

19. raid storage devices controller as claimed in claim 10 is characterized in that the simulation of described host interface is connected to the main IDE memory device of described IDE channel and from the IDE memory device.

20. need not revise existing host B ios software and come raid storage devices controller and the method that the pci bus main frame is connected be said method comprising the steps of for one kind:

In described controller, simulation is connected to the ATA controller of described main frame;

In described controller, also simulation is like the IDE memory device that is connected to described ATA controller;

At least two physical port interfaces are provided, are used for physical storage device is connected to described controller; And

The host interface of described controller is separated with described physical storage device, so that concerning described main frame, described storage device controller appears as the IDE equipment that connects via ata interface, and no matter be physically connected to the actual quantity and the interface type of physical storage device of the described physical port interface of described controller.