TW476030B - RAID controller system and method with ATA emulation host interface - Google Patents

Abstract

A RAID storage device controller provides a host interface for interfacing the controller to a host system bus. The host interface is isolated from the attached storage devices, for example IDE disk drives, so that the actual attached drives are not limited in number or interface protocol. Various device ports can be implemented, and various RAID strategies, e.g. level 3 and level 5, can be used. In all the cases, the host interface provides a standard, uniform interface to the host, namely an ATA interface, and preferably a dual channel ATA interface. The host interface emulates the ATA single or dual channel interface and emulates one or two attached IDE devices per channel, regardless of the actual number of devices physically connected to the controller. Thus, for example, five or seven IDE drives can be deployed in RAID level 5 protocol without changing the standard BIOS in a PCI host machine. Thus the RAID controller is transparent relative to a standard dual channel ATA controller board.

Description

476030 Printed by A7 B7 on consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of invention (ί) Related applications This application is a serial application and has been applied for in the US Provisional-Application 41 on September 22, 1999. 60 / 156,001 claims priority. FIELD OF THE INVENTION The present invention relates to a computer data storage device controller, and more particularly, to a RAID controller having a host interface of an analog ATA standard controller and a connected IDE device. The back of the invention The first IBM PC and compatible models had only one floppy disk drive for mass storage. The following XT and AT models included adapters for 5.25-inch fixed disks (non-removable) for mass data storage. These original adapters provided most of the low-level control signals for drives with data separation circuits, which were used for the read signal and the pre-compensated write signal. Including these features in the adapter avoids repeated actions in a pair of drives that only access one at a time. Unfortunately, when the technology improves, the 5M bit read / write on the adapter does not allow faster drives to be connected. Moving the "instant" view of the controller into the drive system solved the problem. The integrated drive circuit or IDE drive includes all the controls and data channels needed to read or write the drive, and the drive is in an area buffer and Information is transferred between the media. The manufacturer can choose the data transfer rate. A new interface ΑΑ (with a package of 4 paper sizes applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) '----------------- line (please (Please read the notes on the back before filling this page) 476030 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Attachment (,) AT Attachment (ΑΤΑ / ΑΤΑΡ1 · 4)) (ΙΒΜ, Α.Ι _Add-on device interface) is customized as a link between the data storage device and the host system. The earliest IDE interface at most consisted of the address between the ISA bus and the ATFA cable connector and the buffer. The interface protocol uses stylized output and input commands to access the registers of the IDE device. Data transmission uses the host processor's input string and output string instructions to adjust the transfer rate to the connected drive. These transmission rates reached 16 Mbytes per second in later versions. This is the transfer rate between the buffer area in the storage device and the memory on the ISA bus. The transfer rate between the media and the buffer is much lower. With the advent of the PCI bus, Intel released the PCI IDE file (PCI IDE controller specification, version 1.0, 3/4/94), which provides a host interface based on the previous ISA bus to the PCI bus A standard mapping of rows. This standard describes a dual IDE channel controller. A pair of devices, the master device and the slave device can be connected to each of the channels. For data transfer, the device is still accessed as a PCI bus target.

Intel also released the IDE file for the bus master device (programmed interface for the bus master device IDE controller, version 1.0, 5/16/94). This document defines a standard for incorporating DMA devices into IDE channels. The bus master device interface allows the IDE channel to transmit data to and from the system memory on the PCI bus like the same bus master (PCI bus initiator). For memory access, the PCI bus peak-to-peak burst rate is 133M bytes per second. 5 ^ ^ -------- Order --------- ^ IAWI (Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) '476030 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (3) A version of the ATAA specification defines a new transmission mode' Ultra DMA. Conventional transfer rate improvements have been achieved by tightening the setup and hold times required for data transfer over the cable. At 16M bytes per second, the read transmission rate is strictly limited by the round trip of sending the read selection signal, obtaining the data, and returning the data. The Ultra DMA protocol initially maintains all signals and the electrical characteristics of the cable ', but merely re-defines three functions in the signal to provide a new protocol. In this agreement, the timing signal for providing data is sent from the same end as the data, in other words, it is sent by the controller when it is written, and it is sent by the device when it is read. In this structure, the transmission rate is limited only by the skew of the cable due to a single transition of the cable. The earliest UDMA devices doubled the stylized 10 transfer rate to 33M bytes per second. The next version doubles the initial UDMA transmission rate to 66M bytes per second, but requires an 80-wire cable with interleaved signals and ground wires. The current version supports a transmission rate of 100M bytes per second. A plan is now underway to replace the ATAA parallel interface with a high-speed serial connection, but a higher parallel speed increase may be published first. Legs A common personal computer is composed of a motherboard, which is designed around a chipset and includes: a processor, a DRAM interface, various input / output adapters, and a BIOS ROM. The 10 adapter usually includes an IDE interface. The current IDE controller version features a pair of IDE cards, each of which can communicate with a pair of IDE storage devices. These devices 6 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) L -------- ^ --------- ^ i ^ w— (Please read first Note on the back, please fill out this page again) 476030 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (Dr) Usually contains one or more 1DE hard disks plus CD R0M, DVD ROM or CD WROM Drive. The basic input / output system or BIOS is a program that starts the PC and provides a low-level 10 program for the adapter on the motherboard. Basically all of these PCS can be booted and operated from an IDE hard disk using the motherboard's BIOS. Gradually, personal computers are being distributed to servers or workstations in the small office / home office (S0H0) market. Historically, hard drives with small computer system interface (SCSI) have provided some performance gains for these more demanding applications. However, 'Since more than 85% of all drives are made as IDE drives today, this SCSI drive tends to use the same media and read / write head construction, and it has a large or increased cost with little or no performance gain. . Another popular alternative is to use a redundant array of inexpensive disks (RAID), first proposed by Patterson (D. Patterson et al., "A redundant array of inexpensive disk arrays ( Example of RAID), University of California Report No. UCB / CSD87 / 391, December 1987). The RAID system addresses guilty and performance issues. First of all, the reliability is obtained because the stored data is backed up on two or more drives, so if one drive is damaged, the data will not be lost. Second, performance gains are achieved because the collective performance of the array is relative to a single drive. The backup data of different sectors can be read out by two drives at the same time. Data can also be written to stripes across all available drives, so when the data is read back, the transfer rate of the collection can be known. The RAID array controller is further described in the inventor's U.S. Patent No. 6,018,778. 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)-"-------------- Order · -------- Line (Please (Read the precautions on the back before filling this page) 476030 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (<) Unfortunately, there are some disadvantages to these available RAID solutions. Area The use of smart devices and SCSI disk drives is a feature of a type of RAID solution. Although this type has high performance, the cost of the disk drive and controller is quite high. Other popular RAID solution types The feature is the use of an IDE drive without any regional smart devices or buffers. This is basically a software solution. All software that needs to control many drives to get backups or stripe data must be on the host Execution on the system is to greatly increase the redundant actions of the drive on the processor and the system bus. Therefore, due to the increased redundant actions, the cost of obtaining the benefits of RAID is to reduce system performance. These two solution There is an additional problem with these methods. These RAID controllers are not directly supported by the motherboard's BIOS. Additional software drivers are required. These drivers may vary depending on the operating system, such as Windows, Windows NT , UNIX, LINUX, etc., impose an additional burden on controller manufacturers, OEMs, market groups, and system integrators. 'Therefore, the need is for special software that does not need to be executed on the host processor, There is also no need for additional software drivers or RAID storage controller changes to the BIOS. A RAID controller that does not require a BIOS change will have true compatibility with almost all standard, existing computers with an ΑΑ compatible interface "Plug and play" advantages. The RAID controller is transparent to the host, and can be configured with multiple storage devices (not limited to four) in any combination of device interfaces, and can be made into a RAID mirror , Striping, etc., without the need to increase the redundant action of the host. Such RAID control 8 paper size applies to China National Standard (CNS) A4 specifications (210 X 297 Mm) " a '·-^ -------------- ^ --------- line (please read the precautions on the back before filling this page) 476030 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (v) The device will bring the ability of RAID to all PC users at a low cost, and the installation is also very simple. A RAID controller compatible with all operating systems capable of booting and executing on a PC motherboard using a standard IDE controller and an IDE drive. It achieves this compatibility by mimicking the standard controller and the attached disk drive. For example, a particular system may require a pair of drives or a "mirror" organization in a RAID1 for reliability. When connected to the controller described in this invention, the BIOS will see a single, very reliable drive. The same system may also require an array of three drives to form a RAID3 or RAID5 configuration. This will provide twice the transfer rate of any of the three drives with a high reliability. Again, in the present invention, the three-drive array will be treated as a single drive to the BIOS, and the drive will display twice the capacity of either of the two drives, And it has twice the speed of high reliability. In any case, the RAID is transparent to the drivers present in the BIOS. The thin device of the present invention simulates the standard two-channel IDE controller. Like the standard controller, it is logically linked to the PCI bus. It can be actually installed on the motherboard, it can be accumulated in the chipset of the motherboard, or on a card in a PCI slot. It simulates all four devices that can be connected to this standard controller. Each of these logic devices provides a potential interface to an array of physical devices connected to the controller. Although this implementation 9 this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) -------- Order ----- Printed on line 476030 by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. Α7 Β7 V. Description of Invention (< \) The example provides the ΑΤΑ port as a link to a physical drive, but other types of interfaces or combinations of interfaces can also be used. Other objects and advantages of the present invention will be made clearer by the following detailed description of the preferred embodiments, which description is made with reference to the accompanying drawings. Attached_A brief description of the chaos Figure 1 is a simplified block diagram of the ATP two-channel controller application of a known technology, which shows the physical and software / register view. FIG. 2 is a simplified block diagram of one of the RAID controllers with ATA port emulation according to the present invention. FIG. 3 is a high-level block diagram of a currently preferred commercial embodiment of a RAID controller with ATA port emulation. FIG. 4 is a detailed view showing an embodiment of an ATAA register box of the controller of FIG. 3 in detail. 1〇 · ΑΤΑ dual-channel controller 12.PCI bus M · connector M.connector M · secondary channel cable 20. master storage device 22 · slave storage device 24. main channel cable 10 This paper standard China National Standard (CNS) A4 specification (210 X 297 mm) L .-------------- ^ -------- (Please read the notes on the back before filling (This page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476030 A7 _B7_ V. Description of the invention ($) 25. Main device 26. Secondary channel cable 30. Bus main device controller 32. Bus main device controller 36. Register block 38. Command block 40. Control block 50. RAID controller block with ΑΤΑ 璋 simulation 56. Dual channel controller interface block, 58. Bus master device 0 Controller block 60. Bus master Device 1 controller block 62. command and control register block 64. command and control register block 66. command and control register block 68. command and control register block 70. controller block 72. RAM buffer Area cache memory 74.DMA channel 74 80.Processor 82.ΑΤΑ port interface 84.ΑΤΑ port interface 86.ΑΤΑ port interface 90.Life Box 92. Control box This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---- " — ^ -------------- Order --- ------ line " 41 ^ " (Please read the notes on the back before filling out this page) 476030 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7_ V. Description of Invention (5) 96. Connection Server cable 100. Host interface 102. DMA engine 104. IN-SILICON CS6464AF PCI core 106. Target characteristics 108. Main device functions β 110. Configuration space 120. DRAM interface block 122. SDRAM 124. 64-bit data 璋 130. Magnetic Drive interface 134.ATA if 136.DMA engine 144.Bus 146.DMA engine 148.FIFO 150.Processing block 160.EZ4102 RISC 162.Flash memory 166.Extended bus interface 170.SRAM 172.DMA engine 174 .FIFO 200.ΑΤΑ temporary storage box 12 (Please read the precautions on the back before filling in this page) Φ clothing --------order --------- line · This paper size is applicable to China National Standard (CNS) A4 Specification (210 X 297 mm) 476030 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (V. ) 230. Slave register 232. Busy register 234. Master device interrupt request register 236. Master device interrupt enable register 250. Bus master device control block details of a preferred embodiment of the block diagram of Figure 1 The upper part depicts the application of an ATAA controller 10, which is a typical conventional technique in a personal computer. The ATAA controller 10 provides an interface between the system bus 12 and the storage device 14. The system bus 12 is a PCI bus. When logically connected to the PCI bus, an ATAA controller is usually integrated into the motherboard chipset. For a particular application, an alternative or additional controller can be plugged into a PCI bus slot (not shown) on the motherboard. The PCI bus provides a configuration mechanism through which unique addresses are assigned to individual controllers. A typical controller 10 provides two terminations to a pair of connectors 16, 18, which are referred to as the channels of the primary and secondary IDE connectors. Each channel will support a pair of storage devices that share the connector and the cable. For example, in FIG. 1, the secondary channel cable 19 is connected to a master storage device 20 and a slave storage device 22. Another pair of disk drives is similarly connected to the main channel cable 24. The dual-channel controller .10 thus supports a total of four devices, as shown in Figure 1. The lower half of Figure 1 shows the programmed interface of the IDE controller and drive, as seen by the PCI bus. The actual address of each square is through 13 ri -------- ^ --------- (Please read the precautions on the back before filling this page) This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) " 476030 A7 B7 V. Description of the invention (v \) This controller is designated by the PCI bus configuration space, which is well known in the industry and is cited in the aforementioned Intel PCI IDE controller specification. Other previously cited Intel documents, namely, the programmatic interface for the bus master IDE controller, describe the programmatic interface for the bus master IDE controller. Prior to standardizing this mechanism, storage device data was usually transmitted through programmatic I / O, where the loading and storage required for data transmission were performed by the system processor. Although the stylized I / O mechanism is still supported, the bus master device interface allows the ATAA controller to transfer data through direct memory access, that is, DMA. The bus master device IDE controller file defines a 16-byte register block that supports a pair of bus master device controllers, one for the main ATTA channel and one for the secondary ΑΑΑ channel. The register block is the physical part of the controller. As shown it is divided into two elements, 30 and 32, each associated with a respective channel. The ATAA specification defines a programmatic interface for the storage device. The interface consists of two register blocks: the command block and the control block: The command block is an 8-byte wide register block. The control block is a 4-byte wide register block. All implementation details of these registers are disclosed in the ATAA specification. The right side of Figure 1 shows four groups of command and control register blocks, each group corresponding to one of the four connected storage devices. For example, a set of register blocks 36 is composed of a command block 38 and a corresponding control block 40. These registers are shown in the physical part of the corresponding storage device in the upper half of FIG. Therefore, the register group 36 (main channel) is located in the main 14 paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love 1 (please read the precautions on the back before filling this page). Printed by the Consumer Cooperative of the Property Bureau • 1111111 · 11111111 I AVI — — — — — — — — — — — — — — 476030 Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs Α7 Β7 V. Description of Invention (γ) In the storage device 25. If a specific storage device is not connected, its commander and control register box will not appear in the programming interface. The ATTA specification also defines the supported by the storage device Agreement. Generally, an access command and all related parameters are loaded into the register of the command block. The storage device will then execute the command. For a device write, it will first request the write data. For the stylized I / O operation, the host processor will read the data from the system memory and write it to a buffer in the device (not shown), which uses the command block. Partly as a 16-bit window into the buffer. For DMA operation of a bus master device, the ATAA controller will be based on the configuration of the register block of the bus master device controller used in the channel. The data is accessed directly from system memory. The storage device then accesses the storage medium to transfer data between the medium and its area buffer. For a media read, the data in the area buffer then uses the above The programmed I / O or bus master device DMA transfers to the system memory. Finally, the storage device notifies the host system that the action has been completed through the ATAA controller, and the ATAA controller temporarily stores the status by inquiring The device may be informed by an interrupt signal. When the computer is turned on, the personal computer executes the execution code that is actually stored in the non-volatile memory of the motherboard. The basic input / output system or BIOS code is connected to the ATFA controller by ATFA The storage device is loaded into the personal computer operating system, and a low-level I / O system driver for the storage device is provided. The simulation of the present invention is shown in FIG. 1 And the above ATAA controller, and is completely compatible with it in this stylized level. Now refer to Figure 2, above Figure 15 15 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)- --1 —: ----------------------- ^ —Aw] (Please read the notes on the back before filling this page) 476030 A7 _____B7___ V. Description of the invention () The half is a block diagram of a controller according to the present invention. For example, it can be organized as a RAID controller. The left side of the controller block 50 is connected to the PCI bus instead of a standard. Dual channel ATAA controller to simulate 1 to 4 connected ATAA storage devices. The ATFA storage device simulation (described in more detail below) separates the host interface of the controller from the physical device interface, thus allowing considerable freedom in the types and number of device interfaces that can be provided. For example, an application of the present invention may provide X SCSI volumes and / or ΑΑΑτ, where X and volumes are not limited to the presence of 4 logical drives in the host system. Figure 2 is an example of providing N + 1 ATAA ports, numbered from 0 to N. The lower half of FIG. 2 illustrates the stylized interface of the present invention. The host interface 56 provides all the register blocks seen from the PCI bus of the standard ATA controller: the dual-channel bus master device controller blocks 58, 60 and four sets of command and control register blocks 62, 64. , 66, and 68. The host interface block 56 simulates the register of the ATAA controller and the ATAA storage device to the level required to support the ATAA specification agreement. 'Block 70 in the lower half of FIG. 2 illustrates the main components of the controller block 50. In addition to the host interface block 56, the controller 70 includes: a RAM buffer cache 72, a DMA channel 74, and a processor 80, as further described below. The controller block 70 further includes a plurality of ATFA interfaces, such as interfaces 82, 84, and 86. Each ATA port interface provides a standard interface to an IDE storage device, such as a disk drive. As explained previously, each storage device contains command and control register blocks on the board. As an example, order 16 (please read the precautions on the back before filling this page), 1 order --------- The size of thread paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476030 A7 __ B7 V. Description of the invention (fire) Register block 90 and control block 92, both of which are related to a single device, that is, the main drive, which will be It is connected to the ATFA interface 82, the standard connector cable 96. The controller block 70 can be organized to contain any desired number of ATAA ports, while still providing a standard dual-channel controller interface 56 to the host PCI bus 12. A detailed block diagram of a presently preferred embodiment of the present invention is shown in FIG. The system is provided by a special application integrated circuit (ASIC) manufactured in a 0.18 micron CMOS process. The device is logically divided into 4 modules, each with an associated port connected to the outside of the device. The host interface 100 is constructed around a PCI core 104 from In-Silicon. CS6464AF is a software core (synthesized as a Verilog source for special applications). It supports 32-bit and 64-bit PCI buses at 33MHZ or 66MHZ PCI bus clock rates. The core supports the host device and target operations. The target feature 106 provides access to an ATAA-compatible scratchpad as previously discussed. The master device function 108 is used to simulate the characteristics of a bus master device DMA of an ATAA controller. The PCI core includes a configuration space 110 that simulates a configuration space 110 of a dual-port ATAA controller. The DRAM interface block 120 supports externally connected SDRAM 122. The 64-bit wide, 100MHZ single data rate port 124 supports peak transmission rates of 800M bytes per second. Regionally, the DRAM interface is passed to and from the PCI bus through the host interface 100, to and from the drive through the drive interface 130, and from the area processor in the processor block 150. Shared by access. 17. Κ Order --------- ^ IAW1 (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau, 476030 A7 B7_______ V. Invention Description (4) The drive interface block 130 provides 5 ΑΤΑ134, such as 134, each of which can support a master and slave drive. Each port supports stylized input and output (PIO) with a transfer rate of up to 16 megabytes per second and Ultra DMA with a transfer rate of up to 100 megabytes per second. The processor block is built around the EZ4102 TinyRISC core 160 manufactured by LSI Logic. The processor is a modification of the MIPS processor. When booting, the processor loads the code from an external flash memory 162. The memory system is accessed through the extended bus port 166. The code is transmitted to the SRAM block 170 in the processor block. The processor 160 organizes various other modules, and through these modules, it can access the PCI bus, the SDRAM, or the ATA drive. Generally, the system transfer rate is accelerated because the processor is not required to process the data. The processor coordinates the data movement between the drive and the SDRAM by organizing the DMA engines 136, 146 in these blocks to load or unload the FIFO 148 therebetween. In the same way, it coordinates the transfer between the SDRAM and the PCI bus target by organizing the DRAM interface and DMA engines 172, 102 in the host interface to load or unload FIFOs 174 between these blocks. Figure 4 shows the implementation details of the ATAA register box. The registers are all dual-ported, and can be accessed from the PCI bus by the host system or the area or the domain processor 160. As seen from the PCI bus, each ATAA lane has two register blocks associated with it. The command block 208 is a register with a width of one bit and a size of eight bytes. The size of the controller block 210 is 4 bytes, of which only one position is used. Same as the previous 18 paper ruler ^ Applicable to China National Standard (CNS) A4 (210 X 297 mm) ----_ — ^ -------------- Order ---- ----- (Please read the notes on the back before filling this page) 476030

V. Description of the Invention (A single ATAA port described by v \ o can be used to access a pair of devices connected to ordinary cables. Each device has its own command and control register block. The lines are actually organized to designate one master or the other as a slave. By writing a byte of data to the device's head register at an address of 6 in the command box, a specific device Is selected for access. If the 4th bit is set, the slave device is selected for continued operation, the master device is not selected. If the same register is selected in the 4th bit After being written, it becomes that the master device is selected and the slave device is not selected. In the present invention, in order to simulate this behavior, the master and slave register groups are provided. In addition, a single The bit slave register 230 is provided to record the last bit written to the device's head register. The slave register controls read multiplexing and write addresses from the PCI bus. Decode so that the appropriate pair of registers The block will be accessed according to the most recent device selection. At power-on or following a reset action, the ATAA device is initialized to a busy state. The busy state can be shifted to 7 by reading the address in the command block The state register or the alternative state register block in the control block is detected. When a device is busy, no other register can be accessed. In order to simulate this behavior in the present invention 'A single-bit busy register 232 is provided. The register is set by resetting from the PCI bus and writing a soft reset bit in the device control register to the control block. Or when the command register is written at the address shift 7 of its command register block. The area processor can eliminate the busy register. 19 This paper size applies the Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) Printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs ----- H ϋ ί One bite, I nnn I n I line I, ----------------- 476030 A7 B7 ^ ___ The Ministry of Economic Affairs and the Intellectual Property Bureau of the People's Republic of China printed a description of the invention (Λ) If the interrupt in each ATAA device is enabled, it can issue an interrupt request to the host system. To simulate this behavior, a single-bit interrupt request 234 And the interrupt enable 236 register has been provided in the master and the slave device. The interrupt enable is controlled by the device control register of the individual device. Each device can issue the interrupt request to the host The system transfers data or returns the completion status. In the present invention, the interrupt request can be set or cancelled by the area processor. The interrupt request can also be read by reading the status register of the device (but not the Substitute Status Register), as described in the agreement of the ATAA specification. The interrupt request and interrupt enable status in the master and slave devices are independently controlled, so when the host changes the device's choice, it can get proper behavior. The command and control register bins for the master and slave devices as well as the slave, busy, and interrupt "side effects" are all repeated in this secondary channel. The command and control register boxes for all four devices are all mapped linearly to the address space of the processor in the area. The shared dual-channel bus master device control block 250 may be accessed from the PCI bus or accessed by the regional processor. According to the ATAA agreement, after a device is selected, after all parameters required for a particular command are loaded into the command register box, the particular command itself is loaded into the register at shift 7. As mentioned above, this will set the channel to busy. The rising edge of the busy signal causes an interrupt signal to be sent to the regional processor, which will parse the command and its parameters in response. Most commands are remapped to access the selected array. This access can be used to implement any common raid agreement, including (but not limited to) levels 0, 1 20 (please read the notes on the back before filling this page) I- ϋ ϋ > Γ _ _t 衣 订 ---- ----- Line · This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 476030 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Invention Description (J), 3, and 5 . The area processor has the option to read more data than required. The additional data is temporarily stored in the SDRAM and is expected to be read next time. When requested by the command, the area processor can schedule a programmable 10 or DMA to transfer data between the SDRAM and the host system. In summary, the present invention includes a RAID storage device controller, which provides a host interface for communication between the controller and a host system bus. The host interface is isolated from the connected storage device, such as an IDE disk drive, so there are no restrictions on the number and agreement of the actual connected disk drives. Various device ports can be provided, and various RAID policies such as level 3 and level 5 can be used. In all examples, the host interface provides a standard, uniform interface to the host, known as an ATAA interface, and preferably a dual channel ATAA interface. The host interface simulates a single or dual channel interface and simulates one or two connected IDE devices per channel, regardless of the number of devices actually connected to the controller. Therefore, for example, 5 or 7 IDE drives can be set in the RAID level 5 protocol without changing the standard BIOS in a PCI host interface. Therefore, the RAID controller is transparent relative to a standard dual-channel ATA controller board. It is obvious to those skilled in the art that the details in the foregoing embodiments of the present invention can be changed without departing from the basic principles thereof. Therefore, the scope of the present invention is determined by the following patent application scope. 21 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ----- 1--Κ -------------- Order ------ --- Line f Jing first read the notes on the back before filling out this page)

Claims (1)

476030 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 _S__ VI. Patent Application 1. A storage device controller, which includes: a host interface, which is used to interface the controller with a host system bus The host interface simulates a standard IDE channel and also simulates an IDE device connected to the IDE channel; and at least one physical interface used to connect the storage device controller to a physical storage device. 2. As for the storage device controller of the first patent application scope, at least one of the physical interfaces is made as an ATAA port for connecting an ATAA compatible storage device to the controller. 3. For example, the storage device controller of the scope of patent application, wherein the host interface simulates at least one main channel and a secondary channel. 4. The storage device controller of item 3 of the patent application, wherein the host interface simulates a single IDE device connected to each of the primary and secondary channels. 5. For the storage device controller of the third scope of the patent application, the host interface simulates both a primary IDE storage device and a secondary IDE storage device, and the two are connected to the primary channel and the secondary channel. one of them. 6. If the storage device controller of item 3 of the patent application scope, it further includes a mechanism for simulating the bus master DMA controller of a standard dual-port IDE controller. 7. The storage device controller of item 1 of the patent application, wherein the host interface simulates a single IDE device connected to the IDE channel. 8. If you apply for the storage device controller of item 1 of the patent scope, where _ ^ _ 1 ____ This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this purchase ), 1T line 476030 8 8 8 8 ABCD VI. Patent application scope The host interface simulates both a master IDE storage device and a slave IDE storage device connected to the IDE channel. 9. The storage device controller of item 1 of the patent application scope further includes a mechanism for simulating a bus master device of a bus master device, which is one of the standard dual-port IDE controllers. 10 · —A storage device controller includes: a host interface, which is used to interface the controller with a host system bus, the host interface simulates at least one ATP controller channel; the host interface is made into an IDE Compatible commands and control register blocks to further simulate at least one IDL · device connected to the simulated ATA controller channel; at least two ports for connecting the storage device controller to a plurality of storage devices An interface; and an area processor, which is attached to the motherboard as a controller for controlling the access operation of the storage device. 11. The storage device controller of claim 10, further comprising a mechanism for simulating a bus master DMA controller of a standard dual-port IDE controller. 12. The storage device controller according to item 10 of the patent application scope, further comprising: a buffer memory system for buffering data transfer between the host system bus and the connected storage device; and a DMA engine system It is arranged as a data transfer between the host interface and the buffer memory. 13 · If the storage device controller of item 12 of the patent scope is applied, the paper size is also applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau, 476030 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, A8 B8 C8 _ D8 __ VI. The scope of patent application includes a DMA engine which is arranged as the buffer memory and between the interface. Data transmission. H. The storage device controller according to item 10 of the patent application scope, wherein the host interface simulates both an ATP channel and a secondary ATP channel. 15. The storage device controller according to item 14 of the patent application scope, wherein the host interface simulates a single IDE device connected to each of the primary channel and the secondary channel. 16. The storage device controller according to item 14 of the patent application scope, wherein the host interface simulates both a primary IDE storage device and a secondary IDE storage device, which are connected to one of the primary channel and the secondary channel. * — ^ 〇17. If the storage device controller of item 10 of the patent application scope, the host interface simulates both a master IDE device and a slave IDE device connected to the IDE channel. 18. The storage device controller of claim 10, wherein the host interface simulates a single IDE device connected to the IDE channel. '19. The storage device controller according to item 10 of the patent application scope, wherein the host interface simulates both a master idE storage device and a slave UI storage device connected to the IDE channel. 20 · —A method for connecting a storage device to a PCI bus host without modifying the host BIOS software. The method includes the steps of: simulating an ΑΑΑ interfacing with the host in the controller. Controller; and _3 books and degrees are applicable to China National Standard (CNS) Α4 specifications (210X297 mm) — '(Please read the precautions on the back before filling this page) 1T- line 476030 A8 B8 C8 D8 6. The scope of patent application in this controller further simulates an IDE storage device as if it is connected to the ΑΑΑ controller, so the storage device controller appears to the host as if it was passed through an ΑΤΑ An IDE device connected to the interface without regard to the actual number of physical storage devices and the interface type actually connected to the controller. (Please read the precautions on the back before filling out this page). Install ·! Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs