KR19990074053A - Atapi (ID) RAID Controller - Google Patents

Abstract

The present invention implements a RAID controller in a much cheaper ATAPI method than a conventional SCSI method. Based on a PCI-connected ATAPI adapter, the existing adapter accesses only one channel of ATAPI at a time, whereas the existing adapter accesses only one channel at a time. The hardware is implemented to allow simultaneous access to the FIFO controller, and the FIFO controller is implemented to solve the synchronization problem in the PCI and ATAPI interfaces.

Description

Atapi (ID) RAID Controller

The present invention relates to a Redundant Array with Inexpensive Disks (RAID) controller, and more particularly, to an ATAPI type RAID controller employing the AT Attatchment with Packet Interface (ATAPI) -4 standard.

RAID systems have recently been developed as a concept of data backup using several inexpensive disks rather than one expensive hard disk for stable storage of data.

In general, RAID systems interface hard disks, CD-ROMs, and DVD-ROMs to computer systems, and adopt SCSI (Small Computer System Interconnect) method, which has higher data transfer speed and stability than IDE method. However, the conventional SCSI interface RAID controller has a disadvantage that the price is expensive. In addition, the recent development of the ATAPI-4 specification, which includes Ultra DMA and Cyclic Redundancy Check (CRC) specifications, also makes the IDE method comparable to SCSI in speed and stability.

An object of the present invention devised to solve the above problems is a function and data stripping (e.g., data recovery) that can easily recover when an error occurs when data stored in a hard disk, which is a secondary storage device of a PC, through data mirroring. In order to increase the data transfer rate of the ATAPI bus through striping, an inexpensive ATAPI RAID controller is provided.

1 is a block diagram of a RAID controller of the ATAPI method according to the present invention.

2 is a FIFO structure for an ATAPI RAID controller according to the present invention.

3 is a circuit diagram for synchronization of a PCI-connected ATAPI according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: PCI bus 11: slave controller

12: mast controller 13: EPROM

20, 64: FIFO 30: Interface

50, 51, 54, 56, 57: Mux 55, 58: Tri-State buffer

61, 62, 63: flip-flop

The RAID controller connects and controls the RAID hard disk, which is a host and an external storage medium, and provides various functions for speed improvement and error recovery. RAID has a data striping function that divides 32-bit PCI data into two 16-bit ATAPI data and then transfers data over two channels, which doubles the transmission speed of the ATAPI bus. This is called RAID-0. .

Data mirroring and parity storage are two ways to recover from a storage device failure. Data mirroring is called RAID-1 by storing the same data on two storage devices and then recovering data from another disk when one device fails. In order to minimize the storage required while backing up data, there is a parity storage method, which is also divided into several types.

In order to achieve the above object, the present invention implements an ATAPI RAID controller having a RADI-0 (data striping) and a RADI-1 (data mirroring) function using a PCI-connected ATAPI adapter. The adapter accesses only one of the two ATAPI channels at a time, whereas in the present invention, the hardware is implemented to access both channels at the same time, the FIFO controller is implemented accordingly, and the synchronization problem occurs in the PCI-connected ATAPI interface. Solved by.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a RAID controller of the ATAPI method according to an embodiment of the present invention. As shown in FIG. 1, the RAID controller exchanges data with a host through the PCI bus 10, which is configured as 32 bits. Commands for accessing the ATAPI device and data transfer in Programmed IO (PIO) mode are performed by the slave controller 11, and PCI bus mastering is performed by the master controller 12. Pass between FIFOs. BIOS for initialization operation including the Plug and Play (PnP) function of the RAID controller is stored in the EPROM 13 and moved to the system memory through the EPROM interface block 14 when the system is booted, and then executed. The controller contains various information necessary for operation. The information is transferred to the host or to the required block by the configuration interface block 15. IO space interface block 16 serves to map the address of the ATAPI port from the host to the address corresponding to the actual ATAPI device.

The DMA register 17 stores data necessary for a DMA operation, that is, a memory address in which data to be transferred is located, a data size, a transfer direction, and the like. The Multi Word DMA 18 controls the operation of the Multi Word DMA and performs the FIFO operation accordingly, and the Ultra DMA 19 block performs the Ultra DMA operation and the FIFO operation.

The PCI bus consists of 32 bits and the ATAPI bus consists of 16 bits. In order to facilitate data transfer between them, the FIFO 20 is composed of an upper 16 bit FIFO 21 and a lower 16 bit FIFO 22. The ATAPI bus 40 is composed of two channels, that is, a channel 0 ATAPI bus 41 and a channel 1 ATAPI bus 42. In order to implement a RAID function, the ATAPI bus 40 must be able to access two channels simultaneously. To this end, the interface 30 with the ATAPI adapter is implemented separately as an interface with each channel, that is, an interface 31 for channel 0 and an interface 32 for channel 1. It also has a special FIFO structure to perform RAID functions as well as general ATAPI adapter functions.

2 is a FIFO structure for efficiently performing an ATAPI adapter function and a RAID-0 and a RAID-1 function according to an embodiment of the present invention.

As shown in Fig. 2, in the write mode, 32-bit data is transferred from the PCI bus to the high-word FIFO 52 and the lower-word FIFO 53 via Mux (50, 51), respectively. Divided into 16 bits, it is transmitted to the ATAPI bus via Mux 54 and Tri-State buffer 55 again. The mux selects either the upper word or the lower word, and the tri-state buffer allows the two channels to be delivered either selectively or simultaneously (in the case of RAID).

In read mode, 16-bit data from ATAPI channel 0, channel 1, or both channels simultaneously (if RAID) is transferred to the FIFO via Mux (56, 57), which in turn is transferred to the PCI bus via Tri-State buffer (58). Is delivered to.

Since data transfers to and from the PCI bus are synchronized by a PCI clock (33MHz), PCI-attached ATAPI adapters are typically driven by the PCI clock. However, data transfer with the ATAPI bus is asynchronous by hand-shaking without a clock signal, so it is necessary to synchronize this asynchronous ATAPI data to the PCI clock.

When sending ATAPI device data, always send a strobe signal to tell the adapter that the data is valid. However, this strobe signal is not synchronized with the PCI clock and the FIFO is driven by the PCI clock, requiring synchronization.

3 is a circuit diagram for synchronization of a PCI-connected ATAPI in ultra DMA mode according to an embodiment of the present invention.

As shown in FIG. 3, the ATAPI-4 standard ultra DMA fetches data at both the rising edge and the falling edge of the strobe signal, thus doubling the strobe signal first. 60) and then patch the ATAPI data to generate a Latched_Data signal by flip-flop (61). This doubled strobe signal is also fetched by the doubled speed 65 PCI clock and then generated by the flip-flop 62 as a signal Data_Ready. In the Latched_Data signal, ATAPI data synchronized by the flip-flop 63 driven by the Data_Ready signal enters the FIFO 64. In this case, the doubled PCI clock has 15 nanosecond cycles, so in the worst case, data can come in and be stored in the FIFO within 15 nanoseconds, fully satisfying the ATAPI-4 specification. In addition, as in the present invention, the strobe signal is first synchronized to the PCI clock to patch ATAPI data, thereby solving setup and hold problems that may occur in flip-flops.

ATAPI RAID controller of the present invention can contribute to the popularization of the RAID controller by manufacturing at a much lower price without falling in terms of data transfer speed or stability. In addition, based on the general PCI-connected ATAPI adapter, both channels of the ATAPI bus can be accessed simultaneously to implement RAID-0 and RAID-1 functions, enabling both ATAPI adapters and RAID controller functions.

Claims (7)

PCI bus (10) to exchange data with the host, A slave controller 11 which delivers instructions for accessing the ATAPI device and PIO data; A master controller 12 that performs PCI bus mastering and transfers DMA data between the PCI bus and the FIFO, An EPROM (13) that stores the BIOS for initialization operations, including the PnP functionality of the RAID controller, An EPROM interface block 14 which causes the BIOS stored in the EPROM 13 to be moved to system memory upon system booting and then executed; A configuration interface block 15 for transferring various information required for operation of the RAID controller to a host or a block required internally; An IO space interface block 16 for mapping an address of an ATAPI port from a host to an address corresponding to an actual ATAPI device; A DMA register 17 for storing data necessary for a DMA operation; A multi-word DMA 18 that performs operations and FIFO operations on the multi-word DMAs; An ultra DMA block 19 that performs ultra DMA operations and FIFO operations, A FIFO 20 that facilitates data transfer between the PCI bus 10 and the channel 0 ATAPI bus 40 and the channel 1 ATAPI bus 41; and ATAPI type RAID controller, characterized in that consisting of an interface block (30) for accessing two channels of the channel 0 ATAPI bus (40) and the channel 1 ATAPI bus (41). The method of claim 1, The interface block 30 includes an interface 31 for channel 0 and an interface 32 for channel 1 to simultaneously access two channels of the channel 0 ATAPI bus 40 and the channel 1 ATAPI bus 41. ATAPI type RAID controller characterized in that. The method of claim 1, The FIFO (20) is an ATAPI RAID controller, characterized in that consisting of the upper word FIFO (21) and lower word FIFO (22). The method of claim 1, In the FIFO 20, 32-bit data is transmitted in 16 bits to the upper word FIFO 52 and the lower word FIFO 53 from the PCI bus through the Mux 50 and 51. The FIFO 20 transmits the Mux 54 and the Tri. Means for transmitting to the ATAPI bus via the state buffer 55, and in read mode, 16-bit data from ATAPI channel 0, channel 1, or both channels simultaneously is transmitted via the Mux (56, 57, 50, 51). 52) and means for transferring to the lower word FIFO (53) and to the PC bus through the Tri-State buffer (58). The method of claim 4, wherein The mux (54) selects one of the upper word and the lower word, and the tri-state buffer (55) is characterized in that the two channels can be selectively or simultaneously transfer RAID controller of the ATAPI method. The method of claim 4, wherein Data transfer with the ATAPI bus 40 is asynchronous, so ATAPI data RAID controller characterized in that to synchronize the ATAPI data to the PCI clock. The method of claim 6, A flip-flop 61 for doubling (60) an ultra DMA strobe signal (60) and then fetching the ATAPI data to generate a Latched_Data signal to synchronize the ATAPI data to a PCI clock; The doubled (60) strobe signal is a flip-flop (62) for generating a Data_Ready signal after being patched by a doubled (65) doubled PCI clock, The Latched_Data signal is a flip-flop 63 driven by the Data_Ready signal, and ATFI RAID controller, characterized in that consisting of a FIFO (64) for receiving the ATAPI data synchronized by the flip-flop (63).