WO2012169820A3 - Semiconductor storage device memory disk unit with multiple host interfaces - Google Patents

Semiconductor storage device memory disk unit with multiple host interfaces Download PDF

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Publication number
WO2012169820A3
WO2012169820A3 PCT/KR2012/004529 KR2012004529W WO2012169820A3 WO 2012169820 A3 WO2012169820 A3 WO 2012169820A3 KR 2012004529 W KR2012004529 W KR 2012004529W WO 2012169820 A3 WO2012169820 A3 WO 2012169820A3
Authority
WO
WIPO (PCT)
Prior art keywords
disk unit
controller
memory
storage device
memory disk
Prior art date
Application number
PCT/KR2012/004529
Other languages
French (fr)
Other versions
WO2012169820A2 (en
Inventor
Byungcheol Cho
Original Assignee
Taejin Info Tech Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/155,576 external-priority patent/US20110252250A1/en
Application filed by Taejin Info Tech Co., Ltd. filed Critical Taejin Info Tech Co., Ltd.
Publication of WO2012169820A2 publication Critical patent/WO2012169820A2/en
Publication of WO2012169820A3 publication Critical patent/WO2012169820A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays

Abstract

In general, embodiments of the present invention provide a Semiconductor Storage Device (SSD) memory disk unit having multiple host interface units. Specifically, in a typical embodiment, the SSD memory disk unit comprises a plurality of host interface units for coupling the SSD memory disk unit to at least one host; a host interface controller unit coupled to each of the plurality of host interface units; a DMA controller coupled to the host interface controller unit; an ECC controller coupled to the DMA controller; a memory controller coupled to the ECC controller; and a memory array coupled to the memory controller, the memory array comprising at least one SSD memory block.
PCT/KR2012/004529 2011-06-08 2012-06-08 Semiconductor storage device memory disk unit with multiple host interfaces WO2012169820A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/155,576 2011-06-08
US13/155,576 US20110252250A1 (en) 2010-04-13 2011-06-08 Semiconductor storage device memory disk unit with multiple host interfaces

Publications (2)

Publication Number Publication Date
WO2012169820A2 WO2012169820A2 (en) 2012-12-13
WO2012169820A3 true WO2012169820A3 (en) 2013-03-07

Family

ID=47296617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2012/004529 WO2012169820A2 (en) 2011-06-08 2012-06-08 Semiconductor storage device memory disk unit with multiple host interfaces

Country Status (2)

Country Link
KR (1) KR101212809B1 (en)
WO (1) WO2012169820A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9436630B2 (en) * 2013-06-11 2016-09-06 Western Digital Technologies, Inc. Using dual phys to support multiple PCIe link widths
KR102384773B1 (en) 2017-10-12 2022-04-11 삼성전자주식회사 Storage device, computing system and debugging method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020048414A (en) * 1999-09-22 2002-06-22 네트셀 코포레이션 RAID controller system and method with ATA emulation host interface
KR20080106775A (en) * 2007-06-04 2008-12-09 삼성전자주식회사 Memory system using the interleaving scheme and method having the same
KR100928438B1 (en) * 2008-11-24 2009-11-25 주식회사 태진인포텍 Storage of serial attached small computer system interface/serial advanced technology attachment type

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020048414A (en) * 1999-09-22 2002-06-22 네트셀 코포레이션 RAID controller system and method with ATA emulation host interface
KR20080106775A (en) * 2007-06-04 2008-12-09 삼성전자주식회사 Memory system using the interleaving scheme and method having the same
KR100928438B1 (en) * 2008-11-24 2009-11-25 주식회사 태진인포텍 Storage of serial attached small computer system interface/serial advanced technology attachment type

Also Published As

Publication number Publication date
KR101212809B1 (en) 2012-12-18
WO2012169820A2 (en) 2012-12-13

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