KR20020046469A - Pattern for reducing oxide erosion during chemical mechanical polishing of metal - Google Patents
Pattern for reducing oxide erosion during chemical mechanical polishing of metal Download PDFInfo
- Publication number
- KR20020046469A KR20020046469A KR1020000076665A KR20000076665A KR20020046469A KR 20020046469 A KR20020046469 A KR 20020046469A KR 1020000076665 A KR1020000076665 A KR 1020000076665A KR 20000076665 A KR20000076665 A KR 20000076665A KR 20020046469 A KR20020046469 A KR 20020046469A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- metal
- erosion
- oxide
- dummy pattern
- Prior art date
Links
- 230000003628 erosive effect Effects 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 title claims description 43
- 239000002184 metal Substances 0.000 title claims description 43
- 238000005498 polishing Methods 0.000 title description 12
- 239000000126 substance Substances 0.000 title description 5
- 238000000034 method Methods 0.000 claims description 50
- 230000007547 defect Effects 0.000 abstract description 3
- 239000010949 copper Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002002 slurry Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000002522 swelling effect Effects 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 금속의 화학적 기계적 연마(Chemical mechanical polishing;CMP)공정시의 산화막 침식 감소를 위한 패턴구조에 관한 것으로, 특히 CMP공정에서 더미패턴을 삽입하여 산화막 침식을 줄이고 패턴 경계면에서의 프로파일 개선을 도모하는 방법에 관한 것이다.The present invention relates to a pattern structure for reducing oxide film erosion during a chemical mechanical polishing (CMP) process of metals. In particular, a dummy pattern is inserted in a CMP process to reduce oxide film erosion and improve a profile at a pattern interface. It is about how to.
금속의 CMP공정은 금속 매립콘택의 형성 및 대머신(Damascene)기술에 의한 배선 형성을 위해 사용되는 기술이다. 연마공정은 금속의 산화막에 대한 연마선택비가 매우 큰 슬러리를 사용하여 진행하지만 금속과 산화막이 동시에 연마되는 시점에서 산화막이 금속과 함께 연되는 산화막 침식현상이 발생한다. 이러한 산화막 침식은 배선의 유효 두께를 감소시켜 배선의 저항을 증가시킬 뿐만 아니라 단차 발생으로 인해 후속 공정의 공정마진을 줄이기 때문에 CMP공정에서 최대한 줄일 수 있도록 해야 한다.The metal CMP process is a technique used for forming a metal buried contact and forming a wiring by a damascene technique. The polishing process is performed using a slurry having a very high polishing selectivity to the oxide film of the metal, but an oxide erosion phenomenon occurs in which the oxide film is softened together with the metal when the metal and the oxide film are simultaneously polished. Such oxide erosion not only increases the resistance of the wiring by reducing the effective thickness of the wiring, but also reduces the process margin of subsequent processes due to the generation of steps, so that the CMP process can be minimized.
상기한 바와 같이 금속의 CMP공정은 근본적으로 금속의 산화막에 대한 연마선택비가 높은 슬러리를 사용하기 때문에 패턴지역에서 산화막 침식현상이 발생한다. 층간절연막의 CMP공정에서는 높은 평탄화 효과를 내기 위해 더미패턴을 마스크에 삽입하여 공정을 진행하는 기술이 널리 사용되어 왔다. 그러나 금속의 CMP공정에서는 반도체소자에의 적용분야가 한정되어 있고 공정마진이 매우 큰 부분에 사용되어 왔기 때문에 더미패턴 설계에 대한 개념이 비교적 희박하였다. 그러나 최근 금속 게이트 형성, 커패시터의 스토리지노드 콘택 및 하부 전극 형성과 대머신기술에 의한 배선 형성 (알루미늄 또는 구리배선) 등 반도체소자 제조공정에 금속 CMP공정의 적용분야가 확대되고 공정마진 또한 매우 작은 경우가 많아지게 되었다.As described above, since the CMP process of the metal basically uses a slurry having a high polishing selectivity with respect to the oxide of the metal, oxide erosion occurs in the pattern region. In the CMP process of the interlayer insulating film, a technique of inserting a dummy pattern into a mask and performing a process in order to obtain a high planarization effect has been widely used. However, in the CMP process of metals, the concept of the dummy pattern design is relatively slim because the application field to the semiconductor device is limited and the process margin is used for a very large part. However, in recent years, the application of the metal CMP process to the semiconductor device manufacturing process, such as metal gate formation, storage node contact of capacitors, lower electrode formation, and wiring formation (aluminum or copper wiring) by a large machine technology has been expanded and the process margin is very small. Has become a lot.
한편, 과도한 산화막 침식은 금속배선의 저항 증가과 후속공정(사진공정, CMP공정 등)의 공정마진을 매우 작게 만드는 부정적인 효과를 내기 때문에 유효배선 두께의 확보와 후속공정에서의 부담을 줄이기 위해 산화막 침식을 효과적으로 줄일 수 있는 방법이 필요하게 되었다. 듀얼 대머신에 의한 구리배선 형성시 적용되는 구리 CMP의 경우에 있어서는 산화막 침식을 줄이기 위해 Cu/Ta/산화막의 연마속도가 동일한 슬러리를 사용한다. 이는 현재로서는 산화막 침식을 줄이기 위한 가장 실용적인 방법이나, 이 경우 연마속도가 낮고 기존 층간절연막의 CMP공정에서와 같이 산화막의 두께를 타겟으로 공정을 진행해야 하는 어려움이 있다. 또한 금속 CMP공정에 의해 패턴 경계부위가 패턴 내부보다 깊에 파이는 팽효과(fang effect)가 나타난다. 이는 금속과 산화막의 연마선택비 차이에 의한 것으로, 선택비가 크면 클수록 그 정도는 더욱 심해진다. 이러한 팽효과는 패턴 내부와 경계에서 금속배선의 두께 차이를 유발하게 되어 경우에 따라서는 전기적 특성 차이를 유발할 수 있는 원인이 된다. 따라서 근본적으로 금속 CMP공정에서도 더미패턴을 삽입하여 산화막 침식을 줄이고 패턴경계면에서의 프로파일 개선을 도모할 수 있는 방법의 도입이 절실히 요구된다.On the other hand, excessive erosion of the oxide film has the negative effect of increasing the resistance of the metal wiring and making the process margin of the subsequent process (photographic process, CMP process, etc.) very small, so that oxide erosion is performed to secure the effective wiring thickness and reduce the burden on the subsequent process. There is a need for a method that can effectively reduce it. In the case of copper CMP applied when forming copper wiring by dual damascene, a slurry having the same polishing rate of Cu / Ta / oxide is used to reduce oxide erosion. This is the most practical method for reducing oxide erosion at present, but in this case, the polishing rate is low and there is a difficulty in proceeding the process targeting the thickness of the oxide film as in the CMP process of the existing interlayer insulating film. Also, due to the metal CMP process, the pie has a fang effect when the pattern boundary is deeper than the inside of the pattern. This is caused by the difference in the polishing selectivity between the metal and the oxide film. The larger the selectivity, the more severe the degree. This swelling effect causes a difference in the thickness of the metal wiring at the inside and the boundary of the pattern, which in some cases can cause a difference in electrical characteristics. Therefore, there is an urgent need for the introduction of a method of inserting a dummy pattern in the metal CMP process to reduce the erosion of the oxide film and to improve the profile at the pattern boundary surface.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 보호하고자 하는 주 패턴의 주변에 더미패턴을 삽입하고 더미패턴의 밀도를 조절하여 주 패턴의 산화막 침식현상을 감소시킬 수 있도록 하는 금속의 화학적 기계적 연마공정시의 산화막 침식 감소를 위한 패턴구조를 제공하는데 목적이 있다.The present invention is to solve the above problems, by inserting a dummy pattern around the main pattern to be protected, and by adjusting the density of the dummy pattern chemical mechanical polishing process of the metal to reduce the erosion of the oxide film of the main pattern It is an object of the present invention to provide a pattern structure for reducing oxide erosion in the city.
도1은 본 발명에 의한 금속의 화학적 기계적 연마공정시의 산화막 침식 감소를 위한 패턴구조를 나타낸 평면도.1 is a plan view showing a pattern structure for reducing the oxide film erosion during the chemical mechanical polishing process of the metal according to the present invention.
도2 및 도3은 본 발명에 의한 금속의 화학적 기계적 연마공정시의 산화막 침식 감소를 위한 패턴구조에 있어서 더미패턴과 주 패턴의 배치관계를 나타낸 도면.2 and 3 are views showing the arrangement relationship between the dummy pattern and the main pattern in the pattern structure for reducing the oxide film erosion during the chemical mechanical polishing process of the metal according to the present invention.
도4는 더미패턴을 삽입한 경우와 삽입하지 않은 경우의 주 패턴의 엣지 프로파일을 비교하여 나타낸 도면.Fig. 4 is a diagram showing a comparison of the edge profile of the main pattern with and without inserting the dummy pattern.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 주 패턴 20 : 더미패턴10: main pattern 20: dummy pattern
상기 목적을 달성하기 위한 본 발명은, 금속 CMP공정에서의 산화막 침식을 감소시키기 위한 패턴구조에 있어서, 연마하고자 하는 금속패턴의 주변에 더미패턴이 삽입된 것을 특징으로 한다.The present invention for achieving the above object, in the pattern structure for reducing the oxide film erosion in the metal CMP process, characterized in that the dummy pattern is inserted around the metal pattern to be polished.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
금속 CMP공정에서 이상적인 공정 타겟은 패턴지역에서 산화막 침식없이 금속배선간을 분리하는 것이다. 그러나 근본적으로 금속과 산화막간의 연마선택비의 차이 때문에 산화막 침식은 필연적으로 발생하며 패턴밀도에 크게 의존하는 특성을 보인다. 통상 산화막 침식은 500Å이하를 공정 타겟으로 설정하지만 여타 여러 변수들에 의해 1000Å이상 발생하는 경우도 흔하다. 이러한 산화막 침식이 발생하면 후속 사진공정에서의 부담과 상부층 금속 CMP공정에서 분리를 위해 과도연마가 불가피해지기 때문에 추가적으로 공정시간 증가와 결함발생이라는 문제가 심각해져 층이 점점 늘어날수록 이러한 부담을 더욱 커지게 된다. 구리 대머신에 의한 배선 형성시 CMP공정에서 산화막 침식에 의한 500Å의 단차를 줄이기 위해서는 1분 이상의 추가연마(공정시간 30% 증가)를 진행해야 한다. 따라서 산화막 침식을 줄이는것이 금속 CMP의 가장 큰 문제중의 하나이다.The ideal process target in the metal CMP process is to separate metal interconnects without oxide erosion in the pattern region. However, due to the difference in the polishing selectivity between the metal and the oxide film, oxide erosion is inevitably occurring and is highly dependent on the pattern density. Oxide erosion is usually set to less than 500 mW as a process target, but is often more than 1000 mW due to many other variables. If such oxide erosion occurs, over-polishing becomes inevitable for the subsequent photo process and separation in the upper layer metal CMP process, which further increases the process time and the problem of defects. do. In order to reduce the 500Å step due to oxide erosion in the CMP process during wiring formation by copper damascene, additional polishing (30% increase in processing time) of 1 minute or more should be performed. Therefore, reducing oxide erosion is one of the biggest problems of metal CMP.
본 발명은 금속 CMP공정에서 인접패턴이 존재할 경우 산화막 침식의 정도가 변화하는 특성을 응용한 것이다. 산화막 침식은 주변 패턴과의 상호 작용에 의해 발생하기 때문에 더미패턴의 밀도 및 배치방법에 따라 주 패턴의 산화막 침식은 크게 변화하게 된다.The present invention applies the characteristic that the degree of oxide erosion changes when there is an adjacent pattern in the metal CMP process. Since the erosion of the oxide film is caused by the interaction with the surrounding pattern, the erosion of the oxide film of the main pattern is greatly changed depending on the density and the arrangement method of the dummy pattern.
도1에 본 발명에 의한 금속 CMP공정에서의 산화막 침식을 감소시키기 위한 패턴구조를 나타내었다. 도시한 바와 같이 산화막 침식을 줄이기 위해 연마하고자 하는 주 패턴(10)의 주변에 더미패턴(20)을 삽입한다. 이때 더미패턴(20)은 도2에 나타낸 바와 같이 연마하고자 하는 주 패턴(10)과 같은 면에 형성되도록 하며, 더미패턴과 주 패턴간의 거리(d)는 더미패턴의 폭(W)의 50% 이하로 한다. 더미패턴의 금속밀도는 30-70%로 하는 것이 바람직하다.Figure 1 shows a pattern structure for reducing the oxide film erosion in the metal CMP process according to the present invention. As shown in the drawing, the dummy pattern 20 is inserted around the main pattern 10 to be polished to reduce erosion of the oxide film. At this time, the dummy pattern 20 is formed on the same surface as the main pattern 10 to be polished as shown in FIG. 2, and the distance d between the dummy pattern and the main pattern is 50% of the width W of the dummy pattern. It is set as follows. The metal density of the dummy pattern is preferably set to 30-70%.
또한, 도3에 나타낸 바와 같이 주 패턴(10)이 라인/스페이스 패턴이고 더미패턴(20)도 같은 라인/스페이스 패턴일 경우에는 주 패턴과 더미패턴의 라인방향을 서로 평행하게 하고 더미패턴은 라인에 수직하게 배치한다.3, if the main pattern 10 is a line / space pattern and the dummy pattern 20 is also the same line / space pattern, the line directions of the main pattern and the dummy pattern are parallel to each other, and the dummy pattern is a line. Place it perpendicular to the.
상기와 같이 더미 패턴을 주 패턴의 주변에 삽입한 경우의 패턴의 엣지 프로파일을 도4에 나타내었다. 도4에 도시된 바와 같이 더미패턴을 삽입하지 않은 경우(a)에는 주 패턴의 엣지(A)에 쐐기 모양으로 파이는 현상이 발생하나, 더미패턴을 삽입하면(b) 주 패턴 좌우의 더미패턴으로 내부패턴의 프로파일이 균일해짐을 알 수 있다.As shown in FIG. 4, the edge profile of the pattern when the dummy pattern is inserted around the main pattern is shown in FIG. 4. As shown in FIG. 4, when the dummy pattern is not inserted (a), a wedge is formed in the edge A of the main pattern. However, when the dummy pattern is inserted (b), the dummy pattern on the left and right sides of the main pattern is inserted. It can be seen that the profile of the internal pattern becomes uniform.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 금속 CMP공정에 있어서 주 패턴의 주변에 더미패턴을 삽입함으로써 산화막 침식을 감소시킨다. 산화막 침식이 감소하면 상위층에서 금속 CMP공정시 과도연마시간이 줄어들어 생산량이 감소하지 않고 과도연마에 의한 스크래치와 같은 결함 발생을 억제할 수 있어 수율 증가에 크게 기여할 수 있다.The present invention reduces oxide film erosion by inserting a dummy pattern around the main pattern in the metal CMP process. Reduction of oxide erosion reduces over-polishing time during the metal CMP process in the upper layer, which does not reduce production and can suppress defects such as scratches caused by over-polishing, which can greatly contribute to yield increase.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000076665A KR20020046469A (en) | 2000-12-14 | 2000-12-14 | Pattern for reducing oxide erosion during chemical mechanical polishing of metal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000076665A KR20020046469A (en) | 2000-12-14 | 2000-12-14 | Pattern for reducing oxide erosion during chemical mechanical polishing of metal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020046469A true KR20020046469A (en) | 2002-06-21 |
Family
ID=27681984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000076665A KR20020046469A (en) | 2000-12-14 | 2000-12-14 | Pattern for reducing oxide erosion during chemical mechanical polishing of metal |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020046469A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100900242B1 (en) * | 2002-11-14 | 2009-05-29 | 매그나칩 반도체 유한회사 | Structure of metal line |
| KR101043870B1 (en) * | 2008-12-19 | 2011-06-22 | 주식회사 하이닉스반도체 | Semiconductor having CMP dummy pattern and method for manufacturing the CMP dummy pattern |
-
2000
- 2000-12-14 KR KR1020000076665A patent/KR20020046469A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100900242B1 (en) * | 2002-11-14 | 2009-05-29 | 매그나칩 반도체 유한회사 | Structure of metal line |
| KR101043870B1 (en) * | 2008-12-19 | 2011-06-22 | 주식회사 하이닉스반도체 | Semiconductor having CMP dummy pattern and method for manufacturing the CMP dummy pattern |
| US8242583B2 (en) | 2008-12-19 | 2012-08-14 | Hynix Semiconductor Inc. | Semiconductor device having CMP dummy pattern |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100440484C (en) | Method of fabricating flash memory device | |
| KR20010050525A (en) | Dual damascene flowable oxide insulation structure and metallic barrier | |
| TW299458B (en) | ||
| US7276451B2 (en) | Method for manufacturing semiconductor device | |
| CN102543699A (en) | Method for forming metal gate | |
| US5966632A (en) | Method of forming borderless metal to contact structure | |
| KR20020046469A (en) | Pattern for reducing oxide erosion during chemical mechanical polishing of metal | |
| KR100695431B1 (en) | Method for forming a contact hole in semiconductor device | |
| KR100315039B1 (en) | Method for forming metal interconnection line of semiconductor device | |
| KR100390838B1 (en) | Method for forming landing plug contact in semiconductor device | |
| KR100538097B1 (en) | Method for manufacturing a metal layer and method for manufacturing semiconductor device using the same | |
| KR0124635B1 (en) | Planerizing method of semiconductor device | |
| KR100802311B1 (en) | Method for fabricating cmos image sensor | |
| JP4953183B2 (en) | Semiconductor device planarization method | |
| KR20040001938A (en) | Forming method of self align contact in semiconductor device | |
| KR100336793B1 (en) | Fabricating method of semiconductor device | |
| US6838371B2 (en) | Method of manufacturing semiconductor device | |
| KR100723789B1 (en) | Method of planarization a semiconductor device | |
| KR20000003445A (en) | Chemical mechanical flattening method of semiconductor device | |
| KR20030058263A (en) | Method of forming storage node contact | |
| KR20040059454A (en) | Method for forming storage node contact in semiconductor | |
| KR100370162B1 (en) | method for manufacturing semiconductor device | |
| KR20050116665A (en) | Method for fabricating semiconductor device | |
| KR20000044923A (en) | Method for flattening interlayer dielectric of semiconductor device | |
| KR100727438B1 (en) | A forming method of metal line using diamond light carbon organic dielectric layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |