KR0124635B1 - Planerizing method of semiconductor device - Google Patents

Planerizing method of semiconductor device

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Publication number
KR0124635B1
KR0124635B1 KR1019940007741A KR19940007741A KR0124635B1 KR 0124635 B1 KR0124635 B1 KR 0124635B1 KR 1019940007741 A KR1019940007741 A KR 1019940007741A KR 19940007741 A KR19940007741 A KR 19940007741A KR 0124635 B1 KR0124635 B1 KR 0124635B1
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KR
South Korea
Prior art keywords
semiconductor device
layer
polishing
imd
cap layer
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KR1019940007741A
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Korean (ko)
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KR950030248A (en
Inventor
박내학
민융기
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문정환
엘지반도체주식회사
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Priority to KR1019940007741A priority Critical patent/KR0124635B1/en
Publication of KR950030248A publication Critical patent/KR950030248A/en
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Publication of KR0124635B1 publication Critical patent/KR0124635B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

On an inter-metal dielectric layer(3) having a step coverage, a cap layer(4) having a low polishing rate relative to the inter-metal dielectric layer(3) is formed. Then, the cap layer(4) and the inter-metal dielectric layer(3) are polished by CMP(chemical mechanical polishing). The polishing rate of the cap layer(4) is lower than that of the inter-metal dielectric(3). Thereby, it is possible to increase a global flatness of step coverage.

Description

반도체 소자의 평탄화방법Planarization method of semiconductor device

제1도는 종래의 반도체 소자의 평탄화공정을 나타낸 도면도.1 is a view showing a planarization process of a conventional semiconductor device.

제2도는 본 발명의 반도체 소자의 평탄화공정을 나타낸 단면도.2 is a cross-sectional view showing the planarization process of the semiconductor device of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : BPSG(평탄화용 보호막) 2 : 금속배선(Metal Line)1: BPSG (flattening protective film) 2: Metal line

3 : IMD(인터메탈유전체층) 4 : 캡층(Cap Layer)3: IMD (intermetal dielectric layer) 4: Cap layer

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다층 금속배선 구조를 반도체 셀(Cell)의 IMD(Inter Metal Dieletric)공정에 적당하도록 한 화학 기계적 경면연마(Chemical Mechanical Polishing)를 이용한 반도체 셀의 평탄화 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to planarize a semiconductor cell using chemical mechanical polishing, in which a multilayer metal wiring structure is suitable for an intermetal dieletric (IMD) process of a semiconductor cell. It is about process.

일반적으로, 고밀도의 디바이스 형성을 위한 각소자의 디멘션(Dimension)축소방향으로 배선의 패턴폭을 줄이는 것이 사용되었으나, 이러한 방법은 전류용량이나 배선 저항의 문제로 한계에 이르게 되었다.In general, it has been used to reduce the pattern width of the wiring in the dimension reduction direction of each element for forming a high-density device, but this method has reached its limit due to the problem of current capacity or wiring resistance.

따라서, 배선의 패턴폭을 줄이지 않고 각 소자의 디멘션을 축소시키기 위해 다층 배선 기술을 도입하여 디바이스의 집적도를 향상시켰다.Accordingly, multilayer wiring technology has been introduced to reduce the dimension of each device without reducing the pattern width of the wiring, thereby improving the degree of integration of the device.

그러나 다층 배선 기술에는 배선을 다층으로 하기 때문에 표면의 단차가 심해져, 디바이스의 수율이나 신뢰성에 상당한 영향을 주는 단선문제를 야기시켰다.However, in the multilayer wiring technology, since the wiring is multi-layered, the step height of the surface is increased, causing a disconnection problem that significantly affects the yield and reliability of the device.

이와같은 문제점을 해결하기 위한 표면을 평탄화 방법이 디바이스 제조공정상의 중요 과제로 대두되었다.The method of planarizing the surface to solve such a problem has emerged as an important problem in the device manufacturing process.

이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 평탄화 방법을 설명하면 다음과 같다.Hereinafter, a planarization method of a conventional semiconductor device will be described with reference to the accompanying drawings.

제1도(a)(b)는 종래의 반도체 소자의 평탄화 공정을 나타낸 것으로 제1도(a)에서와 같이 반도체 소자의 표면을 안정화시키기 위하여 형성한 BPSG(Boron Phosphorus Silicate Glass)층(1)상에 패터닝되어진, 금속배선(2)위에 유전체(Dielectric)를 증착하여 인터메탈 유전체층(IMD : Inter Metal Dielectric Layer)(3)을 형성한다.(A) and (b) show a planarization process of a conventional semiconductor device. As shown in FIG. 1 (a), a BPSG (Boron Phosphorus Silicate Glass) layer 1 is formed to stabilize the surface of a semiconductor device. A dielectric is deposited on the metallization 2, patterned on it, to form an intermetal dielectric layer (IMD) 3.

이어, 경면 연마시에 IMD층(3)의 단차가 높은 영역의 경면 연마비가 낮은 영역의 경면 연마비보다 상대적으로 큰 것을 이용하여, 현탁액(slurry)을 매질로 하여 CMP(Chemical Mechanical Polishing) 방법으로 IMD층(3)을 경면 연마(Polishing)한다.Subsequently, in the case of mirror polishing, a slurry is used as a medium and a CMP (Chemical Mechanical Polishing) method using a slurry that is relatively larger than the mirror polishing rate in the region where the step height of the IMD layer 3 is high is low. The IMD layer 3 is mirror polished.

그리고 탈이온수(D·I)를 이용하여 경면연마가 끝난 IMD층(3)과 경면연마(Polishing)과정으로 IMD층(3)에 잔존해있는 현탁액(Slurry)등 기타 불순물을 세정한다.Deionized water (D-I) is used to clean other impurities such as a slurry remaining in the IMD layer 3 by mirror polishing and IMD layer 3 after a mirror polishing process.

상기와 같은 방법으로 평탄화 공정을 수행한 반도체 소자는 평탄화 공정을 하기전에는 (X)만큼의 IMD층(3)단차가 존재하였으나, 평탄화 공정후에는 제1도(b)에서와 같이 IMD층(3)의 단차가 (Y)로 줄었음을 알수 있다.In the semiconductor device subjected to the planarization process as described above, the step of the IMD layer 3 as much as (X) existed before the planarization process, but after the planarization process, the IMD layer 3 as shown in FIG. We can see that the step is reduced to (Y).

그러나 상기와 같은 종래의 반도체 소자 평탄화 방법은 IMD층(3)의 단차가 높은 영역과 낮은 영역에 대한 경면 연마비(Polishing Rate)의 조정에는 한계가 있어 반도체 소자의 평탄화에도 역시 한계가 있었다.However, the conventional method of planarizing a semiconductor device as described above has a limitation in adjusting the polishing rate for regions where the step height of the IMD layer 3 is high and low, so that the planarization of the semiconductor device is also limited.

또한 단차가 높은 영역의 경면연마비를 높이기 위하여 경도가 높은 패드(Pad)를 사용할 경우는 경면연마비의 불일치(Non Uniformity)로 하여 반도체 소자의 표면상의 균일성에 문제가 발생하였다.In addition, in the case of using a pad having a high hardness in order to increase the mirror polishing in the high step area, there is a problem in the uniformity on the surface of the semiconductor device due to the non uniformity of the mirror polishing.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 다층 금속 배선 구조를 갖는 반도체셀의 IMD 공정에 적당하도록 한 평탄화 공정으로 소자의 특성을 향상시키고, 고집적화가 가능한 반도체 소자를 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and the purpose of the present invention is to provide a semiconductor device capable of improving the characteristics of the device and making it highly integrated by a planarization process suitable for the IMD process of a semiconductor cell having a multi-layered metal wiring structure. have.

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 평탄화 공정을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, the planarization process of the semiconductor device of the present invention for achieving the above object is as follows.

제2도(a) 내지 (d)는 본 발명의 반도체 소자의 평탄화 공정을 나타낸 단면도이다.2A to 2D are cross-sectional views showing the planarization process of the semiconductor device of the present invention.

제2도(a)와 같이 반도체 소자의 표면을 안정화시키기 위하여 형성한 BPSG층(1)상에 패터닝 되어진 금속배선(2)위에 유전체(Dielectric)를 증착하여 인터메탈 유전체층(IMD Layer)(3)을 형성한다.As shown in FIG. 2A, a dielectric is deposited on the metallization 2 patterned on the BPSG layer 1 formed to stabilize the surface of the semiconductor device, thereby forming an intermetal dielectric layer 3 To form.

이어 제2도(b)와 같이 IMD층(3)에 비하여 상대적으로 연마속도가 느린, 즉 경면 연마비(Polishing Rate)가 낮은 유전체(나이트라이드(Nitride) 또는 기타 옥사이드(Oxide))를 증착하여 캡층(Cap Layer)(4)을 형성한 후, 제2도(c)와 같이 현탁액(slurry)을 매질로 하여 CMP(Chemical Mechanical Polishing)을 이용하여 단차가 높은 셀(Cell)부위의 경면 연마비가 낮은 캡층(4)을 완전히 제거(이때, 단차가 낮은 셀부위의 경면 연마비가 낮은 캡층(4)은 제2도(c)의 A부분에서와 같이 약간 남아있다.) 한후 CMP 공정을 계속 진행하여 단차가 낮은 셀 부위의 경면 연마비가 낮은 캡층(4)이 마스킹층으로 작용하여 단차가 높은 지역의 IMD층(3)을 충분히 빨리 연마시켜 결국 제2도(c)의 Z와같이 IMD층(3)의 단차를 없앤다.Then, as shown in FIG. 2 (b), a dielectric (Nitride or other oxide) having a relatively slow polishing rate, that is, a low polishing rate, is deposited compared to the IMD layer 3. After forming the cap layer (4), as shown in Fig. 2 (c), the suspension is used as a medium, and the mirror polishing ratio of the cell portion having a high level of difference using CMP (Chemical Mechanical Polishing) is increased. Completely remove the low cap layer 4 (at this time, the cap layer 4 having a low mirror polishing rate at the stepped cell portion remains slightly as shown in part A of FIG. 2C), and then proceed with the CMP process. A cap layer 4 having a low mirror polishing ratio at a cell level having a low step acts as a masking layer, thereby polishing the IMD layer 3 in a high step area sufficiently fast, so that the IMD layer 3 as shown in Z in FIG. ) Remove the step.

이어, 제2도(d)와 같이 탈이온수(D·I)를 이용하여 경면 연마가 끝난 캡층(4)과 IMD층(3), 그리고 경면 연마 과정으로 캡층(4)와 IMD층(3)에 잔존해 있는 현탁액(slurry)등 기타 불순물을 세정한다.Subsequently, as shown in FIG. 2D, the cap layer 4 and the IMD layer 3 which have been mirror polished using deionized water D · I, and the cap layer 4 and IMD layer 3 which have been mirror polished. Clean out any remaining impurities such as slurry.

상기와 같은 본 발명의 반도체 소자 평탄화 방법은 상대적으로 IMD층(3)에 비하여 경마비가 낮은 유전체를 IMD층(3)상에 증착하여 캡층(4)을 형성한 후, CMP 공정을 하므로 단차가 높은 영역의 IMD층(3)을 먼저 경면 가공하게 되어 다층 금속배선 구조를 반도체 소자의 평판도를 높일 수 있다.In the semiconductor device planarization method of the present invention as described above, since the dielectric layer having a low paralysis relative to the IMD layer 3 is deposited on the IMD layer 3 to form the cap layer 4, the CMP process is performed. The IMD layer 3 in the region is first mirror-finished to increase the flatness of the semiconductor device in the multilayer metal wiring structure.

그러므로 금속배선이 패터닝시 공정시 마진(Margine)을 크게 하여 소자의 집적도를 높일 수 있고, 평판도의 증가로 상층부 금속배선의 저항을 감소시켜 반도체 소자의 특성을 증가시키는 효과가 있다.Therefore, the metal wiring can increase the integration degree of the device by increasing the margin (Margine) during the patterning process, and there is an effect of increasing the characteristics of the semiconductor device by reducing the resistance of the upper metal wiring by increasing the flatness.

Claims (2)

반도체 소자의 인터메탈 유전체층상에 상기 인터메탈 유전체층보다 경면 연마비가 낮은 캡층을 형성하는 공정과, 상기의 인터메탈 유전체층과 캡층을 동시에 경면 연마(Polishing)하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 평탄화 방법.And forming a cap layer having a lower mirror polishing rate than the intermetal dielectric layer on the intermetal dielectric layer of the semiconductor device, and simultaneously mirror-polishing the intermetal dielectric layer and the cap layer. Method of planarization. 제1항에 있어서, 경면 연마(Polishing)는 CMP(Chemical Mechanical Polishing)로 하는 것을 특징으로 하는 반도체 소자의 평탄화 방법.The planarization method of a semiconductor device according to claim 1, wherein mirror polishing is chemical mechanical polishing (CMP).
KR1019940007741A 1994-04-13 1994-04-13 Planerizing method of semiconductor device KR0124635B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100955931B1 (en) * 2007-03-15 2010-05-03 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020080158A (en) * 2001-04-12 2002-10-23 주식회사 하이닉스반도체 Method for planarizing of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100955931B1 (en) * 2007-03-15 2010-05-03 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

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