CN102543699A - Method for forming metal gate - Google Patents
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- CN102543699A CN102543699A CN2010106034179A CN201010603417A CN102543699A CN 102543699 A CN102543699 A CN 102543699A CN 2010106034179 A CN2010106034179 A CN 2010106034179A CN 201010603417 A CN201010603417 A CN 201010603417A CN 102543699 A CN102543699 A CN 102543699A
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Abstract
The invention relates to a method for forming a metal gate. The method comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate is divided into a core unit area and a peripheral circuit area, sacrificial oxide layers and dummy gates are formed on the semiconductor substrate in turn, spacers are formed on the semiconductor substrate on the two sides of each dummy gate, and interlayer dielectric (ILD) layers are formed on the semiconductor substrate and flush with the tops of the dummy gates and the spacers; removing the dummy gates and the sacrificial oxide layers to form grooves; forming metal layers on the ILD layers, and filling the grooves; forming protection layers in the groove of the peripheral circuit area and the metal layer on the edge of the groove; and grinding the protection layers and the metal layers until the ILD layers are exposed to form the metal gate, wherein the grinding rate of the protection layers is lower than that of the metal layers. By the method, the defect that the metal gate is sunken is overcome, and the electrical property of the metal gate and the reliability of a semiconductor device are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of formation method of metal gates.
Background technology
Semiconductor chip manufacturing has at present developed into 32 nanometers and following technology, and traditional polysilicon gate can not satisfy the requirement on electric performance under this characteristic size.In order to solve serious leakage current and the power problems that traditional polysilicon gate brings, in 32 nanometers and following technology, adopt high-k (high k) dielectric material at present mostly as gate dielectric layer, metal material is as grid, to obtain good electrical properties.For the manufacturing process of metal gates just like disclosed method in the U.S. Pat 20100052070: on Semiconductor substrate, form the high K medium layer earlier, and on the high K medium layer deposition one deck conductive layer; Utilize polysilicon to form polysilicon gate construction (dummy gate) separately, on entire substrate, deposit interlayer dielectric layer (ILD) then, and carry out the first Dow Chemical mechanical polishing (CMP) in nFET district and pFET district.Then, remove the polysilicon on the polycrystal silicon grid structure in nFET district, form first grid groove, and this groove deposition n type metal; Carry out the second Dow Chemical mechanical polishing (CMP).Polysilicon on the polysilicon gate construction in removal pFET district forms second gate groove, and on this gate groove, deposits p type metal.Carry out the 3rd Dow Chemical mechanical polishing (CMP) then, form high K medium layer metal gate structure.
Existing another kind of preparation technology such as Fig. 1 to Fig. 4.As shown in Figure 1, the Semiconductor substrate (not shown) is provided, the surf zone of said Semiconductor substrate is divided into periphery circuit region II and core cell district I; Be formed with sacrificial oxide layer 102, polysilicon gate 101a, 101b on the said Semiconductor substrate; Has a side wall (spacer) 104 on polysilicon gate 101a, the 101b semiconductor substrates on two sides; On Semiconductor substrate, also be formed with interlayer dielectric layer (ILD) 103, said interlayer dielectric layer 103 and polysilicon gate 101a, 101b and side wall 104 flush.I wherein in the core cell district, because the device closeness is high, so polysilicon gate 101a is relatively also than comparatively dense, the critical size of polysilicon gate 101a (CD) is also less; And at periphery circuit region II, because the device closeness is low, it is sparse that polysilicon gate 101b distributes, and critical size is bigger.
As shown in Figure 2, remove polysilicon gate 101a, 101b and sacrificial oxide layer 102 to exposing Semiconductor substrate, form groove; Because the polysilicon gate 101b critical size of periphery circuit region II is greater than the critical size of the polysilicon gate 101a of core cell district I; Therefore after removing polysilicon gate 101a, 101b, the groove dimensions that the groove dimensions that forms at periphery circuit region II forms greater than the I in the core cell district.
As shown in Figure 3, on interlayer dielectric layer, form metal level 105, and metal level 105 is filled full said groove; After having formed metal level 105; Metal level 105 is not smooth; Since in periphery circuit region II internal channel size greater than core cell district I internal channel size; Therefore the metal level 105 that is positioned at the groove of periphery circuit region II highly is lower than the groove inner metal layer 105 of core cell district I, and forms the slope at the slot wedge of periphery circuit region II.
As shown in Figure 4, grinding metal layer 105 is to exposing interlayer dielectric layer 103, and I forms metal gates 105a in the core cell district, forms metal gates 105b at periphery circuit region II.Depression 106 has wherein appearred in the metal gates 105b of periphery circuit region II.
Because periphery circuit region is active device non-dense set district; Therefore the metal gates critical size that forms at periphery circuit region is bigger; Usually can be greater than 10 microns; After metal gates in the groove ground, very serious depression can appear in the metal gates of periphery circuit region, and 106 degree of depth that cave in can reach more than 300 dusts.For example, form total height is the aluminum metal grid of 400～600 dusts, and the depression of 300 dusts makes the less thick of aluminum metal grid, causes that metal gates resistivity seriously changes, and causes semiconductor device failure.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of metal gates, improves that periphery circuit region metal gates in the mill produces depression and the electrical performance issues that causes grid, even the problem of semiconductor device failure.
For addressing the above problem, the present invention adopts following technical scheme:
A kind of formation method of metal gates may further comprise the steps: Semiconductor substrate is provided, and said Semiconductor substrate is divided into core cell district and periphery circuit region; Be formed with sacrificial oxide layer and polysilicon gate on the said Semiconductor substrate successively; Be formed with side wall on the Semiconductor substrate of said polysilicon gate both sides; On said Semiconductor substrate, be formed with interlayer dielectric layer, said interlayer dielectric layer flushes with polysilicon gate and side wall top; Remove polysilicon gate and sacrificial oxide layer, form groove, the groove dimensions in said core cell district is less than the groove dimensions of periphery circuit region; On interlayer dielectric layer, form metal level, and fill full said groove; In the periphery circuit region groove and on the slot wedge metal level, form protective layer; Grind said protective layer and metal level to exposing interlayer dielectric layer, form metal gates, to the grinding rate of said protective layer less than metal level.
Preferably, the method for said grinding protection layer and metal level is a chemical mechanical milling method.
Preferably, said chemical mechanical milling method adopts alumina lap liquid.
Preferably, said protective layer is an alumina layer.
Preferably, said alumina layer adopts thermal oxidation method to form.
Preferably, said alumina layer thickness is 10～100 dusts.
Preferably, said lapping liquid is 3: 1～10: 1 to the grinding rate ratio of metal level and alumina layer.
Preferably, said protective layer is the nitride metal level.
Preferably, said metal nitride layer material is TaN or TiN.
Preferably, said lapping liquid is 3: 1～10: 1 to the grinding rate ratio of metal level and metal nitride layer.
Preferably, said nitride metal layer thickness is 50～500 dusts.
Preferably, the formation method of said nitride metal level is chemical vapour deposition technique or physical vaporous deposition.
Compared with prior art, the present invention has the following advantages:
The present invention is owing to formed protective layer in the periphery circuit region groove and on the slot wedge metal level, the grinding rate of said protective layer is less than metal level, make when protective layer and metal level are ground, the metal level in core cell district remove sooner.When in the periphery circuit region groove and the protective layer on the slot wedge metal level when just having removed fully; Metal level in the core cell district has been milled to consistent or lower slightly with the metal level height of periphery circuit region; When therefore continuing grinding metal layer formation metal gates; The metal gates depression situation of periphery circuit region is improved greatly; Prevent that effectively metal gates from making less thick because of depression, cause metal gates resistivity that the serious problem that changes takes place, improved the electrical property and the reliability of semiconductor device.
Description of drawings
Fig. 1 to Fig. 4 is the generalized section that prior art forms metal gates;
Fig. 5 is the specific embodiment flow chart of metal gates formation method of the present invention;
Fig. 6 to Figure 15 is the first embodiment generalized section that the present invention forms method;
Figure 16 to Figure 25 is the second embodiment generalized section that the present invention forms method.
Embodiment
The inventor finds in the technology of existing formation metal gates; The device closeness in core cell district is high, and the critical size of grid is smaller, and the device closeness of periphery circuit region is low; The critical size of grid is also bigger, and metallic pattern area occupied ratio is also bigger; Because the influence of load effect (loading effect), periphery circuit region is different with epitaxial growth speed between the core cell district.Therefore, after forming metal level, the metal level height of the metal level aspect ratio periphery circuit region in core cell district is high, and on the periphery circuit region slot wedge, forms the slope; Follow-up grinding metal layer is when exposing the interlayer dielectric layer in core cell district; The metal level meeting over-lapping of periphery circuit region; And the metal gates that makes periphery circuit region depression occurs and makes and the metal gates less thick cause the serious variation of metal gates resistivity, causes semiconductor device failure.
To the problems referred to above, the inventor has proposed solution through researching and analysing, and is specifically as shown in Figure 5:
Execution in step S101 provides Semiconductor substrate; Said semiconductor substrate surface zone is divided into core cell district and periphery circuit region; Be formed with sacrificial oxide layer and polysilicon gate on the said Semiconductor substrate successively; Be formed with side wall on the Semiconductor substrate of said polysilicon gate both sides;
Execution in step S102 forms interlayer dielectric layer on Semiconductor substrate; Said inter-level dielectric laminar surface flushes with polysilicon gate and side wall top;
Execution in step S103 removes said polysilicon gate and sacrificial oxide layer, forms groove; The groove dimensions in said core cell district is less than the groove dimensions of periphery circuit region;
Execution in step S104 forms metal level on interlayer dielectric layer, and fills full said groove;
Execution in step S105 forms protective layer in the groove of periphery circuit region and on the slot wedge metal level;
Execution in step S106, grinding protection layer and metal level form metal gates to exposing interlayer dielectric layer, to the grinding rate of said protective layer less than metal level.
Metal gates formation method provided by the invention forms protective layer on the first metal level; And then protective layer and metal level carried out cmp to exposing the interlayer metal layer, the grinding rate of protective layer less than metal level, is ground the gate recess problem that metal gates that the back forms can avoid occurring periphery circuit region.Its reason is: through in the groove of periphery circuit region and on the metal level of slot wedge, forming protective layer; The grinding rate of said protective layer is less than metal level, and when making grinding metal layer and protective layer, the metal level in core cell district is removed sooner than periphery circuit region; When protective layer was removed fully, the metal layer thickness in core cell district was consistent or lower slightly with the metal layer thickness of periphery circuit region; Continue grinding metal layer to exposing interlayer dielectric layer; After forming metal gates; The metal gates surface of periphery circuit region flushes with interlayer dielectric layer and side wall; Depression do not occur, thereby prevent that effectively metal gates from causing metal gates resistivity that serious the variation taken place because of depression makes less thick, avoided semiconductor device to lose efficacy.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
First embodiment
Fig. 6 to Figure 15 is the first embodiment generalized section of metal gates formation method of the present invention.As shown in Figure 6, Semiconductor substrate 200 is provided; Said Semiconductor substrate 200 surf zones are divided into core cell district I and periphery circuit region II; Be formed with sacrificial oxide layer 202 and polysilicon gate 201 on the said Semiconductor substrate 200 successively.Wherein, the I in the core cell district, because the device closeness is high, so polysilicon gate 201a is relatively also many, and the critical size of polysilicon gate 201a is smaller; At periphery circuit region II, because the device closeness is low, polysilicon gate 201b is more sparse, and critical size is bigger.The technology of concrete formation polysilicon gate 201a, 201b is following: on Semiconductor substrate 200, form sacrificial oxide layer 202 with chemical vapour deposition technique; On sacrificial oxide layer 202, form polysilicon layer; On polysilicon layer, form photoresist layer, define gate patterns through exposure imaging; With the photoresist layer is mask, along pattern etching polysilicon layer and sacrificial oxide layer 202 to exposing Semiconductor substrate 200; Remove photoresist layer, form polysilicon gate 201a, 201b.
As shown in Figure 7, on the Semiconductor substrate 200 of polysilicon gate 201a, 201b both sides, form side wall 203.The technology of concrete formation side wall 203 is following: on Semiconductor substrate 200, form the silicon oxide layer that surrounds polysilicon gate 201 with chemical vapour deposition technique; On silicon oxide layer, form silicon nitride layer with chemical vapour deposition technique; With eat-backing method etch silicon nitride layer and silicon oxide layer, remove silicon nitride layer and silicon oxide layer on the Semiconductor substrate 200, keep the silicon oxide layer and the silicon nitride layer of polysilicon gate 201a, 201b both sides, form side wall 203.
As shown in Figure 8, on Semiconductor substrate 200, form interlayer dielectric layer 204; Said interlayer dielectric layer 204 surfaces flush with polysilicon gate 201a, 201b and side wall 203 tops.Concrete formation technology is following: on Semiconductor substrate 200, form the interlayer dielectric layer 204 that covers polysilicon gate 201a, 201b and side wall 203 with chemical vapour deposition technique; Grind interlayer dielectric layer 204 to exposing polysilicon gate 201a, 201b with chemical mechanical milling method, make interlayer dielectric layer 204 surfaces flush with polysilicon gate 201a, 201b and side wall 203 tops.
In the present embodiment; The material of said interlayer dielectric layer 204 is an oxide containing silicon, and the method that forms said layer dielectric layer 204 is high-density plasma (HDP:high density plasma) growing method or high-aspect-ratio (HARP:high aspect ratio process) growing method.
As shown in Figure 9, remove polysilicon gate 201a, 201b with the dry etching method; Remove sacrificial oxide layer 202 with the wet etching method, form groove.
In the present embodiment; Because the polysilicon gate 201b critical size of periphery circuit region II is greater than the critical size of the polysilicon gate 201a of core cell district I; Therefore after removing polysilicon gate 201a, 201b, the groove dimensions that the groove dimensions that forms at periphery circuit region II forms greater than the I in the core cell district.
Shown in figure 10, on Semiconductor substrate 200, form metal level 205, and fill full said groove.
In the present embodiment, the material of metal level 205 is an aluminum metal.Because the influence of load effect (loading effect); After having formed metal level 205; Metal level 205 surfaces are not smooth; Because greater than core cell district I internal channel size, make that the metal level 205 in the periphery circuit region II groove highly is lower than the groove inner metal layer 205 of core cell district I, and on the slot wedge of periphery circuit region II, form the slope in periphery circuit region II internal channel size.
Shown in figure 11, on metal level 205, form protective layer 206; Said protective layer 206 comprises the protective layer 206a that is positioned at core cell district I and is positioned at the protective layer 206b on periphery circuit region II groove and the slot wedge metal level.
In the present embodiment, protective layer 206 is an alumina layer, and thickness is 10～100 dusts, and the formation method is a thermal oxidation method, promptly metal level 205 surfaces is fed O2 or O3, and heating, makes metal level 205 surface oxygen change into fine and close alumina layer as protective layer 206.Because the metal level height on the metal level 205 aspect ratio periphery circuit region II of core cell district I is high; Therefore, the protective layers 206 that form along metal level 205 surface the protective layer 206a position of core cell district I than periphery circuit region II groove in and the protective layer 206b position of slot wedge high.
Shown in figure 12, on said protective layer 206, form photoresist layer 207, behind exposure imaging, define figure.The figure of said photoresist layer 207 definition is: only be retained in the photoresist layer 207 that reaches correspondence position on the slot wedge metal level in the periphery circuit region II groove.
Shown in figure 13, be mask with photoresist layer 207, to exposing metal level 205, keep protective layer 206b along pattern etching protective layer 206a.
In the present embodiment, the method for removing protective layer 206a is conventional wet etching method or dry etching method, is as the criterion not damage metal level 205.
Shown in figure 14, remove photoresist layer 207 with ashing method.
Shown in figure 15, grind said protective layer 206b and metal level 205 to exposing interlayer dielectric layer 204 with chemical mechanical milling method, metal level 205 is flushed with interlayer dielectric layer 204 and side wall 203, form metal gates 205a, 205b.
In the present embodiment, the lapping liquid that chemical mechanical milling method adopts is an alumina lap liquid, and said alumina lap liquid is 3: 1～10: 1 to the grinding rate ratio of metal level 205 and protective layer 206b.Because matcoveredn 206b on the metal level 205 of periphery circuit region II, make that the metal level 205 of core cellular zone I is removed faster in the process of lapping.When in the periphery circuit region II groove and the protective layer 206b on the slot wedge metal level 205 when removing fully, the thickness of the metal level 205 of core cell district I be reduced to periphery circuit region II groove in and the metal level 205 of slot wedge consistent or lower slightly; Continue grinding metal layer 205 when exposing interlayer dielectric layer 204 and form metal gates 205a, 205b, the metal gates 205b of periphery circuit region II is consistent with the height of the metal gates 205a of core cell district I, depression defect do not occur.
Second embodiment
Figure 16 to Figure 25 is the second embodiment generalized section of metal gates formation method of the present invention.Shown in figure 16, Semiconductor substrate 300 is provided; Said Semiconductor substrate 300 surf zones are divided into core cell district I and periphery circuit region II; Be formed with sacrificial oxide layer 302 and polysilicon gate 301a, 301b on the said Semiconductor substrate 300.Wherein, core cell district I, because the device closeness is high, polysilicon gate 301a is more, polysilicon gate 301a critical size is less; Then because the device closeness is lower, polysilicon gate 301b is less for periphery circuit region II, and critical size is also bigger.The technology of concrete formation polysilicon gate 301a, 301b is of first embodiment.
Shown in figure 17, on the Semiconductor substrate 300 of polysilicon gate 301a, 301b both sides, form side wall 303; Said side wall 303 comprises silicon oxide layer and silicon nitride layer.Concrete formation technology is of first embodiment.
Shown in figure 18, on Semiconductor substrate 300, form the interlayer dielectric layer 304 that covers polysilicon gate 301a, 301b and side wall 303 with chemical vapour deposition technique; Grind said interlayer dielectric layer 304 to exposing polysilicon gate 301a, 301b with chemical mechanical milling method, make interlayer dielectric layer 304 surfaces flush with polysilicon gate 301a, 301b and side wall 303.
Shown in figure 19, remove polysilicon gate 301a, 301b and sacrificial oxide layer 302, form groove.
In the present embodiment; Because the polysilicon gate 301b critical size of periphery circuit region II is greater than the critical size of the polysilicon gate 301a of core cell district I; Therefore after removing polysilicon gate 301a, 301b, the groove dimensions that the groove dimensions that forms at periphery circuit region II forms greater than the I in the core cell district.
Shown in figure 20, on Semiconductor substrate 300, form metal level 305, and fill full said groove.
In the present embodiment, the material of metal level 305 is electric conducting materials such as aluminium, copper or tungsten, and its formation method is conventional chemical vapour deposition technique or physical vaporous deposition.Because the influence of load effect, metal level 305 surfaces after the formation are also uneven, and are higher than metal level 305 thickness in the periphery circuit region II groove at metal level 305 thickness of core cell district I, and on the slot wedge of periphery circuit region II, form the slope.
Shown in figure 21, on metal level 305, form protective layer 306; Said protective layer 206 comprises the protective layer 306a that is positioned at core cell district I and is positioned at the protective layer 306b on periphery circuit region II groove and the slot wedge metal level.
In the present embodiment, the thickness of said protective layer 306 is 50～500 dusts; The material of said protective layer 306 is the nitride metal, for example tantalum nitride, titanium nitride; The formation method of said protective layer 306 comprises conventional chemical vapour deposition technique and physical vaporous deposition.
Shown in figure 22, on protective layer 306, form photoresist layer 307, behind exposure imaging, define figure; The figure of said photoresist layer 308 definition is: only keep the photoresist layer 307 that reaches correspondence position on the slot wedge metal level in the periphery circuit region II groove.
Shown in figure 23, be mask with photoresist layer 307, to exposing metal level 305, remove the protective layer 306a on the core cell district I metal level along pattern etching protective layer 307, keep in the periphery circuit region II groove and the protective layer 306b on the slot wedge metal level.
In the present embodiment, the method for etching protective layer 306 can be wet etching method or dry etching method.
Shown in figure 24, remove photoresist layer 307 with ashing method.
Shown in figure 25, grind said metal level 305 and protective layer 306b to exposing interlayer dielectric layer 304 with chemical mechanical milling method, form metal gates 305a, 305b.
In the present embodiment, the lapping liquid that chemical mechanical milling method adopts is an alumina lap liquid, is 3: 1～10: 1 to the grinding rate ratio of said metal level 305 and protective layer 306.Because matcoveredn 306b on the metal level 305 of periphery circuit region II, therefore in process of lapping, core cell district I metal level 305 is removed faster; When in the periphery circuit region II groove and the protective layer 306b on the slot wedge metal level 305 when being removed fully, the metal level 305 of core cell district I also be milled to periphery circuit region II groove in and the height of the metal level 305 of slot wedge consistent or lower slightly; Follow-up continuation grinding metal layer 305 forms metal gates 305a, 305b to exposing interlayer dielectric layer 304; The metal gates 305b surface of said periphery circuit region II flushes with side wall 303 and interlayer dielectric layer 304, depression do not occur.
Metal gates formation method provided by the invention is in the groove of periphery circuit region and the metal level of slot wedge on form protective layer, the grinding rate of said protective layer is less than metal level; Grinding metal layer and protective layer; Because the grinding rate of protective layer is lower than metal level, make the metal level in core cell district remove faster; When removing the protective layer of periphery circuit region fully, the metal layer thickness in core cell district and the metal layer thickness of periphery circuit region are unanimous on the whole; Continue grinding metal layer to exposing interlayer dielectric layer, form metal gates; Depression does not appear in metal gates surface and the side wall and the interlayer dielectric layer flush of said periphery circuit region, has avoided metal gates to cause metal gates resistivity that the serious problem that changes takes place because of depression makes less thick, improves the reliability of semiconductor device.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. the formation method of a metal gates is characterized in that, may further comprise the steps:
Semiconductor substrate is provided, and said Semiconductor substrate is divided into core cell district and periphery circuit region, is formed with sacrificial oxide layer and polysilicon gate on the said Semiconductor substrate successively, is formed with side wall on the Semiconductor substrate of said polysilicon gate both sides;
On said Semiconductor substrate, be formed with interlayer dielectric layer, said interlayer dielectric layer flushes with polysilicon gate and side wall top;
Remove polysilicon gate and sacrificial oxide layer, form groove, the groove dimensions in said core cell district is less than the groove dimensions of periphery circuit region;
On interlayer dielectric layer, form metal level, and fill full said groove;
In the periphery circuit region groove and on the slot wedge metal level, form protective layer;
Grind said protective layer and metal level to exposing interlayer dielectric layer, form metal gates, to the grinding rate of said protective layer less than metal level.
2. formation method according to claim 1 is characterized in that, the method for said grinding protection layer and metal level is a chemical mechanical milling method.
3. formation method according to claim 2 is characterized in that, said chemical mechanical milling method adopts alumina lap liquid.
4. formation method according to claim 1 is characterized in that, said protective layer is an alumina layer.
5. formation method according to claim 4 is characterized in that, said alumina layer adopts thermal oxidation method to form.
6. formation method according to claim 4 is characterized in that, said alumina layer thickness is 10～100 dusts.
7. according to claim 3 or 4 described formation methods, it is characterized in that said lapping liquid is 3: 1～10: 1 to the grinding rate ratio of metal level and alumina layer.
8. formation method according to claim 1 is characterized in that, said protective layer is the nitride metal level.
9. formation method according to claim 8 is characterized in that, said metal nitride layer material is TaN or TiN.
10. according to claim 3 or 8 described formation methods, it is characterized in that said lapping liquid is 3: 1～10: 1 to the grinding rate ratio of metal level and metal nitride layer.
11. formation method according to claim 8 is characterized in that, said nitride metal layer thickness is 50～500 dusts.
12. formation method according to claim 8 is characterized in that, the formation method of said nitride metal level is chemical vapour deposition technique or physical vaporous deposition.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183549A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing semiconductor device |
| CN104282564A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device and method for forming fin field effect transistor |
| CN105742184A (en) * | 2014-12-24 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Method For Forming Semiconductor Device Structure With Gate |
| CN106504983A (en) * | 2015-09-06 | 2017-03-15 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN113643979A (en) * | 2021-07-20 | 2021-11-12 | 上海华力集成电路制造有限公司 | HV CMOS CMP method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020098675A1 (en) * | 2000-03-16 | 2002-07-25 | Bih-Tiao Lin | Chemical mechanical polishing method for fabricating cooper damascene structure |
| CN1988123A (en) * | 2005-12-19 | 2007-06-27 | 富士通株式会社 | A semiconductor device, a manufacturing method thereof, and an evaluation method of the semiconductor device |
-
2010
- 2010-12-23 CN CN201010603417.9A patent/CN102543699B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020098675A1 (en) * | 2000-03-16 | 2002-07-25 | Bih-Tiao Lin | Chemical mechanical polishing method for fabricating cooper damascene structure |
| CN1988123A (en) * | 2005-12-19 | 2007-06-27 | 富士通株式会社 | A semiconductor device, a manufacturing method thereof, and an evaluation method of the semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104183549A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Method of manufacturing semiconductor device |
| CN104282564A (en) * | 2013-07-03 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device and method for forming fin field effect transistor |
| CN105742184A (en) * | 2014-12-24 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Method For Forming Semiconductor Device Structure With Gate |
| CN105742184B (en) * | 2014-12-24 | 2019-05-21 | 台湾积体电路制造股份有限公司 | Form the method with the semiconductor device structure of grid |
| US10522411B2 (en) | 2014-12-24 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor device structure with gate |
| US11469145B2 (en) | 2014-12-24 | 2022-10-11 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming semiconductor device structure with gate and resulting structures |
| CN106504983A (en) * | 2015-09-06 | 2017-03-15 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN106504983B (en) * | 2015-09-06 | 2020-12-22 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN113643979A (en) * | 2021-07-20 | 2021-11-12 | 上海华力集成电路制造有限公司 | HV CMOS CMP method |
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| CN102543699B (en) | 2014-04-02 |
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