KR100727438B1 - A forming method of metal line using diamond light carbon organic dielectric layer - Google Patents

A forming method of metal line using diamond light carbon organic dielectric layer Download PDF

Info

Publication number
KR100727438B1
KR100727438B1 KR1020010037442A KR20010037442A KR100727438B1 KR 100727438 B1 KR100727438 B1 KR 100727438B1 KR 1020010037442 A KR1020010037442 A KR 1020010037442A KR 20010037442 A KR20010037442 A KR 20010037442A KR 100727438 B1 KR100727438 B1 KR 100727438B1
Authority
KR
South Korea
Prior art keywords
metal wiring
dlc
organic insulating
layer
insulating film
Prior art date
Application number
KR1020010037442A
Other languages
Korean (ko)
Other versions
KR20030001105A (en
Inventor
류현규
조윤석
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020010037442A priority Critical patent/KR100727438B1/en
Publication of KR20030001105A publication Critical patent/KR20030001105A/en
Application granted granted Critical
Publication of KR100727438B1 publication Critical patent/KR100727438B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 금속배선 형성을 위한 하드마스크 역할을 할 수 있으며, 후속의 다층배선에 따른 층간절연막으로서의 역할을 동시에 할 수 있는 DLC 유기절연막을 사용함으로써, 금속배선의 측벽을 보호하여 공정 마진을 확보할 수 있고, 저유전 특성을 갖는 유기절연막에 따른 RC 지연을 최소화할 수 있는 DLC 유기절연막을 이용한 금속배선 형성 방법을 제공하는데 그 목적이 있다. 이를 위해 본 발명은, 소정 공정이 완료된 기판 상에 금속배선층을 형성하는 단계; 상기 금속배선층 상에 DLC(Diamond Like Carbon) 유기절연막과 금속배선을 정의하기 위한 감광막 패턴을 차례로 형성하는 단계; 상기 감광막 패턴을 마스크로하여 DLC 유기절연막을 식각함으로써 상기 금속배선층 일부을 노출시키는 단계; 상기 감광막 패턴 및 상기 DLC 유기절연막을 마스크로 하여 상기 금속배선층을 식각함과 동시에 상기 식각된 금속배선층 측벽에 상기 DLC 유기절연막의 측면 식각에 따라 발생된 부산물을 잔류시키는 단계; 및 상기 감광막의 스트립과 세정 공정을 진행하여 상기 부산물을 제거하는 단계를 포함하여 이루어지는 DLC 유기절연막을 이용한 금속배선 형성 방법을 제공한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by using a DLC organic insulating film which can serve as a hard mask for forming metal wiring and can also serve as an interlayer insulating film according to a subsequent multilayer wiring. It is an object of the present invention to provide a method for forming a metal wiring using a DLC organic insulating film which can secure a process margin by protecting sidewalls and minimize RC delay according to an organic insulating film having low dielectric properties. To this end, the present invention comprises the steps of forming a metal wiring layer on the substrate is completed a predetermined process; Sequentially forming a DLC (Diamond Like Carbon) organic insulating layer and a photoresist pattern for defining metal wiring on the metal wiring layer; Exposing a portion of the metal wiring layer by etching the DLC organic insulating layer using the photoresist pattern as a mask; Etching the metal wiring layer using the photoresist pattern and the DLC organic insulating layer as a mask, and simultaneously leaving by-products generated by side etching of the DLC organic insulating layer on sidewalls of the etched metal wiring layer; And removing the by-products by performing a strip and cleaning process of the photoresist film, and providing a metal wiring forming method using a DLC organic insulating film.

유기절연막, DLC, PFC, BEOL, FEOL. Organic insulation film, DLC, PFC, BEOL, FEOL.

Description

디엘씨 유기절연막을 이용한 금속배선 형성 방법{A forming method of metal line using diamond light carbon organic dielectric layer} A forming method of metal line using diamond light carbon organic dielectric layer}             

도 1a 내지 도 1d는 본 발명에 따른 금속배선 형성 공정을 도시한 단면도.
1A to 1D are cross-sectional views illustrating a metal wiring forming process according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 기판10: substrate

11 : 층간절연막11: interlayer insulating film

12 : 접착층12: adhesive layer

13 : 금속층13: metal layer

14 : 배리어금속층14: barrier metal layer

15 : DLC 유기절연막
15: DLC organic insulating film

본 발명은 반도체 소자의 제조 방법에 관한 것으로 특히, 금속배선 형성 방 법에 관한 것으로, 더욱 상세하게는 DLC 유기절연막을 이용한 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a metal wiring forming method, and more particularly, to a metal wiring forming method using a DLC organic insulating film.

최근의 반도체 제조 공정은 실리콘 기판 중에 트랜지스터를 형성하는 공정(기판 공정 또는 FEOL ; Front end of the line)과 배선을 형성하는 공정(배선 공정 또는 BEOL ; Backend of the line)으로 구분해서 생각하는 경우가 많다. Recent semiconductor manufacturing processes are often classified into a process of forming a transistor in a silicon substrate (substrate process or front end of the line) and a process of forming a wiring (wiring process or BEOL; backend of the line). many.

FEOL이란, 간단히 말하면 트랜지스터를 만드는 공정으로서 최근 고속을 추구하는 로직 디바이스의 요구가 엄격해지고 있는 바, 게이트 길이, 게이트 산화막 두께, 확산층 깊이 및 저항 등, 어느 것을 들어도 DRAM(Dynamic Random Access Memory)보다 한 세대 앞서고 있다. 여기에 혼재 디바이스의 시장이 증대되고 있어, 사양이 다른 트랜지스터를 하나의 칩 위에 만들고, 쌍방 모두 최대의 성능을 낼 것을 요구하고 있다. 이들을 실현하기 위한 FEOL기술 개발의 핵심은 신재료의 도입과 열 예산의 삭감이라고 할 수 있다.In short, FEOL is a process for making transistors, and the demand for logic devices that pursue high speeds has recently become more stringent. Therefore, the FEOL includes a gate length, a gate oxide thickness, a diffusion layer depth, and a resistance. Generation ahead. In addition, the market for mixed devices is increasing, and it is required to make transistors of different specifications on one chip and to achieve the maximum performance of both. The key to the development of FEOL technology to achieve these is the introduction of new materials and the reduction of thermal budget.

한편, BEOL (Back End Of Line)이란, 콘택(Contact) 이후의 공정을 지칭하는 바, 주로 다층배선과 최종 보호막 공정부터이다. 다층배선기술은 말할 필요 없이 로직 디바이스에 견인되어 있고, 이미 양산을 시작하고 있는 0.35㎛세대에서는 4층 배선이 주류가 되고 있다. On the other hand, BEOL (Back End Of Line) refers to the process after contact (Contact), mainly from the multi-layer wiring and the final protective film process. Needless to say, multi-layer wiring technology is attracted to logic devices, and four-layer wiring is becoming mainstream in the 0.35 micrometer generation, which is already in mass production.

하지만, BEOL에서의 과제는 RC지연이고, 배선의 RC지연이 LSI의 성능을 제한해 왔다. 예를 들면, 0.35㎛세대의 MPU(Micro processor Unit)에서는 지연 시간 전체 중에서 배선의 RC지연이 차지하는 비율은 20%~30%에 달한다. 회로 설계를 제외하고 프로세스에 한한다면, 배선 재료의 저저항화와 절연 재료의 저유전율화에 이 른다. 어떻게 신재료를 개발하고, 어떤 Timing에 도입할 것인가가 포인트이다. 0.15㎛ 이하에서는 배선간 폭의 축소에 따라 선간 용량이 현저히 증대되고, 용량에 의한 지연이 커다란 비율을 차지한다. 0.3㎛의 트랜지스터로 구성된 FO=3인 인버터를 이용하여 층간 절연막 저유전율화의 효과를 계산해 보면, 유전율 4.1의 SiO2를 이용하면 12%정도, 2.7의 막을 이용하면 20% 성능향상을 전망할 수 있다. 따라서, 저유전율 절연막을 도입하여 배선간 용량의 저하를 도모하는 것은 RC지연을 감소시킨 다음에 커다란 효과를 갖는다고 말할 수 있다. 그러나, 유전율이 3이하가 되면 유기물에 의지할 수 밖에 없으며, 이렇듯 만족할 만한 재료의 개발이 급선무로 떠오르고 있다. However, the challenge with BEOL is RC delay, and RC delay in wiring has limited the performance of LSIs. For example, in the 0.35 micrometer generation microprocessor unit (MPU), the RC delay of the wiring accounts for 20% to 30% of the total delay time. If the process is limited except circuit design, it leads to a lower resistance of the wiring material and a lower dielectric constant of the insulating material. The key point is how to develop new materials and to what timing. At 0.15 탆 or less, the line-to-line capacitance is remarkably increased as the width between wirings decreases, and the delay due to the capacitance occupies a large ratio. Calculating the effect of low dielectric constant interlayer insulation using an FO = 3 inverter composed of 0.3 µm transistors, we can expect a performance improvement of about 12% with SiO 2 with a dielectric constant of 4.1 and a 20% performance with a 2.7 film. have. Therefore, it can be said that introducing a low dielectric constant insulating film to reduce the inter-wire capacitance has a great effect after reducing the RC delay. However, when the dielectric constant is 3 or less, it is inevitable to rely on organic matter, and the development of such a satisfactory material is urgently emerging.

또한, 배선을 형성하는 방법으로서는 금후 다마신(Damascene) 프로세스가 주류가 될 것이다. 다마신 프로세스를 이용하면 배선을 고밀도화 할 수 가 있으며, 절연막 표면이 평탄화 되기 때문에 상부 층만큼 완화되지 않으면 안되었던 디자인 룰을 하층부부터 상층부까지 통일할 수 있고, 또 비아홀(Via hole)의 깊이가 일치하는 경계가 없는 구조를 실현할 수 있기 때문이다. 더욱이 Al의 반응성 이온 식각(Reactive Ion Etching; 이하 RIE라 함)를 하지 않기 때문에 부식의 염려가 적어진다는 것도 다마신 프로세스의 장점이며, RIE와 비교해서 경제적으로도 손색이 없다. In addition, the damascene process will become mainstream as a method of forming wiring. By using the damascene process, the wiring can be densified, and the design rules that had to be relaxed by the upper layer can be unified from the lower layer to the upper layer because the surface of the insulating film is flattened, and the depths of the via holes coincide. This is because a structure without boundaries can be realized. In addition, since Al is not reactive ion etching (hereinafter referred to as RIE), less corrosion is an advantage of the damascene process, and it is economically inferior to RIE.

그러나, Al 금속배선에서는 화학 기계적 연마(Chemical Mechanical Polishing; 이하 CMP라 함) 공정의 불안정성으로 인하여 RIE에 비해 큰 장점이 없게 되며, RC 지연을 개선하기 위한 문제가 부각되고 있다. 따라서, 이러한 문제점 을 동시에 해결하기 위하여 듀얼 다마신 공정에 대한 연구가 활발히 진행되고 있으나, 이는 특히 DRAM과 같은 메모리 소자에는 큰 장점이 없다. 그러므로, 금속배선의 식각 공정 마진을 얻고, RC 지연을 개선하기 위한 공정이 필요하게 된다.
However, due to the instability of the chemical mechanical polishing (CMP) process in Al metallization, there is no significant advantage over RIE, and a problem for improving RC delay has been highlighted. Therefore, in order to solve these problems at the same time, the research on the dual damascene process is actively conducted, but there is no great advantage, especially for memory devices such as DRAM. Therefore, there is a need for a process for obtaining an etching process margin of metallization and improving RC delay.

상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 금속배선 형성을 위한 하드마스크 역할을 할 수 있으며, 후속의 다층배선에 따른 층간절연막으로서의 역할을 동시에 할 수 있는 DLC 유기절연막을 사용함으로써, 금속배선의 측벽을 보호하여 공정 마진을 확보할 수 있고, 저유전 특성을 갖는 유기절연막에 따른 RC 지연을 최소화할 수 있는 DLC 유기절연막을 이용한 금속배선 형성 방법을 제공하는데 그 목적이 있다.
The present invention proposed to solve the above problems of the prior art, using a DLC organic insulating film that can serve as a hard mask for forming metal wiring, and at the same time can serve as an interlayer insulating film according to the subsequent multilayer wiring. Accordingly, an object of the present invention is to provide a method for forming a metal wiring using a DLC organic insulating film, which can secure a process margin by protecting sidewalls of the metal wiring and minimize the RC delay according to the organic insulating film having low dielectric properties.

상기와 같은 문제점을 해결하기 위해 본 발명은, 소정 공정이 완료된 기판 상에 금속배선층을 형성하는 단계; 상기 금속배선층 상에 DLC(Diamond Like Carbon) 유기절연막과 금속배선을 정의하기 위한 감광막 패턴을 차례로 형성하는 단계; 상기 감광막 패턴을 마스크로하여 DLC 유기절연막을 식각함으로써 상기 금속배선층 일부을 노출시키는 단계; 상기 감광막 패턴 및 상기 DLC 유기절연막을 마스크로 하여 상기 금속배선층을 식각함과 동시에 상기 식각된 금속배선층 측벽에 상기 DLC 유기절연막의 측면 식각에 따라 발생된 부산물을 잔류시키는 단계; 및 상기 감광막의 스트립과 세정 공정을 진행하여 상기 부산물을 제거하는 단계를 포함하여 이루어지는 DLC 유기절연막을 이용한 금속배선 형성 방법을 제공한다.In order to solve the above problems, the present invention comprises the steps of forming a metal wiring layer on the substrate is completed; Sequentially forming a DLC (Diamond Like Carbon) organic insulating layer and a photoresist pattern for defining metal wiring on the metal wiring layer; Exposing a portion of the metal wiring layer by etching the DLC organic insulating layer using the photoresist pattern as a mask; Etching the metal wiring layer using the photoresist pattern and the DLC organic insulating layer as a mask, and simultaneously leaving by-products generated by side etching of the DLC organic insulating layer on sidewalls of the etched metal wiring layer; And removing the by-products by performing a strip and cleaning process of the photoresist film, and providing a metal wiring forming method using a DLC organic insulating film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도 1a 내지 도 1d를 참조하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.

도 1a 내지 도 1d는 본 발명의 일실시예에 따른 DLC 유기절연막을 이용한 금속배선 형성 공정을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a metal wiring forming process using a DLC organic insulating film according to an embodiment of the present invention.

먼저, 도 1a에 도시된 바와 같이, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(10) 상에 층간절연막(11)과 접착층(12)을 형성한 다음, W 등의 금속층(13)과 Ti/TiN 등의 배리어금속층(14)을 형성한 다음, 그 상부에 DLC(Diamond Like Carbon) 유기절연막(15)을 형성한다.First, as shown in FIG. 1A, an interlayer insulating film 11 and an adhesive layer 12 are formed on a substrate 10 on which various elements for forming a semiconductor element are formed, and then a metal layer 13 such as W and Ti are formed. After forming the barrier metal layer 14 such as / TiN, a DLC (Diamond Like Carbon) organic insulating film 15 is formed thereon.

이어서, 금속배선을 정의하기 위해 DLC 유기절연막(15) 상에 감광막 패턴을 형성한다.Subsequently, a photosensitive film pattern is formed on the DLC organic insulating film 15 to define a metal wiring.

여기서, DLC 유기절연막(15)은 후속 금속배선층(13, 14) 형성에 따른 하드마스크로서의 역할과 상부에 형성될 또 다른 금속배선과의 층간절연막의 역할을 수행하는 바, RC 지연을 감소시키기 역할을 하는 바, 유전율이 2.0 내지 2.4로 매우 낮은 특성이 있다.Here, the DLC organic insulating film 15 serves as a hard mask according to the subsequent formation of the metallization layers 13 and 14 and serves as an interlayer insulating layer with another metallization to be formed thereon, thereby reducing the RC delay. As a result, the dielectric constant is very low as 2.0 to 2.4.

또한, 층간절연막(11)은 BPSG(Boro-Phospho Silicate Glass) 또는 HDP(High Density Plasma) 산화막 등의 통상의 층간절연을 위한 산화막 계열 물질막을 이용 한다.In addition, the interlayer insulating film 11 uses an oxide-based material film for conventional interlayer insulation such as Boro-Phospho Silicate Glass (BPSG) or High Density Plasma (HDP) oxide film.

다음으로 도 1b에 도시된 바와 같이, 감광막 패턴(16)을 마스크로 하여 DLC 유기절연막(15)을 선택적으로 식각하여 하부의 금속배선층(14)을 노출시키는 바, 산화막 PFC(Perfluorocarbon) 에천트(Etchant)를 이용하여 식각한다. Next, as shown in FIG. 1B, the DLC organic insulating layer 15 is selectively etched using the photoresist pattern 16 as a mask to expose the lower metal wiring layer 14, thereby forming an oxide film PFC (Perfluorocarbon) etchant ( Etchant) to etch.

다음으로 도 1c에 도시된 바와 같이, 감광막 패턴(16)과 DLC 유기절연막(15)을 마스크로 하여 금속배선층(13, 14)과 접착층(12)을 식각하여 층간절연막(11)이 노출되도록 하는 바, 이때 Cl2/BCl3가 포함된 가스를 이용한 건식식각을 이용하며, 금속배선층(13, 14) 식각시 DLC 유기절연막(15)의 측면이 식각되면서 식각가스와 DLC 유기절연막(15) 그리고, 금속배선층(13, 14) 등의 반응에 의한 부산물(17)이 형성되어 금속배선층(13, 14)의 측벽에 스페이서 형상으로 잔류하게 된다. 따라서, 이러한 부산물(17)에 의해 금속배선층(13, 14) 보호막 역할을 수행하게 되어 금속배선층(13, 14)의 손실을 방지하게 된다.Next, as shown in FIG. 1C, the metallization layers 13 and 14 and the adhesive layer 12 are etched using the photoresist pattern 16 and the DLC organic insulating layer 15 as a mask to expose the interlayer insulating layer 11. In this case, dry etching using a gas containing Cl 2 / BCl 3 is used, and the side surface of the DLC organic insulating layer 15 is etched when the metal wiring layers 13 and 14 are etched, thereby etching the etching gas and the DLC organic insulating layer 15 and By-products 17 formed by the reaction of the metallization layers 13 and 14 are formed and remain on the sidewalls of the metallization layers 13 and 14 in a spacer shape. Therefore, the by-products 17 serve as protective layers of the metallization layers 13 and 14 to prevent the loss of the metallization layers 13 and 14.

여기서, 산화막과 유기절연막(15)을 식각한 후에는 세정 공정을 거치지 않고 후속 공정인 하부의 금속배선층(14)에 대한 식각 공정을 진행한다. 유기 절연막(15)을 식각한 후에 측벽에 생기는 부산물(17)은 산화막을 식각하는 경우에 생기는 부산물에 비해 탄소 성분이 상대적으로 많은 불화 탄소막(CF layer)이다. 이 불화 탄소막은 Cl2/BCl3 base chemistry를 이용하여 금속층을 식각하는 공정에서 금속층에 비해 식각되는 반응 속도가 느리므로, 일종의 하드마스크 역할을 수행할 수 있으며, 금속배선층(14) 식각 공정 중에 측벽을 보호해주는 보호막(Passivation layer)인 탄소막의 재료를 공급해주는 공급원 역할을 수행할 수 있다. 이 때, 금속배선층(14) 측벽에 형성되는 부산물(17)은 탄소-불소-금속이 섞여 있는 일종의 혼합물의 형태이다. 이와 같이 유기 절연막을 이용하여 금속층을 식각하는 경우에 유기 절연막은 일종의 마스크 역할과 금속 측벽을 보호해 주는 부산물 막의 탄소 공급원 역할을 수행하는 이중적인 역할을 수행하게 된다. After etching the oxide film and the organic insulating film 15, the etching process is performed on the lower metal wiring layer 14, which is a subsequent process, without undergoing a cleaning process. The by-products 17 formed on the sidewalls after the organic insulating layer 15 is etched are a fluorinated carbon layer having a relatively higher carbon content than the by-products generated when the oxide film is etched. The carbon fluoride film has a slower reaction rate than that of the metal layer in the process of etching the metal layer using Cl 2 / BCl 3 base chemistry, and thus can act as a hard mask. It can serve as a source for supplying the material of the carbon film, which is a passivation layer that protects it. At this time, the by-products 17 formed on the sidewalls of the metallization layer 14 are in the form of a mixture of carbon-fluorine-metal. As such, when the metal layer is etched using the organic insulating layer, the organic insulating layer plays a dual role of serving as a kind of mask and a carbon source of the by-product layer protecting the metal sidewalls.

한편, DLC 유기절연막(15) 대신에 일반적인 산화막 계열을 사용하는 것도 생각할 수 있으나, 산화막 계열은 유전율이 상대적으로 높아 DLC 유기절연막(15)에 비해 RC 지연 효과의 개선이 떨어질 뿐아니라, 식각시 산소에 의해 식각가스 성분인 탄소와 반응하여 소멸되므로 부산물 형성이 거의 이루어지지 않는다.On the other hand, it is conceivable to use a general oxide film instead of the DLC organic insulating film 15. However, the oxide film has a relatively high dielectric constant, and the RC delay effect is inferior to that of the DLC organic insulating film 15. By reacting with and disappears with the carbon as an etching gas component by-product formation is hardly achieved.

또한, 감광막 만을 사용하여 부산물을 형성하는 방법도 있을 수 있으나, 미세 가공 기술에 따라 감광막의 두께가 얇아지게 됨에 따라 금속배선층(13, 14)의 보호막으로서의 역할을 수행할 만큼의 충분한 양의 부산물 생성이 안될 뿐만아니라, 본 발명에서는 DLC 유기절연막(15)을 후속의 층간절연막으로 사용할 수 있는 것과 비교했을 때, 효과면에서도 비교할 바가 되지 않는다.In addition, there may be a method of forming a by-product using only the photoresist film, but as the thickness of the photoresist film becomes thinner according to the microfabrication technique, a sufficient amount of the by-product is generated to serve as a protective film of the metallization layers 13 and 14. Not only this, but also in the present invention, when the DLC organic insulating film 15 can be used as a subsequent interlayer insulating film, the effect is not comparable.

다른 한편으로는, 무기계열의 저유전율막 예컨대, FSG (k = 3.3 ~ 3.6), HSQ ( k = 2.9 ~ 3.1) 또는 Xerogel (k = 2.0이하) 등을 사용할 수 있다고 일견 간주할 수도 있으나, 이러한 무기계열에 의해 생성된 부산물은 후속 세정 공정에 의해 용이하게 제거되지 않기 때문에 세정 공정에 따른 또다른 문제점을 야기할 수 있다.On the other hand, it may be considered that inorganic low dielectric constant films such as FSG (k = 3.3 to 3.6), HSQ (k = 2.9 to 3.1), or Xerogel (k = 2.0 or less) may be used. By-products produced by the inorganic series may cause another problem with the cleaning process because they are not easily removed by the subsequent cleaning process.

다음으로 도 1d에 도시된 바와 같이, 피알 스트립을 통해 잔류하는 감광막 패턴(16)을 제거한 후, 세정공정을 통하여 부산물(17)을 제거하는 바, ACT, EKC 또 는 ATMI 등의 케미칼을 이용한다.
Next, as shown in FIG. 1D, after removing the photoresist pattern 16 remaining through the PAL strip, the by-product 17 is removed through a cleaning process, and chemicals such as ACT, EKC, or ATMI are used.

상기한 바와 같이 이루어지는 본 발명은, 유기계열의 저유전율막 특히, DLC 유기절연막을 금속배선 식각시 하드마스크로 이용함으로써, 금속배선 형성시 금속배선층의 측벽 보호막인 부산물을 발생시켜 금속배선층의 손실을 방지함으로써 금속배선 형성에 따른 공정 마진을 확보할 수 있을 뿐만아니라, 후속 다층 배선시 층간절연막으로 이용함으로써, 저유전율에 의해 RC 지연을 감소시켜 소자의 빠른 동작 수행을 가능하게 할 수 있음을 실시예를 통해 알아 보았다.
According to the present invention, the organic dielectric low dielectric constant film, particularly the DLC organic insulating film, is used as a hard mask for etching the metal wiring, thereby generating by-products, which are sidewall protective films of the metal wiring layer, during the formation of the metal wiring, thereby reducing loss of the metal wiring layer. By preventing the process margins due to the formation of the metal wiring, as well as by using the interlayer insulating film in the subsequent multi-layer wiring, it is possible to reduce the RC delay due to the low dielectric constant, it is possible to perform the device faster operation Learned through.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은, 금속배선 형성에 따른 공정 마진을 확보함과 동시에 RC 지연을 감소시킬 수 있도록 함으로써, 궁극적으로 제품의 수율을 향상시킬 수 있으며, 전기적 특성을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.The present invention as described above, by ensuring the process margin due to the metal wiring formation and at the same time reduce the RC delay, can ultimately improve the yield of the product, can be expected to have an excellent effect to improve the electrical properties have.

Claims (5)

반도체 소자 제조 방법에 있어서,In the semiconductor device manufacturing method, 소정 공정이 완료된 기판 상에 금속배선층을 형성하는 단계;Forming a metallization layer on the substrate on which the predetermined process is completed; 상기 금속배선층 상에 DLC(Diamond Like Carbon) 유기절연막과 금속배선을 정의하기 위한 감광막 패턴을 차례로 형성하는 단계;Sequentially forming a DLC (Diamond Like Carbon) organic insulating layer and a photoresist pattern for defining metal wiring on the metal wiring layer; 상기 감광막 패턴을 마스크로하여 DLC 유기절연막을 식각함으로써 상기 금속배선층 일부을 노출시키는 단계;Exposing a portion of the metal wiring layer by etching the DLC organic insulating layer using the photoresist pattern as a mask; 상기 감광막 패턴 및 상기 DLC 유기절연막을 마스크로 하여 상기 금속배선층을 식각함과 동시에 상기 식각된 금속배선층 측벽에 상기 DLC 유기절연막의 측면 식각에 따라 발생된 부산물을 잔류시키는 단계; 및Etching the metal wiring layer using the photoresist pattern and the DLC organic insulating layer as a mask, and simultaneously leaving by-products generated by side etching of the DLC organic insulating layer on sidewalls of the etched metal wiring layer; And 상기 감광막의 스트립과 세정 공정을 진행하여 상기 부산물을 제거하는 단계Performing the cleaning process with the strip of the photoresist to remove the by-products 를 포함하여 이루어지는 DLC 유기절연막을 이용한 금속배선 형성 방법.Metal wiring forming method using a DLC organic insulating film comprising a. 제 1 항에 있어서,The method of claim 1, 상기 DLC 유기절연막의 식각시, PFC(Prefluorocarbon) 에천트를 이용하는 것을 특징으로 하는 DLC 유기절연막을 이용한 금속배선 형성 방법.When etching the DLC organic insulating layer, using a PFC (Prefluorocarbon) etchant, metal wiring forming method using a DLC organic insulating layer, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 금속배선층의 식각은, Cl2/BCl3가 포함된 가스를 이용한 건식식각인 것을 특징으로 하는 DLC 유기절연막을 이용한 금속배선 형성 방법.The etching of the metal wiring layer is a metal etching method using a DLC organic insulating film, characterized in that the dry etching using a gas containing Cl 2 / BCl 3 . 제 1 항에 있어서,The method of claim 1, 상기 세정시, ACT, EKC 또는 ATMI를 이용하는 것을 특징으로 하는 DLC 유기절연막을 이용한 금속배선 형성 방법.The metal wiring forming method using the DLC organic insulating film, characterized in that for cleaning, using ACT, EKC or ATMI. 제 1 항에 있어서,The method of claim 1, 상기 금속배선층은, Al과 Ti/TiN이 적층된 것 임을 특징으로 하는 DLC 유기절연막을 이용한 금속배선 형성 방법.The metal wiring layer is a metal wiring forming method using a DLC organic insulating film, characterized in that the Al and Ti / TiN laminated.
KR1020010037442A 2001-06-28 2001-06-28 A forming method of metal line using diamond light carbon organic dielectric layer KR100727438B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010037442A KR100727438B1 (en) 2001-06-28 2001-06-28 A forming method of metal line using diamond light carbon organic dielectric layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010037442A KR100727438B1 (en) 2001-06-28 2001-06-28 A forming method of metal line using diamond light carbon organic dielectric layer

Publications (2)

Publication Number Publication Date
KR20030001105A KR20030001105A (en) 2003-01-06
KR100727438B1 true KR100727438B1 (en) 2007-06-13

Family

ID=27711760

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010037442A KR100727438B1 (en) 2001-06-28 2001-06-28 A forming method of metal line using diamond light carbon organic dielectric layer

Country Status (1)

Country Link
KR (1) KR100727438B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058507A (en) * 1998-08-17 2000-02-25 Sony Corp Manufacture of semiconductor device
JP2001068428A (en) * 1999-08-26 2001-03-16 Fuji Electric Co Ltd Manufacture of silicon carbide semiconductor element
KR20030001082A (en) * 2001-06-28 2003-01-06 주식회사 하이닉스반도체 A forming method of metal line using divinyl siloxane biszocylclobutene benzocyclobutene organic dielectric layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058507A (en) * 1998-08-17 2000-02-25 Sony Corp Manufacture of semiconductor device
JP2001068428A (en) * 1999-08-26 2001-03-16 Fuji Electric Co Ltd Manufacture of silicon carbide semiconductor element
KR20030001082A (en) * 2001-06-28 2003-01-06 주식회사 하이닉스반도체 A forming method of metal line using divinyl siloxane biszocylclobutene benzocyclobutene organic dielectric layer

Also Published As

Publication number Publication date
KR20030001105A (en) 2003-01-06

Similar Documents

Publication Publication Date Title
US7871923B2 (en) Self-aligned air-gap in interconnect structures
US7419916B2 (en) Manufacturing method of semiconductor device
KR100588373B1 (en) Method for forming semiconductor device
KR100430472B1 (en) Method for forming wiring using dual damacine process
TW200522203A (en) Method for fabricating semiconductor device
JP2003282710A (en) METHOD OF FORMING VIA AND TRENCH BY CONTROLLING SiC ETCHING RATE AND SELECTIVITY
US6278147B1 (en) On-chip decoupling capacitor with bottom hardmask
JP2010161166A (en) Method of forming interconnection
CN106409752B (en) Method for forming semiconductor structure
CN1661799B (en) Semiconductor device
KR100441685B1 (en) Dual damascene process
KR100727438B1 (en) A forming method of metal line using diamond light carbon organic dielectric layer
KR100400302B1 (en) Method for manufacturing semiconductor device
JP2000294545A (en) Semiconductor device and manufacture of the same
KR20030001082A (en) A forming method of metal line using divinyl siloxane biszocylclobutene benzocyclobutene organic dielectric layer
KR20080001714A (en) Method of manufacturing a semiconductor device
JPH1041385A (en) Semiconductor device and manufacture thereof
JP2006032721A (en) Fabrication process of semiconductor device
KR20010059539A (en) Method for forming metal line of semiconductor device
JPH11186274A (en) Dual damascene technique
KR100439111B1 (en) Method for forming metal line in semiconductor device
KR20060116360A (en) Method for fabricating metal line using dual damascene in semiconductor device
KR100475536B1 (en) Method of manufacturing a semiconductor device
US20060281301A1 (en) Method for manufacturing dual damascene pattern
KR20010113520A (en) A process for manufacturing an integrated circuit including a dual-damascene structure and a capacitor

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
G170 Re-publication after modification of scope of protection [patent]
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee