KR100900242B1 - Structure of metal line - Google Patents
Structure of metal line Download PDFInfo
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- KR100900242B1 KR100900242B1 KR1020020070727A KR20020070727A KR100900242B1 KR 100900242 B1 KR100900242 B1 KR 100900242B1 KR 1020020070727 A KR1020020070727 A KR 1020020070727A KR 20020070727 A KR20020070727 A KR 20020070727A KR 100900242 B1 KR100900242 B1 KR 100900242B1
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- metal wiring
- dummy pattern
- passive connection
- metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 67
- 239000002184 metal Substances 0.000 title claims abstract description 67
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- 239000011800 void material Substances 0.000 abstract description 7
- 238000011156 evaluation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 보이드 형성을 억제하고 금속 배선의 신뢰성을 향상시킬 수 있는 금속 배선 구조에 관해 개시한 것으로서, 금속 배선과, 금속 배선과 일정 거리를 유지하도록 형성된 더미 패턴과, 금속 배선과 더미 패턴을 연결시키는 수동 연결부를 포함하며, 상기 금속 배선, 더미 패턴 및 수동연결부는 동일 금속막을 반응성 이온 식각하여 형성한다. 따라서, 본 발명은 더미 패턴을 이용하여 수동 연결부를 형성함으로써, 보이드 형성을 억제하고 금속 배선의 신뢰성을 향상시킬 수 있다.The present invention discloses a metal wiring structure capable of suppressing void formation and improving the reliability of metal wiring. The present invention relates to a metal wiring, a dummy pattern formed to maintain a certain distance from the metal wiring, and a metal wiring and a dummy pattern. And a passive connection portion, wherein the metal wire, the dummy pattern, and the passive connection portion are formed by reactive ion etching the same metal layer. Therefore, the present invention can form a passive connection using a dummy pattern, thereby suppressing void formation and improving the reliability of the metal wiring.
Description
도 1은 본 발명에 따른 금속 배선 구조를 설명하기 위한 평면도.1 is a plan view for explaining a metal wiring structure according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1. 금속 배선 3. 비아 홀1.
5. 더미 패턴 7. 수동 연결부5. Dummy
A. 수동 연결부의 폭 B. 수동 연결부의 길이A. Width of the manual connection B. Length of the manual connection
C. 수동 연결부의 위치C. Location of manual connection
본 발명은 반도체 장치에 관한 것으로, 보다 구체적으로는 보이드(void) 형성을 억제하고 금속 배선의 신뢰성을 향상시킬 수 있는 금속 배선 구조에 관한 것이다.BACKGROUND OF THE
반도체 소자에 사용되는 금속 배선에 전류가 흐르게 되면 전류의 방향 또는 금속 배선 내의 위치에 따라 스트레스(stress) 차이가 존재하여 보이드(void)가 형성된다. 이러한 보이드 형성은 Y.-J.Park and C.V.Thompson, JAP,82,4277(1997)에 개재된 바 있다. When a current flows through a metal wire used in a semiconductor device, a stress difference exists depending on a direction of the current or a position in the metal wire, thereby forming voids. Such void formation has been described in Y.-J. Park and C. V. Tommpson, JAP, 82, 4277 (1997).
한편, 상기 보이드는 배선의 저항을 증가시키고 배선의 신뢰성을 악화시키게 된다. 특히, 듀얼 다마신(dual damascene) 구조를 적용하는 구리 등의 금속 배선의 경우, 비아 홀과 후속의 금속 배선이 연결되어 있어 전기적 저항은 감소하는 반면에 구리 원자의 흐름을 막아주는 계면이 존재하지 않음으로써 보이드 형성은 금속 배선 신뢰성에 치명적인 문제점이 있었다.On the other hand, the voids increase the resistance of the wiring and deteriorate the reliability of the wiring. In particular, in the case of metal wiring such as copper employing a dual damascene structure, the via hole and the subsequent metal wiring are connected so that the electrical resistance is reduced while the interface which prevents the flow of copper atoms does not exist. As a result, void formation had a fatal problem in the reliability of metal wiring.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 금속 배선과 더미 패턴을 연결시키는 수동 연결부를 포함한 구조를 가짐으로써, 상기 수동 연결부의 위치에 따라 스트레스 차이가 발생하는 속도를 감소시켜 수명을 연장시킬 수 있어 금속 배선의 신뢰성을 향상시킬 수 있는 금속 배선 구조를 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the conventional problems, and has a structure including a passive connection for connecting the metal wiring and the dummy pattern, reducing the speed at which the stress difference occurs according to the position of the passive connection life It is an object of the present invention to provide a metal wiring structure that can be extended to improve the reliability of the metal wiring.
상기 목적을 달성하기 위한 본 발명에 따른 금속 배선 구조는 금속 배선과,금속 배선과 일정 거리를 유지하도록 형성된 더미 패턴과, 금속 배선과 더미 패턴을 연결시키는 수동 연결부를 포함하며, 상기 금속 배선, 더미 패턴 및 수동연결부는 동일 금속막을 반응성 이온 식각하여 형성하는 것을 특징으로 한다. Metal wiring structure according to the present invention for achieving the above object includes a metal wiring, a dummy pattern formed to maintain a predetermined distance from the metal wiring, and a passive connection for connecting the metal wiring and the dummy pattern, the metal wiring, dummy The pattern and the passive connection may be formed by reactive ion etching the same metal layer.
상기 금속 배선은 듀얼 다마신 구조를 가진다.The metal wiring has a dual damascene structure.
상기 금속막은 구리, 알루미늄 및 텅스텐 중 어느 하나의 그룹으로부터 형성된다.The metal film is formed from any one group of copper, aluminum and tungsten.
상기 수동연결부는 0.1∼0.5㎛의 폭, 1∼100㎛의 길이를 가지며, 금속 배선의 양단 사이에 형성된다.The passive connection portion has a width of 0.1 to 0.5 µm and a length of 1 to 100 µm and is formed between both ends of the metal wiring.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 금속 배선 구조를 설명하기 위한 평면도로서, 도 1을 참조하여 본 발명에 따른 금속 배선 구조를 설명하면 다음과 같다.1 is a plan view illustrating a metal wiring structure according to the present invention. Referring to FIG. 1, the metal wiring structure according to the present invention will be described as follows.
본 발명의 일실시예에 따른 금속 배선 구조는, 도 1에 도시된 바와 같이, 금속 배선(1)과, 금속 배선(1)과 일정 거리를 유지하도록 형성된 더미 패턴(5)과, 금속 배선(1)과 더미 패턴(5)을 연결시키는 수동 연결부(passive interconnect segment)(7)를 포함하여 구성된다. 도면부호 3은 금속 배선(1)과 상부 또는 하부 의 금속배선(미도시)을 연결시키는 통로인 비아 홀을 도시한 것이다.As shown in FIG. 1, a metal wiring structure according to an embodiment of the present invention includes a
상기 금속 배선(1), 더미 패턴(5) 및 수동 연결부(7)는 구리, 알루미늄 및 텅스텐 중 어느 하나의 금속막(미도시)을 스퍼터링(sputtering) 방식에 의해 형성한 다음, 상기 금속막을 반응성 이온 식각(reactive ion etching)하여 동시에 형성한다. The
또는, 상기 금속 배선(1), 더미 패턴(5) 및 수동 연결부(7)는 듀얼 다마신 구조를 적용하여 형성할 수도 있다. Alternatively, the
상기 듀얼 다마신 구조를 적용하여 상기 금속 배선(1), 더미 패턴(5) 및 수동 연결부(7)를 형성하는 과정을 알아보면 다음과 같다. 먼저, 절연막을 포함한 반도체 기판에 상기 절연막을 식각하여 트렌치를 형성한 다음, 상기 트렌치를 포함한 결과물에 구리, 알루미늄 및 텅스텐 중 어느 하나의 금속막(미도시)을 매립하고 나 서, 상기 금속막을 씨엠피하여 각각의 금속 배선(1), 더미 패턴(5) 및 수동 연결부(7)를 형성한다. The process of forming the
상기 더미 패턴(5)은 씨엠피(Chemical Mechnical Polishing) 공정에서 평탄화 용도로 사용되는 것으로서, 크기와 모양에 상관없다.The
한편, 상기 수동 연결부(7)는 전자 이동(electromigration), 스트레스 이동(stress migration) 또는 열사이클(thermal cycle) 등의 배선 신뢰성 평가를 선진행하여 금속 배선 수명의 결과에 따라 폭, 길이 및 형성 위치 등을 결정 할 수 있다. On the other hand, the
상기 배선 신뢰성 평가를 진행함으로써, 결정된 수동 연결부(7)의 폭(B)은 0.1∼0.5㎛, 길이(C)는 1∼100㎛ 이내에서 적용가능하다. 또한, 상기 수동 연결부(7)의 형성 위치로는 금속 배선(1)의 양단 사이이며, 상기 금속 배선의 양단 사이의 어느 부분이든지는 상관없다.By conducting the above wiring reliability evaluation, the determined width B of the
본 발명에 따르면, 금속 배선과 더미 패턴을 연결시키는 수동 연결부를 포함한 구조를 가짐으로써, 보이드 형성을 억제하여 금속 배선의 신뢰성 및 수명을 연장시킨다. 또한, 본 발명의 더미 패턴은 반응성 이온 식각을 이용하는 경우와 듀얼 다마신 구조를 이용하는 경우 모두 적용가능하다.According to the present invention, by having a structure including a passive connection portion connecting the metal wiring and the dummy pattern, void formation is suppressed to extend the reliability and life of the metal wiring. In addition, the dummy pattern of the present invention is applicable to both the case of using reactive ion etching and the case of using a dual damascene structure.
한편, 상기 수동 연결부를 형성함에 따라 금속 배선 구조가 차지하는 면적이 넓어질 수 있지만, 본 발명에서는 씨엠피 공정의 평탄화 용도로 사용되는 더미 패턴을 이용함으로써, 추가적인 면적의 증가없이 수동 연결부를 형성할 수 있다.Meanwhile, although the area occupied by the metal wiring structure may be increased by forming the passive connection part, in the present invention, by using a dummy pattern used for planarization of the CMP process, the passive connection part may be formed without increasing an additional area. have.
이상에서와 같이, 본 발명은 더미 패턴을 이용하여 수동 연결부를 형성함으로써, 보이드 형성을 억제하고 금속 배선의 신뢰성을 향상시킨다. As described above, the present invention forms a passive connection by using a dummy pattern, thereby suppressing void formation and improving reliability of metal wiring.
또한, 본 발명에서는 전자 이동, 스트레스 이동 또는 열사이클 등의 배선 신뢰성 평가를 선진행하여 금속 배선 수명의 결과에 따라 폭, 길이 및 형성 위치 등을 결정 할 수 있다. Further, in the present invention, the wiring reliability evaluation such as electron transfer, stress transfer, or thermal cycle can be advanced to determine the width, length, formation position, and the like according to the result of the metal wiring life.
한편, 본 발명에서는 씨엠피 공정의 평탄화 용도로 사용되는 더미 패턴을 이용하여 수동 연결부를 형성함으로써, 수동 연결부를 형성하는데 필요한 면적을 줄일 수 있다.On the other hand, in the present invention by forming a passive connection using a dummy pattern used for the planarization of the CMP process, it is possible to reduce the area required to form the passive connection.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (7)
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| KR1020020070727A KR100900242B1 (en) | 2002-11-14 | 2002-11-14 | Structure of metal line |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990047436A (en) * | 1997-12-04 | 1999-07-05 | 윤종용 | Via Formation Method in Semiconductor Device |
| KR20010045578A (en) * | 1999-11-05 | 2001-06-05 | 박종섭 | Metal interconnection line structure in semiconductor device |
| KR20020010814A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Method of forming metal interconnection |
| KR20020046469A (en) * | 2000-12-14 | 2002-06-21 | 박종섭 | Pattern for reducing oxide erosion during chemical mechanical polishing of metal |
-
2002
- 2002-11-14 KR KR1020020070727A patent/KR100900242B1/en active IP Right Grant
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990047436A (en) * | 1997-12-04 | 1999-07-05 | 윤종용 | Via Formation Method in Semiconductor Device |
| KR20010045578A (en) * | 1999-11-05 | 2001-06-05 | 박종섭 | Metal interconnection line structure in semiconductor device |
| KR20020010814A (en) * | 2000-07-31 | 2002-02-06 | 박종섭 | Method of forming metal interconnection |
| KR20020046469A (en) * | 2000-12-14 | 2002-06-21 | 박종섭 | Pattern for reducing oxide erosion during chemical mechanical polishing of metal |
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