JP4258914B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device effective for improving the reliability of wiring used in an integrated circuit, particularly for improving electromigration resistance.
[0002]
With the recent high integration and miniaturization of LSIs, especially in logic LSIs, the performance of multilayer wiring is rapidly gaining importance as a major factor governing the performance of LSIs themselves. The current wiring is mainly a multilayer film wiring mainly composed of an aluminum alloy film. In practical LSI, 5 to 6 wirings are laminated. Further, in order to reduce the wiring delay and improve the performance, a high-density current as high as 10 ⁵ A / cm ² flows in these wirings. On the other hand, it is known that under such a high current density condition, a so-called electromigration phenomenon (EM phenomenon) in which metal atoms in the wiring move to generate voids or hillocks is likely to occur. This EM phenomenon causes a disconnection of wiring or a short circuit between adjacent wirings, leading to a decrease in LSI reliability.
[0003]
[Prior art]
In order to achieve high performance and high reliability of integrated circuits, attempts have been made to use copper wiring instead of wiring using conventional aluminum alloy, and it is being put into practical use. This is because the wiring resistance can be reduced because the specific resistance of copper is lower than that of aluminum alloy. In addition, the copper wiring is promising to be produced by the damascene process, and is actively researched and developed.
[0004]
Furthermore, it is estimated that the electromigration resistance is about 10 times higher than that of the aluminum alloy because the melting point of copper is higher than that of the aluminum alloy.
[0005]
On the other hand, various means have been studied and disclosed as a method for making the time until a wiring failure due to electromigration occurs longer than before. For example, in Japanese Patent Laid-Open No. 10-256364, an Al—Si—Cu alloy film is provided on the uppermost layer of the wiring, so that the wiring is disconnected by using an aluminum supply source that was not provided in the conventional structure without this film. The time to reach is lengthened.
[0006]
[Problems to be solved by the invention]
The present inventor performed in-situ observation using a TEM (transmission electron microscope) of how the wiring deteriorated due to the EM phenomenon using the copper wiring produced by the damascene process. The result is schematically shown in FIG.
[0007]
The copper wiring used here is a single layer wiring having a width of 0.2 μm, a height of 0.45 μm, and a length of 70 μm. Tantalum nitride (TaN) having a thickness of 25 nm is attached as a barrier metal to both side surfaces and the bottom surface of the wiring. On the upper surface of the wiring, silicon nitride (SiN) having a thickness of 50 nm is laminated as an insulating film and to prevent diffusion of copper.
[0008]
When a current of 4.5 mA was passed through the wiring, it was observed that a void was generated from the interface between SiN and copper (Cu) near the cathode end after about 1 hour. This current of 4.5 mA corresponds to a current density of 5 × 10 ⁶ A / cm ² in Cu metal. This is a severe condition of about 50 times the current in practical use.
[0009]
Thereafter, it was observed that the void did not spread downward or expanded along the grain boundary in the Cu metal, but rapidly expanded along the interface between SiN and Cu. Along with that, the wiring resistance increased, and finally it was broken.
[0010]
That is, when a void is generated, the proportion of Cu metal in the wiring cross section locally decreases in the void area. Therefore, the current is concentrated on this portion. When the size of the void continues to expand in the cross-sectional direction or the wiring width direction, the current concentration is further accelerated, and eventually Joule heat is generated, leading to Cu melting. This is considered to be a process leading to disconnection.
[0011]
From this, it is clear that the electromigration resistance of Cu wiring is affected by the ease of diffusion of atoms at the interface between SiN and Cu, which is an insulating film, rather than the inherent properties of Cu such as grain boundaries and melting points. became. Since the deterioration at the interface eventually leads to disconnection of the wiring, it is necessary to prevent the generation and expansion of voids at the interface between the insulating film and Cu.
[0012]
As a means for preventing the generation and expansion of voids at the interface between the insulating film and Cu, for example, a method of covering not only the side surface and the bottom surface of the Cu wiring but also the upper surface with a barrier metal is conceivable. Such a method is disclosed in Japanese Laid-Open Patent Publication No. Hei 6-275612, a manufacturing method of an integrated circuit, Japanese Laid-Open Patent Publication No. 9-55427, Japanese Laid-Open Patent Publication No. 7-263589 and the like.
[0013]
However, these methods have the following drawbacks.
[0014]
First of all, there is a drawback that the manufacturing process is complicated and many. In a normal damascene process, after depositing a barrier material and a conductive material such as copper or aluminum in an opening formed on a substrate, the conductive material other than the opening is removed by CMP or the like.
[0015]
However, for example, in Japanese Patent Laid-Open No. 6-275612, it is necessary to remove with good control so that the copper surface of the opening is a step lower than the surroundings. After this, it is said that it is necessary to deposit a barrier material and perform another CMP. Obviously, this increases the number of processes than usual, resulting in high manufacturing costs.
[0016]
Secondly, as disclosed in JP-A-6-275612, the upper surface of copper, which is a conductive material, is made lower than the periphery of the opening so that a barrier material is placed thereon. The rate is low. For this reason, the wiring resistance is higher than that of a structure manufactured by a normal damascene process. As a result, the performance of the integrated circuit is degraded.
[0017]
In view of the above points, the present invention has an object to provide a simple technique that can increase the electromigration resistance of a copper wiring produced mainly by a damascene process.
[0018]
[Means for Solving the Problems]
As a result of intensive studies by the present inventors to solve the problem, the above-described problem has a wiring and a first through via connected to the wiring and electrically independent from the other wiring. The wiring has an upper surface covered with an insulating film, and has an uppermost layer made of copper or a copper alloy, and a lowermost layer made of a refractory metal or a refractory metal nitride covering the side and bottom surfaces of the uppermost layer. a multilayer film, said first through vias are embedded in the same layer configuration as the multilayer film, and in close contact with the top layer which is exposed to the bottom of the opening that is opened in the insulating film, wherein This is solved by providing a semiconductor device characterized in that it is arranged only on the cathode side of the uppermost layer .
[0019]
That is, in the semiconductor device of the present invention, the other wiring has a first through-via you are electrically independent, so as to constitute on the wiring made from the multi-layer film. Thus, even if a void is generated at the interface between the insulating film and the uppermost layer due to electromigration and spreads along the interface, the barrier metal and the uppermost layer made of the refractory metal or refractory metal nitride are formed. Because of the good adhesion at the interface, the expansion of the void is prevented, and the growth of the void stops there.
[0020]
In addition, the above-described problem can be solved by using a semiconductor device in which the opening has a width exceeding the width of the wiring, and the first through-through via is expanded in the width direction of the wiring.
[0021]
That is, in the semiconductor device of the present invention, the width of the opening exceeds the width of the wiring, and the first through via is configured to be a semiconductor device bulging in the width direction of the wiring. By doing so, the cross section of the wiring in the portion in contact with the first through via is completely surrounded by the refractory metal or refractory metal nitride as the barrier metal, and the electromigration causes the insulating film and the uppermost layer to be surrounded. Even if a void is generated at the interface and spreads along the interface, the expansion of the void is prevented because the adhesiveness is good at the interface between the barrier metal made of refractory metal or refractory metal nitride and the uppermost layer, and the wiring Void growth stops there because it is the first through via with a diameter that exceeds the width of. Therefore, an increase in wiring resistance is suppressed, and electromigration resistance is increased.
[0024]
FIG. 1 shows an example in which a wiring is manufactured by a single damascene method according to the present invention.
[0025]
First, a first through via is formed on the wiring. A barrier metal that is a high melting point adhesive layer such as TaN or TiN is used at the bottom of the first through via, and the upper portion of the cross section of the uppermost layer in contact with the barrier metal is covered with the barrier metal. Therefore, as observed by in-situ observation, even if voids are generated at the interface between the insulating film and the uppermost layer due to electromigration and spread along the interface, the adhesion at the interface between the barrier metal and the uppermost layer is good. Voids are prevented from expanding and growth stops there. Therefore, an increase in resistance is suppressed and electromigration resistance is increased. FIG. 2 shows an example in which wiring is manufactured by the dual damascene method according to the present invention. The first through via is formed simultaneously with the second through via. For this reason, it is sufficient to produce the second through via at the same time, and the number of processes does not increase particularly.
[0026]
In the first through via as shown in FIGS. 1 and 2, voids can be generated in various places. Therefore, if as many as possible are installed along the longitudinal direction of one wiring, the voids are enlarged. It is effective in suppressing both occurrence and occurrence.
[0027]
In addition, voids are usually easily generated at the cathode end of the wiring. For this reason, when many first through vias cannot be arranged at an arbitrary position in the wiring layout, it is preferable to place them on the cathode side or the side that has a high probability of becoming a cathode.
[0028]
As shown in FIG. 1, the shape of the first through via needs to be large enough to cover the width direction of the wiring to be connected in order to completely prevent the void from expanding. If the first through via is cylindrical or conical, the diameter of the bottom surface of the first through via may be equal to or greater than the wiring width. As a result, the cross section of the wiring in the portion in contact with the first through via is completely surrounded by the barrier metal, which is the lowermost layer made of refractory metal or refractory metal nitride, and the expansion of the void can be prevented.
[0029]
However, if the width of the wiring is wide or the width of the first through via cannot be made too large for the convenience of the process, as shown in FIG. You may arrange. In this case, assuming that the void extends to the wiring width, it is desirable that the contact surface between the first through via and the wiring extends to the entire wiring width as viewed from the length direction of the wiring.
[0030]
Further, it is desirable that the distance in the longitudinal direction of the wiring is within about twice the width of the wiring. By doing in this way, even if the void that has expanded to the wiring width in the worst case expands, the expansion can be effectively prevented.
[0031]
In the above description, the material of the uppermost layer is not particularly specified, but any of copper, copper alloy, aluminum, aluminum alloy, silver, or silver alloy is effective.
[0032]
Like the semiconductor device of the present invention, there is an advantage that the reliability can be improved only by arranging the first through via on the wiring, and at the same time, there is no need to change the conventional wiring manufacturing process at all. However, it is extremely effective from the viewpoint of cost.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, this invention is not limited to these.
[0034]
FIG. 3 is a cross-sectional view showing a structure of a copper wiring produced by a single damascene method according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view showing a conventional wiring structure. In the figure, 1 and 6 are wirings, 1a and 6a are copper (Cu) films as the uppermost layer, 1b and 6b are TaN with a thickness of 40 nm as the lowermost layer made of refractory metal or refractory metal nitride. 2 shows an insulating film, 51 and 52 show a second through via, and 53 shows a first through via, respectively.
[0035]
In addition, the same code | symbol is attached | subjected to the component shown in a figure corresponding to FIG. 6 which shows a prior art example.
[0036]
[Example 1]
FIG. 3 is a cross-sectional view illustrating the first embodiment. The copper wiring shown in this figure was produced by a single damascene method. The Cu film as the uppermost layer shown by 1a and 6a was formed by a plating method, and TaN was formed by the sputtering method as the lowermost layer made of a refractory metal or refractory metal nitride as a barrier metal shown by 1b and 6b. .
[0037]
The formed uppermost layer 1a has a width of 0.3 μm and a height of 0.4 μm. The uppermost layer 1a is connected to second through vias 51 and 52 that connect the wirings at both ends, and is connected to the upper wiring 6. Here, the distance between the second through vias 51 and 52 is 100 μm. The second through vias 51 and 52 have a cylindrical shape, a height of 0.4 μm, and a diameter of 0.3 μm. Then, the first through via 53 was arranged at a distance of 5 μm from the second through via 52. The shape of the first through via 53 is the same as that of the second through via 51 or 52. Here, a single damascene method is used, and the first through via 53 is not connected to an upper layer wiring or a lower layer wiring.
[0038]
The second through vias 51 and 52 and the first through via 53 are formed by embedding a Cu conductor layer using TaN as a barrier metal, similarly to the wirings 1 and 6. The lead-out wiring 6 is also formed by the same process as the wiring 1, and the wiring width is 5 μm.
[0039]
The reliability of the wiring 1 was examined, and a life test was performed in order to compare with the conventional wiring. The conventional wiring structure used is shown in FIG. 6, and a wiring structure having a wiring width of 0.3 μm is used here. Compared with FIG. 3, the first through via 53 is not provided, and all other structures are the same as FIG.
[0040]
The temperature of the life test was 250 ° C., and the acceleration current was continuously applied at 3.6 mA. At this time, current flowed from the second through via 51 toward the through via 52. The value of the acceleration current corresponds to a current density of 3 × 10 ⁶ A / cm ² in the wiring 1 to be tested. FIG. 7 shows the change in wiring resistance with respect to the elapsed time during the life test. From this result, when the life at 110 ° C. and 1 × 10 ⁶ A / cm ² is estimated as the actual use condition using the Black equation generally used for life estimation, the conventional example is 9 years. The invention has been found to extend to 16.5 years. That is, it can be seen that the life of the wiring structure according to the present invention is about 1.8 times longer than that of the conventional wiring structure because it is difficult to expand even if voids are formed.
[0041]
[Example 2]
In this embodiment, an example in which a copper wiring is manufactured using a dual damascene method is shown. FIG. 4 shows the wiring structure used. The lowermost layers 1b and 6b made of a refractory metal or a refractory metal nitride use TaN having a thickness of 40 nm as in the first embodiment, and the Cu uppermost layers 1a and 6a are embedded therein by a plating method. The wiring height is also 0.4 μm, but the wiring width is 0.9 μm and 8 μm for 1a and 6a, respectively.
[0042]
Second through vias 54 and 55 are provided at both ends of the wiring 1, and are connected to the upper wiring 6 through the second through vias 54 and 55. Each of the second through vias 54 and 55 has a cylindrical shape with a diameter of 0.3 μm, and has a structure in which two are spaced apart by 0.6 μm in a direction perpendicular to the longitudinal direction of the wiring.
[0043]
The length of the wiring 1 used in this test is 100 μm, but the first through via is arranged as a first through through via group 56 having a reduced diameter at a distance of 10 μm from the second through via 55. As shown in FIG. 4, five first through via groups 56 are arranged at a pitch of 0.6 μm. The first through via group 56 is connected to an upper wiring 61 having a length of 1.5 μm and a width of 1.2 μm. However, the wiring 61 is not electrically connected to other wirings and is independent. ing.
[0044]
In order to examine the effect of the number of first through via groups 56 in which the diameters of the first through vias were reduced, a life test was performed on only two wires arranged in the wiring width direction as shown in FIG. The wiring structure and configuration other than the number of through vias of the first through via group 56 are the same as those in FIG.
[0045]
A life test similar to that in Example 1 was performed using this structure. The test condition was 250 ° C., and a current of 12 mA was continuously applied from the second through via 54 toward the through via 55. This current corresponds to a current density of 3.3 × 10 ⁶ A / cm ² in the wiring 1. Further, as in Example 1, a conventional wiring without the first through via group 56 was also produced and compared. FIG. 8 shows the change in wiring resistance with respect to the elapsed time during the life test of Example 2.
[0046]
When this result is used to estimate the life under actual use conditions using the Black equation in the same manner as in Example 1, this corresponds to an increase in the average life from 81 years to 97 years. That is, it has been found that the time until the wiring resistance starts to increase is about 20% longer than the conventional one. The average life of the first through via group 56 with two through vias corresponds to an extension of about 8%.
[0047]
Compared with the first embodiment, the lifetime is less likely to be extended, but it can be easily considered that the lifetime is further extended by changing the arrangement of the first through via group.
[0048]
【The invention's effect】
As described above, according to the present invention, by providing the first through via connected to the upper part of the wiring, it is possible to prevent the expansion of voids caused by electromigration. As a result, it is possible to extend the time until the wiring breaks and the resistance value increases, which greatly contributes to improving the reliability of the semiconductor device.
[0049]
In addition, the present invention does not require any changes to the integrated circuit manufacturing process, and can be achieved by changing the layout that is not related to the operation of the circuit, thus contributing to the improvement of reliability and cost reduction. There is a lot to do.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing the effect of the present invention (part 1).
FIG. 2 is a sectional view showing the effect of the present invention (part 2).
3 is a cross-sectional view illustrating Example 1. FIG.
4 is a cross-sectional view illustrating a second embodiment (No. 1). FIG.
FIG. 5 is a cross-sectional view illustrating a second embodiment (No. 2).
FIG. 6 is a cross-sectional view showing a conventional wiring structure.
7 is a graph showing a change in wiring resistance during a life test in Example 1. FIG.
8 is a graph showing a change in wiring resistance during a life test in Example 2. FIG.
FIG. 9 is a schematic cross-sectional view showing in-situ observation with a TEM.
[Explanation of symbols]
1, 6 and 61 Wirings 1a and 6a Top layers 1b and 6b made of copper, copper alloy, aluminum, aluminum alloy, silver or silver alloy Bottom layer 2 made of refractory metal or refractory metal nitride 2 Insulating film 2a SiO ₂ film 2 b SiN film 3 Silicon substrate 4 Void 5 Through vias 51, 52, 54, 55 Second through via 53 for connecting wirings First through via 56 First through via group

Claims (3)

A wiring and a first through via connected to the wiring and electrically independent from the other wiring;
The wiring is a multilayer film having an upper surface covered with an insulating film and having a top layer made of copper or a copper alloy and a bottom layer made of a refractory metal or a refractory metal nitride covering the side and bottom surfaces of the top layer. Consists of
The first through via is embedded in the same layer configuration as the multilayer film, is in close contact with the uppermost layer exposed on the bottom surface of the opening formed in the insulating film, and is on the cathode side of the uppermost layer A semiconductor device characterized in that the semiconductor device is arranged only in the semiconductor device.   The semiconductor device according to claim 1, wherein a width of the opening exceeds a width of the wiring, and the first through via bulges in a width direction of the wiring. A wiring and a first through via connected to the wiring and electrically independent from the other wiring;
The wiring is a multilayer film having an upper surface covered with an insulating film and having a top layer made of copper or a copper alloy and a bottom layer made of a refractory metal or a refractory metal nitride covering the side and bottom surfaces of the top layer. Consists of
The first through via is embedded in the same layer structure as the multilayer film, and has a contact surface with the uppermost layer exposed on the bottom surface of the opening formed in the insulating film. 2. A semiconductor device, wherein at least two surfaces are arranged side by side in the width direction of the wiring .

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