KR20010045578A - Metal interconnection line structure in semiconductor device - Google Patents

Metal interconnection line structure in semiconductor device Download PDF

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Publication number
KR20010045578A
KR20010045578A KR1019990048909A KR19990048909A KR20010045578A KR 20010045578 A KR20010045578 A KR 20010045578A KR 1019990048909 A KR1019990048909 A KR 1019990048909A KR 19990048909 A KR19990048909 A KR 19990048909A KR 20010045578 A KR20010045578 A KR 20010045578A
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South Korea
Prior art keywords
metal wiring
film
metal interconnection
semiconductor device
semiconductor substrate
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KR1019990048909A
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Korean (ko)
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이성권
마숙락
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990048909A priority Critical patent/KR20010045578A/en
Publication of KR20010045578A publication Critical patent/KR20010045578A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A metal interconnection structure of a semiconductor device is provided to prevent a shift of the metal interconnection even if a heat treatment process is performed after the metal interconnection is formed on an interlayer planarization layer having high temperature fluidity. CONSTITUTION: A circuit device is formed in a semiconductor substrate(20). A high temperature fluid insulating layer planarizes the surface of the substrate, formed on the semiconductor substrate. A conductive interconnection is formed on the high temperature fluid insulating layer. At least one dummy pattern(dc) not electrically connected to the circuit device is formed in a lower portion of a metal interconnection(22).

Description

반도체 소자의 금속 배선 구조{Metal interconnection line structure in semiconductor device}Metal interconnection structure of semiconductor device

본 발명은 반도체 소자의 금속 배선 구조에 관한 것으로, 보다 구체적으로는 고온 유동성 절연막 상부에 형성되는 금속 배선 구조에 관한 것이다.The present invention relates to a metal wiring structure of a semiconductor device, and more particularly to a metal wiring structure formed on the high-temperature fluid insulating film.

일반적으로, 반도체 기판상에 모스 트랜지스터와 회로 소자가 형성되면, 반도체 기판 표면에는 모스 트랜지스터의 높이로 인한 토폴로지가 발생된다. 특히, 반도체 소자의 집적도가 증가될수록, 이러한 토폴로지 문제는 더욱 심각하다. 이와같이 토폴로지가 발생되면, 후속으로 공정을 진행하는데 있어, 오정렬 및 패턴 불량이 발생되므로, 평탄화 공정을 실시하여 줌이 필수적이다.In general, when a MOS transistor and a circuit element are formed on a semiconductor substrate, a topology due to the height of the MOS transistor is generated on the surface of the semiconductor substrate. In particular, as the degree of integration of semiconductor devices increases, this topology problem becomes more serious. In this way, when the topology is generated, misalignment and pattern defects are generated in the subsequent process, and it is essential to carry out the planarization process.

종래의 평탄화 방법으로는 고온에서 유동성을 갖는 절연막을 증착하는 방법과, 표면이 평탄해지도록 표면을 연마하는 공정등이 있다.Conventional planarization methods include a method of depositing an insulating film having fluidity at a high temperature, and a step of polishing the surface to make the surface flat.

그중, 고온에서 유동성을 갖는 절연막을 증착하는 방법은, 회로 소자가 형성된 반도체 기판 상부에 예를들어, BPSG막을 증착한다. 그 다음, BPSG막을 약 800℃ 이상의 온도로 열처리하여 플로우시켜서 기판 표면을 평탄화시킨다. 그리고나서, 금속막등을 증착한후 소정 부분 패터닝하여 금속 배선을 형성한다.Among them, in the method of depositing an insulating film having fluidity at high temperature, for example, a BPSG film is deposited on the semiconductor substrate on which a circuit element is formed. Then, the BPSG film is heat treated by heat treatment at a temperature of about 800 ° C. or higher to planarize the substrate surface. Then, after depositing a metal film or the like, a predetermined portion is patterned to form a metal wiring.

이와같이, BPSG막을 이용하여 반도체 기판 표면을 평탄화시키고, 금속 배선을 형성한다음, 후속 공정으로 열처리 공정이 실시될 수 있다. 그러나, 상기의 열처리 공정으로 유동성을 지닌 BPSG막이 일부 재플로우 될 수 있다. 이에따라, 이미 형성된 배선들이 BPSG막의 재플로우에 의하여 위치 이동을 하게 된다.As described above, the surface of the semiconductor substrate is planarized using the BPSG film, the metal wirings are formed, and then a heat treatment process may be performed in a subsequent process. However, the BPSG film having fluidity may be partially reflowed by the above heat treatment process. Accordingly, the already formed wirings are moved in position by reflow of the BPSG film.

즉, 도 1에 도시된 바와 같이, 하부층과 콘택되어진 콘택부(C)는 하부와 연결되어 있으므로, BPSG막(11)이 재플로우 될지라도, 일정한 간격, 예를들어 5㎝ 간격으로 유지하며 위치한다.That is, as shown in FIG. 1, since the contact portion C contacted with the lower layer is connected to the lower portion, even if the BPSG film 11 is reflowed, the contact portion C is maintained at a constant interval, for example, 5 cm interval. do.

하지만, 지지 부재가 없는 금속 배선(L)들은 열처리 공정시 BPSG막의 재플로우로 인하여 소정 거리만큼 쉬프트된다. 이때, BPSG막은 웨이퍼 외곽쪽으로 흐르게 되어, 배선(L)들 역시 웨이퍼 외곽으로 갈수록 점점 간격이 벌어지게 된다. 즉, 도 1에서와 같이 웨이퍼 외곽으로 갈수록 동일 역할을 하는 배선 간격이 4.9㎝, 4.92㎝, 5㎝, 5.1㎝ 등으로 점차 증가된다.However, the metal lines L without the supporting member are shifted by a predetermined distance due to the reflow of the BPSG film during the heat treatment process. At this time, the BPSG film flows toward the outer edge of the wafer, and thus the wirings L also become more and more spaced toward the outer edge of the wafer. That is, as shown in FIG. 1, wiring intervals that play the same role gradually increase to 4.9 cm, 4.92 cm, 5 cm, 5.1 cm, and the like toward the outside of the wafer.

이와같이, 배선간의 간격이 웨이퍼 외곽으로 갈수록 증대되면, 열처리 공정전에는 도 2a와 같이, 콘택부(C)와 금속 배선(L)간에 소정 간격이 존재하도록 설계되었다.As described above, when the spacing between wirings increases toward the outer edge of the wafer, it is designed such that a predetermined spacing exists between the contact portion C and the metal wiring L as shown in FIG. 2A before the heat treatment process.

하지만, 열처리 공정이 진행되면, BPSG막(11)의 재플로우됨에 의하여, 금속 배선(L)이 쉬프트됨에 따라, 도 2b에서와 같이 금속 배선(L)과 콘택부(C)가 쇼트되어진다. 여기서, 미설명 도면 부호 10은 반도체 기판을 나타내고, LL은 하부 금속 배선을 나타내며, 13은 상부 층간 절연막을 나타낸다.However, when the heat treatment process is performed, as the metal wiring L is shifted by the reflow of the BPSG film 11, the metal wiring L and the contact portion C are shorted as shown in FIG. 2B. Here, reference numeral 10 denotes a semiconductor substrate, LL denotes a lower metal wiring, and 13 denotes an upper interlayer insulating film.

따라서, 본 발명의 목적은 고온 유동성을 갖는 층간 평탄화막상에 금속 배선을 형성한후, 다시 열처리 공정이 진행되어도 금속 배선의 쉬프트를 방지할 수 있는 반도체 소자의 금속 배선 구조를 제공하는 것이다.Accordingly, an object of the present invention is to provide a metal wiring structure of a semiconductor device which can prevent the shift of the metal wiring even after the heat treatment step is performed after forming the metal wiring on the interlayer planarization film having high temperature fluidity.

도 1은 종래의 반도체 소자의 금속 배선 구조를 나타낸 평면도.1 is a plan view showing a metal wiring structure of a conventional semiconductor device.

도 2a는 열처리 공정전 반도체 소자의 금속 배선 구조 단면도.2A is a cross-sectional view of a metal wiring structure of a semiconductor device before heat treatment.

도 2b는 열처리 공정후 반도체 소자의 금속 배선 구조 단면도.2B is a cross-sectional view of a metal wiring structure of a semiconductor device after a heat treatment step.

도 3은 본 발명에 따른 반도체 소자의 금속 배선 구조를 나타낸 평면도.3 is a plan view showing a metal wiring structure of a semiconductor device according to the present invention.

도 4는 도 3을 Ⅳ-Ⅳ'선으로 절단하여 나타낸 단면도.FIG. 4 is a cross-sectional view of FIG. 3 taken along the line IV-IV '.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

20 - 반도체 기판 21 - BPSG막20-semiconductor substrate 21-BPSG film

22 - 금속 배선 23 - 상부 층간 절연막22-metal wiring 23-upper interlayer insulating film

24 - 콘택부 dc - 더미 패턴24-contact dc-dummy pattern

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 회로 소자가 형성된 반도체 기판; 상기 반도체 기판 상부에 형성되며, 기판 표면을 평탄화시키는 고온 유동성 절연막; 및 상기 절연막 상부에 형성되는 도전 배선을 포함하며, 상기 ㄷ도전 배선의 저부에는 상기 회로 소자와 전기적으로 연결되지 않는 적어도 하나 이상의 더미 패턴이 형성되는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention is a semiconductor substrate formed circuit circuit; A high temperature fluid insulating layer formed on the semiconductor substrate and planarizing the surface of the substrate; And conductive wires formed on the insulating film, and at least one dummy pattern is formed on the bottom of the c-conductive wire, which is not electrically connected to the circuit element.

상기한 본 발명에 의하면, BPSG막 상부에 금속 배선의 형성시, 하부 배선들과 전기적 문제를 주지않는 범위에서 상부 금속 배선에 다수개의 더미 패턴을 형성한다.According to the present invention described above, when the metal wiring is formed on the BPSG film, a plurality of dummy patterns are formed on the upper metal wiring in a range that does not cause an electrical problem with the lower wirings.

이에따라, 더미 패턴들이 상부 금속 배선을 지지해주게 되어, 후속 공정으로 열처리 공정이 진행되어도, 금속 배선이 쉬프트되지 않는다.Accordingly, the dummy patterns support the upper metal lines, so that the metal lines are not shifted even when the heat treatment process is performed in a subsequent process.

따라서, 금속 배선의 쉬프트로 인하여, 금속 배선과 콘택부가 쇼트되는 문제를 해결할 수 있다.Therefore, the problem that the metal wiring and the contact portion are shorted due to the shift of the metal wiring can be solved.

(실시예)(Example)

이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 3은 본 발명에 따른 반도체 소자의 금속 배선 구조를 설명하기 위한 평면도이고, 도 4는 도 3을 Ⅳ-Ⅳ'선으로 절단하여 나타낸 단면도이다.3 is a plan view illustrating a metal wiring structure of the semiconductor device according to the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3.

도 3 및 도 4를 참조하여, 회로 소자(도시되지 않음)이 형성된 반도체 기판(20) 상부에 BPSG막(21)이 증착되고, 소정온도에서 열처리되어, 회로 소자가 형성된 반도체 기판(20) 표면이 평탄해진다. 이때, BPSG막 대신 PSG막, BSG막이 사용될 수 있다.3 and 4, a BPSG film 21 is deposited on a semiconductor substrate 20 on which a circuit element (not shown) is formed and heat-treated at a predetermined temperature, thereby forming a surface of the semiconductor substrate 20 on which the circuit element is formed. Is flattened. In this case, a PSG film or a BSG film may be used instead of the BPSG film.

그 다음, 금속 배선(22)이 일정한 규칙을 가지고 배열된다. 이때, 금속 배선(22)에는 후속의 열공정시 BPSG막이 재플로우되더라도 쉬프트되지 않도록 더미 패턴(dc)이 형성되어 있다. 여기서, 더미 패턴은 다음과 같이 형성된다. 기판 표면을 평탄화시키고 금속 배선(22) 형성전, 하부의 회로 소자와 전기적으로 문제를 일으키지 않게 하기 위하여, 예를들어 절연막등이 노출되도록, BPSG막(21)을 식각하여 적어도 하나 이상의 더미 콘택홀을 형성한다. 그후에 더미 콘택홀내에 금속 배선(22)을 형성한다. 이에따라, 금속 배선(22)은 하부의 지지부재를 갖게된다.Then, the metal wirings 22 are arranged with a certain rule. At this time, a dummy pattern dc is formed in the metal wiring 22 so as not to be shifted even when the BPSG film is reflowed during a subsequent thermal process. Here, the dummy pattern is formed as follows. At least one dummy contact hole may be etched by etching the BPSG film 21 so as to expose an insulating film or the like so as to planarize the surface of the substrate and prevent electrical problems with the lower circuit elements before forming the metal wiring 22. To form. Thereafter, the metal wiring 22 is formed in the dummy contact hole. Accordingly, the metal wire 22 has a lower support member.

그리고나서, 다시 상부 층간절연막(24)을 증착하고, 상부 층간 절연막과 BPSG막(21)을 관통하는 콘택부(24)를 형성한다.Then, the upper interlayer insulating film 24 is deposited again, and the contact portion 24 penetrating the upper interlayer insulating film and the BPSG film 21 is formed.

다음, 후속 공정을 진행한다. 이때, 후속 공정으로 열처리 공정이 진행될 수 있는데, 이와같은 열처리 공정이 진행되어, BPSG막(21)이 재플로우되어도, 금속 배선(22)은 더미 패턴에 의하여 지지되므로, 쉬프트되지 않는다.Next, proceed to the subsequent process. At this time, the heat treatment process may be performed in a subsequent process. Even if the heat treatment process is performed such that the BPSG film 21 is reflowed, the metal wires 22 are supported by the dummy pattern and thus are not shifted.

이에따라, 웨이퍼 외곽 부분에서 금속 배선(22)과 콘택부(24)의 쇼트가 방지된다.As a result, the short circuit between the metal wiring 22 and the contact portion 24 is prevented at the wafer outer portion.

이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, BPSG막 상부에 금속 배선의 형성시, 하부 배선들과 전기적 문제를 주지않는 범위에서 상부 금속 배선에 다수개의 더미 패턴을 형성한다.As described in detail above, according to the present invention, when the metal wiring is formed on the BPSG film, a plurality of dummy patterns are formed on the upper metal wiring in a range that does not cause an electrical problem with the lower wirings.

이에따라, 더미 패턴들이 상부 금속 배선을 지지해주게 되어, 후속 공정으로 열처리 공정이 진행되어도, 금속 배선이 쉬프트되지 않는다.Accordingly, the dummy patterns support the upper metal lines, so that the metal lines are not shifted even when the heat treatment process is performed in a subsequent process.

따라서, 금속 배선의 쉬프트로 인하여, 금속 배선과 콘택부가 쇼트되는 문제를 해결할 수 있다.Therefore, the problem that the metal wiring and the contact portion are shorted due to the shift of the metal wiring can be solved.

본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 이 기술에 속하는 당업자에게 자명할 뿐만 아니라 용이하게 발명해낼 수 있다. 따라서 여기에 첨부된 청구범위는 앞서 설명된 것에 한정하지 않고, 상기 의 청구범위는 이 발명에 내제되어 있는 특허성 있는 신규한 모든 것을 포함하며, 아울러 이 발명이 속하는 기술분야에서 통상의 지식을 가진자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments are obvious to those skilled in the art without departing from the spirit and spirit of the invention and can be easily invented. Thus, the claims appended hereto are not limited to those described above, and the claims above include all patented novelties that are inherent in this invention, and furthermore, those of ordinary skill in the art to which this invention pertains. It includes all features processed evenly by the ruler.

Claims (2)

회로 소자가 형성된 반도체 기판;A semiconductor substrate on which circuit elements are formed; 상기 반도체 기판 상부에 형성되며, 기판 표면을 평탄화시키는 고온 유동성 절연막; 및A high temperature fluid insulating layer formed on the semiconductor substrate and planarizing the surface of the substrate; And 상기 고온 유동성 절연막 상부에 형성되는 도전 배선을 포함하며,Conductive wiring formed on the high-temperature fluid insulating film, 상기 금속 배선의 저부에는 상기 회로 소자와 전기적으로 연결되지 않는 적어도 하나 이상의 더미 패턴이 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 구조.At least one dummy pattern which is not electrically connected to the circuit element is formed at a bottom of the metal line. 제 1 항에 있어서, 상기 고온 유동성 절연막은 BPSG막, PSG막, BSG막 중 선택되는 하나의 막인 것을 특징으로 하는 반도체 소자의 금속 배선 구조.The metal wiring structure of a semiconductor device according to claim 1, wherein the high temperature fluid insulating film is one film selected from a BPSG film, a PSG film, and a BSG film.
KR1019990048909A 1999-11-05 1999-11-05 Metal interconnection line structure in semiconductor device KR20010045578A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100900242B1 (en) * 2002-11-14 2009-05-29 매그나칩 반도체 유한회사 Structure of metal line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100900242B1 (en) * 2002-11-14 2009-05-29 매그나칩 반도체 유한회사 Structure of metal line

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