KR20020034221A - Circuit of generation gamma voltage for tft lcd - Google Patents
Circuit of generation gamma voltage for tft lcd Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
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- G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
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Abstract
Description
본 발명은 박막 트랜지스터 액정 표시소자(TFT LCD)의 감마전압 발생 회로에 관한 것으로, 특히 로드(load) 신호가 엑티브(active)한 구간에서만 감마 저항에 전류를 공급하여 감마 전압을 출력하도록 하므로써, 전류 소비를 줄인 감마전압 발생 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gamma voltage generation circuit of a thin film transistor liquid crystal display device (TFT LCD), and in particular, by supplying a current to the gamma resistor to output a gamma voltage only in a section in which a load signal is active. The present invention relates to a gamma voltage generating circuit with reduced consumption.
일반적으로, 감마 전압은 드라이버 IC에서 디지털을 아날로그로 변환하는 D/A(digital to analog) 변환기의 기준전압으로 사용된다.In general, gamma voltages are used as reference voltages for digital-to-analog (D / A) converters that convert digital to analog in driver ICs.
도 1은 종래의 감마전압 발생 회로를 나타낸 것으로, 전원전압(Vcc)과 접지전압(Vss) 사이에 다수개로 직렬접속된 감마 저항(RN+1)과, 상기 감마 저항과 감마 저항 사이의 단자 전압과 출력단의 감마 전압을 차동 증폭하여 감마 전압(VN)으로 출력하는 버퍼 회로부(BRN)로 구성되어 있다.1 illustrates a conventional gamma voltage generation circuit, and a plurality of gamma resistors R N + 1 connected in series between a power supply voltage Vcc and a ground voltage Vss, and a terminal between the gamma resistors and the gamma resistors. It consists of a buffer circuit section BR N which differentially amplifies the voltage and the gamma voltage at the output stage and outputs the gamma voltage V N.
종래의 감마전압 발생 회로는 도시된 바와 같이, 전원전압(Vcc)과 접지전압(Vss) 사이에 직렬접속된 다수개의 감마 저항으로 구성되며, 각각의 저항에서 감마 전압을 추출하여 드라이버 IC에 입력된다. 이때, 출력된 감마 전압은 드라이버 IC내에서 입력된 디지털 데이터를 아날로그로 변환하는데 기준전압으로 사용된다. 상기 감마 전압은 로드(load)가 엑티브한 영역에서만 감마전압으로서의 역할을 하고 나머지 영역에서는 역할을 하지 않는다.The conventional gamma voltage generation circuit is composed of a plurality of gamma resistors connected in series between the power supply voltage (Vcc) and the ground voltage (Vss) as shown, and extracts a gamma voltage from each resistor and inputs it to the driver IC. . At this time, the output gamma voltage is used as a reference voltage to convert the digital data input in the driver IC to analog. The gamma voltage serves as a gamma voltage only in a region in which a load is active and does not play a role in the rest of the region.
도 2는 감마전압이 필요한 기간과 불필요한 기간을 나타내는 입력 신호(데이터 인에이블 신호; DE)와 로드 신호의 동작 파형도이다.2 is an operation waveform diagram of an input signal (data enable signal DE) and a load signal indicating a period during which a gamma voltage is required and an unnecessary period.
현재 대부분의 드라이버 IC는 도면에서와 같이, 엑티브 '하이' 타입의 로드 신호를 입력으로 받는다. 데이터 인에이블 구간에 화면에 디스플레이 된 데이터가 라인별로 입력되고 이 데이터를 드라이버 IC에서 입력받아 D/A 변환을 한 후 전체 화면에 디스플레이하게 된다. 이때, 입력 데이터를 내부의 D/A 변환기 블록으로 전송시켜주는 것이 로드 신호이다. 즉, 로드 신호의 라이징(rising) 시점에 맞추어 내부 D/A 변환기로 입력되고 변환된 아날로그 데이터가 로드 신호의 폴링(falling)에 동기되거나 또는 로드 신호가 '하이'로 된 후 어느정도의 시간이 지난 후에 판넬에 인가되게 된다. 그러므로, 감마 전압은 로드 신호가 '하이'인구간에서만 드라이버 IC로 입력되고, 나머지 구간에서는 아무런 역할을 하지 않는다.Currently, most driver ICs receive an active 'high' type load signal as input. In the data enable section, the data displayed on the screen is input line by line, and this data is input from the driver IC to perform D / A conversion and then displayed on the full screen. At this time, the load signal is to transmit the input data to the internal D / A converter block. That is, some time has passed since the analog data input and converted to the internal D / A converter at the time of rising of the load signal is synchronized with the falling of the load signal or the load signal is 'high'. It is then applied to the panel. Therefore, the gamma voltage is input to the driver IC only in the 'high' section of the load signal and plays no role in the rest of the section.
그런데, 상기 구성을 갖는 종래의 감마전압 발생 회로는 도 1에 도시된 바와 같이, 로드 신호의 엑티브 구간('하이')에 상관없이 항상 전원전압(Vcc)에서 접지전압(Vss)으로 전류 통로가 존재하여 불필요한 전력 소모를 야기한다. 이는 전체 TFT LCD 패널의 전력 소모량의 증가를 가져오는 문제점이 있었다.However, in the conventional gamma voltage generation circuit having the above configuration, as shown in FIG. 1, the current path always flows from the power supply voltage Vcc to the ground voltage Vss regardless of the active period ('high') of the load signal. Present, causing unnecessary power consumption. This has a problem of increasing the power consumption of the entire TFT LCD panel.
따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명의 목적은 감마 저항과 접지전압(Vss) 사이에 로드 신호에 의해 스위칭되는 스위칭 소자를 첨가하여 로드 신호가 엑티브되는 구간에서만 감마 저항에 전류를 공급하므로써, 전류 소비를 줄인 감마전압 발생 회로를 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to add a switching element that is switched by a load signal between the gamma resistor and the ground voltage Vss so that the gamma resistor is active only in a section in which the load signal is active. The present invention provides a gamma voltage generating circuit which reduces current consumption by supplying current.
상기 목적을 달성하기 위하여, 본 발명의 감마전압 발생 회로는,In order to achieve the above object, the gamma voltage generation circuit of the present invention,
박막 트랜지스터 액정 표시소자에 있어서,In the thin film transistor liquid crystal display device,
전원전압과 접지전압 사이에 직렬접속된 다수개의 감마 저항과,A plurality of gamma resistors connected in series between the supply voltage and the ground voltage;
상기 감마 저항과 감마 저항 사이의 단자 전압과 출력단에서 피드백된 감마 전압을 차동 증폭하여 감마 전압으로 각각 출력하는 다수개의 버퍼 회로부와,A plurality of buffer circuit units which differentially amplify the terminal voltage between the gamma resistor and the gamma resistor and the gamma voltage fed back from the output terminal and output the gamma voltage respectively;
상기 접지전압 쪽에 접속된 감마 저항과 상기 접지전압을 로드 신호에 의해 스위칭하는 스위칭 소자를 포함하여 구성된 것을 특징으로 한다.And a switching element for switching the gamma resistor connected to the ground voltage side and the ground voltage by a load signal.
본 발명의 감마전압 발생 회로에 있어서, 상기 스위칭 소자는 MOS 트랜지스터인 것을 특징으로 한다.In the gamma voltage generator circuit of the present invention, the switching element is a MOS transistor.
본 발명의 감마전압 발생 회로에 있어서, 상기 MOS 트랜지스터는 NMOS 트랜지스터인 것을 특징으로 한다.In the gamma voltage generator circuit of the present invention, the MOS transistor is an NMOS transistor.
본 발명의 감마전압 발생 회로에 있어서, 상기 스위칭 소자는 바이폴라 트랜지스터인 것을 특징으로 한다.In the gamma voltage generator circuit of the present invention, the switching element is a bipolar transistor.
본 발명의 감마전압 발생 회로에 있어서, 상기 바이폴라 트랜지스터는 NPN형 바이폴라 트랜지스터인 것을 특징으로 한다.In the gamma voltage generator circuit of the present invention, the bipolar transistor is an NPN type bipolar transistor.
본 발명의 감마전압 발생 회로에 있어서, 상기 스위칭 소자는 전달 게이트인 것을 특징으로 한다.In the gamma voltage generator circuit of the present invention, the switching element is a transfer gate.
본 발명의 감마전압 발생 회로에 있어서, 상기 전달 게이트는 NMOS 및 PMOS 트랜지스터로 구성된 것을 특징으로 한다.In the gamma voltage generator circuit of the present invention, the transfer gate is composed of NMOS and PMOS transistors.
도 1은 종래기술에 따른 감마전압 발생 회로도1 is a gamma voltage generation circuit diagram according to the prior art
도 2는 감마전압이 필요한 기간과 불필요한 기간을 나타내는 입력 신호와 로드 신호의 동작 파형도2 is an operation waveform diagram of an input signal and a load signal indicating a period in which a gamma voltage is required and an unnecessary period;
도 3은 본 발명에 의한 감마전압 발생 회로도3 is a gamma voltage generation circuit diagram according to the present invention.
도 4는 본 발명에 의한 다른 감마전압 발생 회로도4 is another gamma voltage generation circuit diagram according to the present invention;
이하, 본 발명의 실시예에 관하여 첨부도면을 참조하면서 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
또, 실시예를 설명하기 위한 모든 도면에서 동일한 기능을 갖는 것은 동일한 부호를 사용하고 그 반복적인 설명은 생략한다.In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.
도 2는 본 발명에 의한 감마전압 발생 회로를 나타낸 것으로, 전원전압(Vcc)과 접지전압(Vss) 사이에 직렬접속된 다수개의 감마 저항(RN+1)과, 상기 감마 저항과 감마 저항 사이의 단자 전압과 출력단의 감마 전압을 차동 증폭하여 감마 전압(VN)으로 각각 출력하는 다수개의 버퍼 회로부(BRN)와, 상기 접지전압(Vss) 쪽에 접속된 감마 저항(R1)과 상기 접지전압(Vss)을 로드 신호에 의해 스위칭하는 NMOS 트랜지스터(N1)로 구성된다.2 illustrates a gamma voltage generation circuit according to the present invention, and includes a plurality of gamma resistors R N + 1 connected in series between a power supply voltage Vcc and a ground voltage Vss, and between the gamma resistors and the gamma resistors. to the differential amplifier a gamma voltage of the terminal voltage and output a plurality of respective output gamma voltages (V N) of the buffer circuit (BR N), and the gamma resistance (R 1) and the ground connection on the side of the ground voltage (Vss) It consists of an NMOS transistor N1 which switches the voltage Vss by a load signal.
본 발명에서는 도시된 바와 같이 접지전압(Vss)과 감마저항 스트링 사이에 NMOS 트랜지스터(N1)를 연결하였다. NMOS 트랜지스터(N1)는 게이트에 '하이' 전압이 인가되면 드레인과 소오스를 연결하여 전류 통로를 만들게 된다. 이 NMOS 트랜지스터(N1)의 게이트에 로드 신호를 연결할 경우에는 로드 신호가 '하이'인 구간에서만 감마 저항에 전류가 흐르게 되고, 로드 신호가 '로우'인 나머지 구간에서는 접지전압(Vss)과 분리된다. 이때, 전원전압(Vcc)은 감마 저항을 통해 버퍼로 사용되는 연산 증폭기(op-amp)의 입력단으로 연결되게 되는데, 연산 증폭기의 특성상 입력전류는 무시할 만큼 작으므로 전류가 흐르지 않는다고 해도 무방하다. 그러므로, 감마 저항 스트링을 통한 전류는 거의 없다.In the present invention, the NMOS transistor N1 is connected between the ground voltage Vss and the gamma resistance string. When a high voltage is applied to the gate, the NMOS transistor N1 connects the drain and the source to form a current path. When the load signal is connected to the gate of the NMOS transistor N1, current flows to the gamma resistor only in a section where the load signal is 'high', and is separated from the ground voltage Vss in the remaining sections where the load signal is 'low'. . At this time, the power supply voltage Vcc is connected to an input terminal of an op amp used as a buffer through a gamma resistor. However, the input current is small enough to be negligible due to the characteristics of the op amp. Therefore, there is little current through the gamma resistance string.
앞에서 언급했던 것처럼, 감마 전압은 로드 신호가 '하이ㅣ인 구간에서만 드라이버 IC에 입력되어 D/A 변환의 기준 전압으로 작용함으로 이 구간에서만 감마전압이 발생하면 된다.As mentioned earlier, the gamma voltage is input to the driver IC only in the section where the load signal is 'high' and serves as a reference voltage for D / A conversion.
이렇게 함으로써 로드 신호가 '로우'인 대부분의 구간에서는 감마 저항으로전류가 흐르지 않게 되어 불필요한 전력 소모를 막을 수 있다.This prevents unnecessary power consumption by preventing current from flowing through the gamma resistor in most sections where the load signal is 'low'.
로드 신호가 '하이'인 구간에서 드레인과 소오스가 연결되면, 이 드레인과 소오스 사이에는 지극히 작은 저항이 존재하므로 전체 감마 저항값에는 영향을 거의 주지 않는다.When the drain and the source are connected in a section where the load signal is 'high', since there is a very small resistance between the drain and the source, the total gamma resistance value is hardly affected.
만약, NMOS 트랜지스터(N1)의 저항이 너무 클 경우에는 도 4와 같이 NMOS 트랜지스터(N2)와 PMOS 트랜지스터(P1)로 구성된 전달 게이트를 사용하면, 로드가 '하이'인 구간에서 저항을 더욱 감소시킬 수 있다.If the resistance of the NMOS transistor N1 is too large, using a transfer gate composed of the NMOS transistor N2 and the PMOS transistor P1 as shown in FIG. 4 may further reduce the resistance in a section where the load is 'high'. Can be.
참고로, PMOS 트랜지스터는 게이트에 전압이 소오스 전압보다 낮은 전압이 걸리게 되면 드레인과 소오스를 연결하게 된다. 도 4에서는 PMOS 트랜지스터(P1)의 소오스가 전원전압(Vcc)에 연결되어 있고 반전된 로드 신호가 게이트로 입력되므로, 로드 신호가 '하이'인 구간에서 드레인과 소오스를 연결시켜주게 된다.For reference, the PMOS transistor connects the drain and the source when the gate voltage is lower than the source voltage. In FIG. 4, since the source of the PMOS transistor P1 is connected to the power supply voltage Vcc and the inverted load signal is input to the gate, the drain and the source are connected in a section where the load signal is 'high'.
본 발명의 상기 전달 게이트(N2, P1) 대신에 NPN 형 바이폴라 트랜지스터를 사용하여 구현할 수도 있다.An NPN type bipolar transistor may be used instead of the transfer gates N2 and P1 of the present invention.
이상에서 설명한 바와 같이, 본 발명에 의한 박막 트랜지스터 액정 표시소자의 감마전압 발생 회로는, 감마 저항과 접지전압(Vss) 사이에 로드 신호에 의해 스위칭되는 스위칭 소자를 첨가하여 로드 신호가 엑티브되는 구간에서만 감마 저항에 전류를 공급하므로써, 전류 소비를 줄일 수 있다. 따라서, 저전력 소모를 필요로 하는 노트북에서 밧데리의 사용시간을 향상시킬 수 있으며, 휴대성을 증가시킴으로써 고품질의 TFT LCD 제품 생산이 가능하다. 그리고, 저항단에서 발생하는 열을 감소시켜 전체적인 제품의 손실을 감소시키고, 전체의 전력 소모를 감소시킬 수 있는 효과가 있다.As described above, the gamma voltage generator circuit of the thin film transistor liquid crystal display device according to the present invention adds only a switching element switched by the load signal between the gamma resistor and the ground voltage Vss so that the load signal is active only. By supplying current to the gamma resistor, current consumption can be reduced. Therefore, it is possible to improve the use time of the battery in the notebook that requires low power consumption, and to increase the portability, it is possible to produce high-quality TFT LCD products. In addition, by reducing the heat generated in the resistance stage to reduce the overall product loss, there is an effect that can reduce the overall power consumption.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.
Claims (7)
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| KR1020000064297A KR20020034221A (en) | 2000-10-31 | 2000-10-31 | Circuit of generation gamma voltage for tft lcd |
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| KR1020000064297A KR20020034221A (en) | 2000-10-31 | 2000-10-31 | Circuit of generation gamma voltage for tft lcd |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9863762B2 (en) | 2015-04-30 | 2018-01-09 | Samsung Display Co., Ltd. | Method of manufacturing liquid crystal display device and inspection device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05188886A (en) * | 1992-01-14 | 1993-07-30 | Sharp Corp | Liquid crystal driving circuit |
| JPH07261710A (en) * | 1994-03-25 | 1995-10-13 | Matsushita Electric Ind Co Ltd | Liquid crystal driving device |
| JPH0984276A (en) * | 1995-09-14 | 1997-03-28 | Sanyo Electric Co Ltd | Charging voltage detector for storage battery |
| JPH1130974A (en) * | 1997-07-11 | 1999-02-02 | Toshiba Corp | Semiconductor for driving control for liquid crystal display device and liquid crystal display device |
| JPH11133378A (en) * | 1997-10-24 | 1999-05-21 | Nec Corp | Liquid crystal display device |
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2000
- 2000-10-31 KR KR1020000064297A patent/KR20020034221A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05188886A (en) * | 1992-01-14 | 1993-07-30 | Sharp Corp | Liquid crystal driving circuit |
| JPH07261710A (en) * | 1994-03-25 | 1995-10-13 | Matsushita Electric Ind Co Ltd | Liquid crystal driving device |
| JPH0984276A (en) * | 1995-09-14 | 1997-03-28 | Sanyo Electric Co Ltd | Charging voltage detector for storage battery |
| JPH1130974A (en) * | 1997-07-11 | 1999-02-02 | Toshiba Corp | Semiconductor for driving control for liquid crystal display device and liquid crystal display device |
| JPH11133378A (en) * | 1997-10-24 | 1999-05-21 | Nec Corp | Liquid crystal display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9863762B2 (en) | 2015-04-30 | 2018-01-09 | Samsung Display Co., Ltd. | Method of manufacturing liquid crystal display device and inspection device |
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