JP4408715B2 - Driving circuit and processing circuit - Google Patents

Description

  The present invention relates to a drive circuit and a processing circuit, and more particularly to a drive circuit and a processing circuit including a plurality of differential class AB amplifier circuits.

  Conventionally, this type of driving circuit or processing circuit includes a plurality of differential class AB amplifier circuits, and has been used to perform parallel driving of a plurality of analog data lines or parallel amplification of a plurality of analog signals with low power consumption. It was. In addition, since the drive circuit and processing circuit of this invention are provided with an equivalent characteristic part, hereafter, the drive circuit of a display apparatus is demonstrated in this specification on behalf of these drive circuits and processing circuits, for example.

  The driving circuit of this conventional display device, for example, drives a capacitive load such as a data line of each column of an LCD panel in parallel and outputs an analog signal of each column according to display data in parallel. A plurality of differential class AB amplifiers capable of inputting and outputting in the entire power supply voltage range and capable of inputting and outputting Rail-To-Rail have been used in voltage follower connection.

  For example, FIG. 5 is a block diagram illustrating a configuration example of a driving circuit of the conventional display device and a display panel.

  The driving circuit of this conventional display device includes a control circuit 4, a gradation power source 5, a scanning line driving circuit 6, and a data line driving circuit 7, and drives the display panel 8.

  Here, the display panel 8 is an active matrix driving type color liquid crystal panel using thin film MOS transistors (TFTs) as switching elements, and includes scanning lines and data lines provided at predetermined intervals in the row direction and the column direction, respectively. Pixels are arranged in a matrix at intersections, and each pixel includes a liquid crystal capacitor, which is equivalently a capacitive load, and a TFT having a gate connected to a scanning line connected in series between a data line and a common electrode line.

  A scanning pulse generated by the scanning line driving circuit 7 based on a horizontal synchronizing signal and a vertical synchronizing signal is applied to the scanning line of each row of the display panel 8, and the data line of each column of the display panel 8 is In a state where the common potential Vcom is applied to the common electrode line, an analog data signal generated for each color by the data line driving circuit 7 based on the digital display data is applied. As a result, color characters, images, and the like are displayed on the display panel 8.

  Next, the data line driving circuit 7 related to the present invention will be mainly described. The data line driving circuit 7 includes a D / A conversion circuit 71 that D / A converts display data of each column by selecting a gradation voltage, and impedance conversion to drive a data line of each column to generate an analog display data signal. The output circuit 72 includes a plurality of differential class AB amplifier circuits 1 that are voltage follower-connected and can input and output Rail-To-Rail, and the plurality of differential class AB amplifier circuits 1. And a common bias circuit 2 for supplying a common bias voltage.

  The output circuit 72 of the conventional data line driving circuit 7 uses a differential class AB amplifier circuit 1 with low power consumption and a combination of the common bias circuit 2 and a plurality of arrangements of the differential class AB amplifier circuit 1. A plurality of data lines can be driven in parallel while suppressing an increase in circuit scale, and the circuit area is reduced and the power consumption is reduced.

  FIG. 6 is a circuit diagram showing a conventional example 1 of the differential class AB amplifier circuit 1 described above. The differential class AB amplifier circuit 1 includes a differential amplifier 17 and a class AB output circuit 18. For example, Rail-To-Rail input is possible as a driver in the class AB output circuit described in FIG. This is obtained by using a general differential amplifier 17 and enables Rail-To-Rail input / output.

  The differential amplifier 17 includes an N receiving differential amplification mirror output unit 171 and a P receiving differential amplification unit 172.

  The N receiving differential amplification mirror output unit 171 includes a pair of N-channel differential MOS transistors 112 and 113 having a normal input terminal Vin (+) and an inverting input terminal Vin (−) connected to the gate, and a pair of these. A pair of P-channel load MOS transistors 114 and 115 connected as loads of N-channel differential MOS transistors 112 and 113, and mirror currents I4 and I5 of the differential current of the pair of P-channel load MOS transistors 114 and 115 A pair of P channel mirror output MOS transistors 117 and 118 and a pair of N channel differential MOS transistors 21 and 22 for adding and outputting to the pair of N channel load MOS transistors 124 and 125 of the P receiving differential amplifier 172 And a constant current source 116 for supplying a constant current I1 to the source.

  The P receiving differential amplification unit 172 includes a pair of P channel differential MOS transistors 122 and 123 having the inverting input terminal Vin (−) and the non-inverting input terminal Vin (+) connected to the gate, and a pair of these. A constant current I2 is applied to the sources of a pair of N-channel load MOS transistors 124 and 125 connected as a current mirror type load of the P-channel differential MOS transistors 122 and 123 and a pair of P-channel differential MOS transistors 122 and 123. A constant current source 126 is provided, and outputs from the drain of the P-channel differential MOS transistor 123 to the gate of the N-channel output stage MOS transistor 132 of the class AB output circuit 18.

  The class AB output circuit 18 includes a pair of P and N channel output stage MOS transistors 131 and 132 connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, and the pair of P and N channel outputs. A pair of constant current sources 137 and 138 connected between the gate and power supply terminals and between the gate and ground terminals of the stage MOS transistors 131 and 132 are connected in parallel between the pair of constant current sources 137 and 138, respectively. A pair of P and N channel shift MOS transistors 135 and 136 which function as a level shifter by connecting their gates to a pair of constant voltage sources 139 and 140, respectively, and a diode connected P and N channel MOS transistor in series from a power supply terminal and a ground terminal A pair of constant voltage sources 139 and 140 that supply a high voltage that is lower by a threshold of two stages.

  When the bias portions of the plurality of differential class AB amplifier circuits 1 of the conventional example are shared, the constant current sources 116, 126, 137 and 138 of the differential class AB amplifier circuit are configured as current mirror circuits, respectively. The common bias circuit 2 separates the constant current MOS transistor and the mirror input MOS transistor that are mirror outputs of the mirror output, and the mirror input MOS transistor supplies a bias voltage to the gate of the constant current MOS transistor of the differential class AB amplifier circuit 1; The constant voltage sources 139 and 140 are provided.

  In this conventional differential class AB amplifier circuit, the two constant current sources 116 and 126 of the differential amplifier 17 are usually constituted by current mirror circuits of N and P channel MOS transistors, respectively. The input voltage range in which the P-channel MOS transistor of the constant current source 126 normally operates is VSS or more and VDD− [Vgs + Vds (sat)] or less. In the input voltage range of VDD− [Vgs + Vds (sat)] or more, the current mirror circuit of the N-channel MOS transistor constituting the constant current source 116 is operating normally, and two sets of P-channel MOSs each constituting the current mirror circuit. Transistors 114, 117 and 115, 118 fold mirror currents I4, I5, which are differential currents based on bias current I1, and supply them to N-channel load MOS transistors 124, 125. Therefore, the differential amplification section operates in the input voltage range from the ground terminal to the power supply terminal, and Rail-to-rail input is possible, and the differential class AB amplifier circuit is capable of Rail-to-rail input / output.

  FIG. 7 is a circuit diagram showing Conventional Example 2 of the above-described differential class AB amplifier circuit (see Patent Document 2). This conventional differential class AB amplifier circuit 1 includes an N receiving differential amplifier 11, a P receiving differential amplifier 12, and a class AB output circuit 13, and is capable of Rail-To-Rail input / output.

  The N receiving differential amplifier 11 includes a pair of N channel differential MOS transistors 112 and 113 in which the inverting input terminal Vin (−) and the normal input terminal Vin (+) are connected to the gate, and the pair of N channel differentials. A pair of current mirror type P-channel load MOS transistors 114 and 115 connected to the dynamic MOS transistors 112 and 113, and a bias voltage BN are inputted to the gates to be sources of the pair of N-channel differential MOS transistors 112 and 113. An N-channel constant current source MOS transistor 111 for supplying a constant current I1 is provided, and output from the drain of the N-channel differential MOS transistor 113 to the gate of the P-channel output stage MOS transistor 131 of the class AB output circuit.

  The P receiving differential amplifier 12 includes a pair of P channel differential MOS transistors 122 and 123 having a inverting input terminal Vin (−) and a normal input terminal Vin (+) connected to the gate, and a difference between the pair of P channel differential MOS transistors 122 and 123. A pair of N-channel load MOS transistors 124 and 125 of a current mirror type connected to the dynamic MOS transistors 122 and 123, and a bias voltage BP are input to the gates and the sources of the pair of P-channel differential MOS transistors 122 and 123 are input. An N-channel constant current source MOS transistor 121 for supplying a constant current I2 is provided, and output from the drain of the P-channel differential MOS transistor 123 to the gate of the N-channel output stage MOS transistor 132 of the class AB output circuit 13.

  The class AB output circuit 13 is connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and is connected to the gates of the output lines of the pair of N and P receiving differential amplifiers 11 and 12, respectively. N-channel output stage MOS transistors 131 and 132 and a pair of P and N channels connected between the output line of the N receiving differential amplifier 11 and the power supply terminal and between the output line of the P receiving differential amplifier 12 and the ground terminal, respectively. A pair of P and N channel constant current MOS transistors 133 and 134 having constant current bias voltages BP and BN input to their gates are connected in parallel between the output lines of a pair of N and P receiving differential amplifiers 11 and 12, respectively. A pair of P and N channel shift MOS transistors 135 and 136 functioning as level shifters are provided.

  The class AB output circuit 13 is connected to the gates of the pair of P and N channel shift MOS transistors 135 and 136 between the power source terminal and between the gate and the ground terminal, respectively, and inputs bias voltages BP and BN to the gate. A pair of P and N channel mirror output MOS transistors 141 and 142 and a pair of P and N channels connected between the gate and power supply terminals and between the gate and ground terminals of P and N channel shift MOS transistors 135 and 136, respectively. It includes a pair of P and N channel mirror output MOS transistors 143 and 144 through which mirror currents I7 and I6 of channel output stage MOS transistors 131 and 132 flow.

  Further, in this conventional class AB output circuit, a pair of mirror capacitors 145 and 146 for phase compensation are additionally connected between the gates of the pair of P and N channel output stage MOS transistors 131 and 132 and the output terminal Vout. Thus, the differential class AB amplifier circuit has good frequency characteristics.

  Note that the common bias circuit 2 for supplying the bias voltages BP and BN to the plurality of differential class AB amplifier circuits of the conventional example includes a P and N channel mirror input MOS transistors of a current mirror circuit.

  In this conventional differential class AB amplifier circuit 1, a pair of N and P channel mirror output MOS transistors 142 and 141 are current mirror controlled by inputting bias voltages BN and BP to their gates, and a pair of P and N Channel mirror output MOS transistors 143 and 144 are current mirror controlled in the same manner as a pair of P and N channel output stage MOS transistors 131 and 132, and their connection points are a pair of P and N channel shift MOS transistors 135 and 136. Connected to the gate. Therefore, the gate voltage of the pair of P and N channel shift MOS transistors 135 and 136 is not a constant voltage unlike the conventional example 1, but dynamically varies depending on the output state of the differential class AB amplifier circuit 1, and the pair of P and N channel shift MOS transistors 135 and 136 Only one of the N-channel output stage MOS transistors 131 and 132 is set in a current mirror operation state, the idling current is controlled to a small value, and the crossover distortion is reduced.

  In the above-described differential class AB amplifier circuit and common bias circuit of FIGS. 6 and 7, although not shown, the constant current source or the constant current MOS transistor and the shift MOS transistor are turned off in the test mode. And a pair of P and N channel test MOS transistors controlled in the test mode and turned on in the test mode are connected between the gate and power supply terminals of the pair of P and N channel output stage MOS transistors of the class AB output circuit and between the gate and the ground. The terminals are additionally connected to each other, and in the test mode, the pair of P and N channel output stage MOS transistors are respectively turned off, and the idling current of these output MOS transistors is made zero. Thereby, in the test mode, all circuit current paths are turned off, and the chip leakage current as the data line driving circuit can be measured.

JP-A-61-35004 (FIG. 1) Japanese Patent Laying-Open No. 2001-177352 (FIG. 4)

  However, the differential class AB amplifier circuit in the conventional drive circuit described above has several problems.

  The problem of the differential class AB amplifier circuit of the conventional example 1 shown in FIG. 6 is that Rail-to-rail input / output is possible, but in the input voltage range of VDD− [Vgs + Vds (sat)] or more, the bias current I1 Since the mirror currents I4 and I5 of the differential current due to the current need to be folded, not only the number of elements is increased by the folding mirror circuit, but also the current consumption increases by the folding mirror currents I4 and I5, and high integration is achieved. This also hinders the reduction of power consumption and power consumption.

  Further, the problem with the differential class AB amplifier circuit of the conventional example 2 shown in FIG. 7 is that when a plurality of differential class AB amplifier circuits are used as output circuits of the data line driving circuit, a pair of P and N Since the gate voltages of the channel shift MOS transistors 135 and 136 vary depending on the output state of the differential class AB amplifier circuit 1, a pair of P and N channel MOS transistors 135 and 136 of the plurality of differential class AB amplifier circuits 1 are used. The gates cannot be connected in common, and four mirror output MOS transistors 141 to 144 constituting a current mirror circuit are required for each differential class AB amplifier circuit, which hinders high integration.

  Since the idling current of the output stage MOS transistor of the differential class AB amplifier circuit is controlled by the current mirror, the current mirror currents I6 and I7 by the four mirror output MOS transistors 141 to 144 shown in FIG. The current consumption increases.

  When these differential class AB amplifier circuit 1 is used as output circuit 72 of data line drive circuit 7, a pair of P and N channel output stage MOSs are used to turn off all circuit current paths in the test mode. A pair of P and N channel test MOS transistors are added between the gate and power supply terminals of the transistor and between the gate and ground terminals, and the gate voltages of the pair of P and N channel output stage MOS transistors are fixed at the power supply level and the ground level. is doing. In the display circuit drive circuit, 300 to 500 differential class AB amplifier circuits 1 are used per chip, and 600 to 1000 P or N channel test MOS transistors are required, which hinders high integration. is there.

  Accordingly, an object of the present invention is to further increase the integration and power consumption of a drive circuit and a processing circuit including a plurality of differential class AB amplifier circuits.

Therefore, the present invention provides a common bias to a plurality of differential class AB amplifier circuits that are voltage follower connected to each other and input a plurality of analog signals in parallel and drive a plurality of data lines in parallel. In a drive circuit comprising a common bias circuit for supplying a voltage,
The differential class AB amplifier circuit is connected to a pair of normal and inverting input terminals, respectively, and a pair of N and P receiving differentials each controlled at a constant current by a pair of N and P channel differential bias voltages. An amplifier;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connected to the gates of the output lines of the pair of N and P receiving differential amplifiers;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which respectively input a pair of P and N channel shift bias voltages to the gates and function as level shifters; With
In the test mode, the common bias circuit switches the pair of N and P channel differential bias voltages to a ground level and a power supply level, respectively, and the pair of P and N channel constant current bias voltages to a ground level and a power supply level. Switching Each of the pair of P and N channel shift bias voltages is switched to a power supply level and a ground level.

The present invention also includes a plurality of differential class AB amplifier circuits that input a plurality of analog signals in parallel and amplify them in parallel, and a common bias circuit that supplies a bias voltage to the plurality of differential class AB amplifier circuits in common. In the processing circuit,
The differential class AB amplifier circuit is connected to a pair of normal and inverting input terminals, respectively, and a pair of N and P receiving differentials each controlled at a constant current by a pair of N and P channel differential bias voltages. An amplifier;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connected to the gates of the output lines of the pair of N and P receiving differential amplifiers;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which respectively input a pair of P and N channel shift bias voltages to the gates and function as level shifters; With
In the test mode, the common bias circuit switches and outputs the pair of N and P channel differential bias voltages to the ground level and the power supply level, respectively, and outputs the pair of P and N channel constant current bias voltages to the ground level and the power supply. The pair of P and N channel shift bias voltages are switched and output to the power supply level and the ground level, respectively.

The common bias circuit includes a constant current source,
A switch that turns off in test mode;
A pair of P and N channel current mirror circuits for outputting a plurality of mirror currents from a plurality of output terminals for each channel corresponding to the circuit current of a series circuit in which the constant current source and the switch are connected in series;
A pair of switches connected to each channel between the input terminal and the power supply terminal and between the input terminal and the ground terminal of the pair of P and N channel current mirror circuits and turned on in the test mode;
A pair of P and N channel MOSs connected to each channel between the one output terminal of the N channel current mirror circuit and the power supply terminal and between the one output terminal of the P channel current mirror circuit and the ground terminal, with the gate and drain connected in common. A transistor,
A pair of switches each turned off in test mode;
One pair of P and N channel MOS transistors and one pair of switches are connected in series to each channel, and one end of each pair is connected to one end of each series circuit to output the pair of P and N channel constant current bias voltages. Each node is provided with a pair of switches that are turned on in the test mode by connecting the other end to a ground terminal and a power supply terminal for each channel.

Further, two P-channel MOS transistors and two N-channel MOS transistors each having a gate and a drain connected in common are connected between one output terminal of the N-channel current mirror circuit and a power supply terminal and one output terminal of the P-channel current mirror circuit. A pair of P and N channel series circuits connected in series by channel between ground terminals;
One end of each pair of P and N channel series circuits is connected to each channel to serve as an output node for the pair of P and N channel shift bias voltages, and the other end is connected to the power supply terminal and the ground terminal for each channel. And a pair of switches that each turn on at times.

In addition, a pair of P and N is connected to each channel between one output end of the N-channel current mirror circuit and the power supply terminal and between one output end of the P-channel current mirror circuit and the ground terminal, and the gate and drain are commonly connected. A channel MOS transistor;
One end of each pair of P and N channel MOS transistors is connected to the drain for each channel to output the pair of P and N channel differential bias voltage, and the other end is connected to the power supply terminal and the ground terminal for each channel. And a pair of switches that are turned on in each mode.

  The input terminals of the pair of P and N channel current mirror circuits may be output nodes of the pair of P and N channel differential bias voltages.

In addition, the differential class AB amplifier circuit of the present invention has a pair of normal and inverted input terminals connected to each other, and a pair of N and P-channel differential bias voltages that are constant current controlled by a pair of N and P channel differential bias voltages, respectively. A P receiving differential amplifier;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and connected to a pair of P and N channel shift bias voltages with their gates functioning as level shifters;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal and respectively connected to the gates of the output lines of the pair of N and P receiving differential amplifiers. I have.

  In the drive circuit and the processing circuit of the present invention, the number of elements and circuit current paths of a plurality of Rail-to-rail input / output differential class AB amplifier circuits that are provided are reduced, the circuit area and power consumption are reduced, and the drive circuit In addition, the processing circuit is highly integrated and has low power consumption.

  That is, in the differential class AB amplifier circuit in the drive circuit of the present invention, for example, the folding mirror circuit required in the differential amplifier section of the differential class AB amplifier circuit of Conventional Example 1 in FIG. In addition, the four mirror output MOS transistors necessary for controlling the gate voltages of the pair of P and N channel shift MOS transistors in the class AB output circuit of the differential class AB amplifier circuit of the conventional example 2 of FIG. This is unnecessary in the present invention, the number of elements of the differential class AB amplifier circuit is reduced, the current paths of the currents I4 to I7 shown in FIGS. 6 and 7 are not provided, the circuit area and power consumption are reduced, and the drive circuit is reduced. High integration and low power consumption are achieved.

  Conventionally, when a differential class AB amplifier circuit is used as an output circuit of a data line driving circuit, a pair of P and N channel output stage MOS transistors are used to turn off all circuit current paths in the test mode. A pair of P and N channel test MOS transistors were added between the gate and power supply terminals and between the gate and ground terminals, and the gate voltages of the pair of P and N channel output stage MOS transistors were fixed at the power supply level and the ground level. However, in the differential class AB amplifier circuit of the present invention, the addition of the conventional pair of P and N channel test MOS transistors becomes unnecessary, the number of elements of the differential class AB amplifier circuit is reduced by two, and the circuit area is reduced. Is done.

  Particularly, in the data line driving circuit of the driving circuit of the display device, 300 to 500 differential class AB amplifier circuits are used per chip, and the circuit area and power consumption of the driving circuit of the display device are significantly reduced. There are effects such as.

  The drive circuit of the present invention further reduces the circuit area and power consumption without impairing the Rail-to-rail input / output characteristics of the differential class AB amplifier circuit, and the drive circuit is highly integrated and has low power consumption.

  Like the output circuit 72 in the data line drive circuit 7 of the drive circuit of the conventional display device shown in FIG. 5, the drive circuit of the present invention includes a plurality of differential class AB amplifier circuits 1 and a common bias circuit 2. The differential class AB amplifier circuit 1 is capable of rail-to-rail input / output, and the differential class AB amplifier circuit 1 and the common bias circuit 2 have different internal configurations. The configurations and operations of the differential class AB amplifier circuit 1 and the common bias circuit 2 will be described in the following embodiment with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration example of a differential class AB amplifier circuit 1 and a common bias circuit 2 in Embodiment 1 of the drive circuit of the present invention. FIG. 1 (A) shows a differential class AB amplifier circuit 1. FIG. 1B shows the common bias circuit 2.

  Referring to FIG. 1A, the differential class AB amplifier circuit 1 in the drive circuit of this embodiment includes an N receiving differential amplifier 11, a P receiving differential amplifier 12, and a class AB output circuit 13.

  The N receiving differential amplifier 11 includes a pair of N channel differential MOS transistors 112 and 113 in which the inverting input terminal Vin (−) and the normal input terminal Vin (+) are connected to the gate, and the pair of N channel differentials. A pair of current mirror type P-channel load MOS transistors 114, 115 connected to the dynamic MOS transistors 112, 113, and a pair of N-channel differential MOS transistors 112, 115 having an N-channel differential bias voltage BN1 input to the gate. An N-channel constant current source MOS transistor 111 that supplies a constant current I1 to the source of 113 is output from the drain of the N-channel differential MOS transistor 113 to the gate of the P-channel output stage MOS transistor 131 of the class AB output circuit.

  The P receiving differential amplifier 12 includes a pair of P channel differential MOS transistors 122 and 123 having a inverting input terminal Vin (−) and a normal input terminal Vin (+) connected to the gate, and a difference between the pair of P channel differential MOS transistors 122 and 123. A pair of current mirror type N-channel load MOS transistors 124, 125 connected to the dynamic MOS transistors 122, 123, and a pair of P-channel differential MOS transistors 122, N-channel constant current source MOS transistor 121 that supplies constant current I2 to the source of 123, and outputs from the drain of P-channel differential MOS transistor 123 to the gate of N-channel output stage MOS transistor 132 of class AB output circuit 13 .

  The class AB output circuit 13 is connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and is connected to the gates of the output lines of the pair of N and P receiving differential amplifiers 11 and 12, respectively. N-channel output stage MOS transistors 131 and 132 and a pair of P and N channels connected between the output line of the N receiving differential amplifier 11 and the power supply terminal and between the output line of the P receiving differential amplifier 12 and the ground terminal, respectively. A pair of P and N channel constant current MOS transistors 133 and 134 having constant current bias voltages BP2 and BN2 input to their gates, respectively, and a pair of N and P receiving differential amplifiers 11 and 12 are connected in parallel. A pair of P and N channel constant current bias voltages BP3 and BN3 are respectively input to the gates, and a pair of P and N channels functioning as level shifters. And a Nerushifuto MOS transistor 135 and 136.

  In the class AB output circuit 13 in this embodiment, a pair of mirror capacitors 145 for phase compensation is provided between the gates of the pair of P and N channel output stage MOS transistors 131 and 132 and the output terminal Vout, as in the conventional case. , 146 are additionally connected, and the differential class AB amplifier circuit 1 has good frequency characteristics.

  Referring to FIG. 1B, the common bias circuit 2 in the drive circuit of the present invention includes a constant current source 21, a switch 22 that is turned off in the test mode, and a series circuit in which the constant current source 21 and the switch 22 are connected in series. A pair of P and N channel current mirror circuits 23 and 24 for outputting a plurality of mirror currents for each channel from a plurality of output terminals, respectively, and a pair of P and N channel current mirror circuits 23, And a pair of switches 25 and 26 that are connected to each other between the input terminal and the power supply terminal and between the input terminal and the ground terminal and are turned on in the test mode.

  The common bias circuit 2 is connected to each channel between one output terminal of the N-channel current mirror circuit 24 and the power supply terminal and between one output terminal of the P-channel current mirror circuit 23 and the ground terminal, and has a gate and a drain connected in common. One pair of P and N channel MOS transistors 27 and 28, and one pair of P and N channel MOS transistors 27 and 28 connected to the drains of the drains of the pair of P and N channel MOS transistors 27 and 28 for each channel A pair of switches 29 and 30 which are connected to the power supply terminal and the ground terminal as the output node of BN1 and connected to the power supply terminal and the ground terminal and are turned on in the test mode, respectively, and a pair of N and P channel differential bias voltages in the test mode BP1 and BN1 are switched and output to the ground level and the power supply level, respectively.

  The common bias circuit 2 is connected to each channel between one output terminal of the N-channel current mirror circuit 24 and the power supply terminal and between one output terminal of the P-channel current mirror circuit 23 and the ground terminal, and has a gate and a drain connected in common. A pair of P and N channel MOS transistors 31 and 32, a pair of switches 33 and 34 which are turned off in the test mode, respectively, and the pair of P and N channel MOS transistors 31 and 32 and the pair of switches 33 and 34 One end of each pair of series circuits connected in series for each channel is connected to one end of each channel to serve as an output node for a pair of P and N channel constant current bias voltages BP2 and BN2, and the other end of each channel is connected to a ground terminal and a power supply terminal. A pair of switches 35 and 36 that are connected and turned on in the test mode, respectively. The mode, each switching output a pair of P and N-channel constant current bias voltage BP2, the BN2 to ground level and the power level.

  Further, the common bias circuit 2 includes two P-channel MOS transistors 37 and 38 and two N-channel MOS transistors 39 and 40 each having a gate and a drain connected in common, between one output terminal of the N-channel current mirror circuit 24 and the power supply terminal. And a pair of P and N channel series circuits connected in series between one output terminal and the ground terminal of the P channel current mirror circuit 23, and one end of each pair of P and N channel series circuits connected to one end of the pair of P and N channel series circuits. And a pair of switches 41 and 42 which serve as output nodes of a pair of P and N channel shift bias voltages BP3 and BN3 and which are connected to the power supply terminal and the ground terminal for each channel and turned on in the test mode, respectively. During mode, a pair of P and N channel shift bias voltages BP3, BN3 Respectively switching outputs to the power supply level and the ground level.

  Each switch in the common bias circuit 2 is composed of a P or N channel MOS transistor.

  Next, the operation of the differential class AB amplifier circuit 1 in the drive circuit of this embodiment will be described. The N receiving differential amplifier 11 in the differential class AB amplifier circuit 1 of the present embodiment is configured such that the constant current source of the differential stage is composed of the N channel constant current MOS transistor 111, and therefore [Vgs1 + Vds1 (sat) from the power supply terminal VDD. )] Can be amplified and transmitted to the class AB output circuit 13. Here, Vds1 (sat) is a source-drain voltage when the N-channel constant current MOS transistor 111 constituting the constant current source operates in the saturation region, and Vgs1 is biased to the N-channel differential MOS transistor 112 or 113. This is the source-gate voltage of the N-channel differential MOS transistor 112 or 113 when the current I2 flows.

  Further, the P receiving differential amplifier 12 amplifies an input signal from VDD− [Vgs2 + Vds2 (sat)] to the ground potential VSS because the constant current source of the differential stage is composed of the P channel constant current MOS transistor 121. And can be transmitted to the class AB output circuit 13. Here, Vds2 (sat) is a source-drain voltage when the P channel constant current MOS transistor 121 constituting the constant current source operates in the saturation region, and Vgs2 is biased to the P channel differential MOS transistor 122 or 123. This is the source-gate voltage of the P-channel differential MOS transistor 122 or 123 when the current I3 flows.

  FIG. 2 is an explanatory diagram for explaining the operation mode of the differential class AB amplifier circuit 1 of the present embodiment, and the input voltages Vin (+) and Vin (−) of the differential class AB amplifier circuit 1. The range is shown in the vertical axis direction.

  The differential class AB amplifier circuit 1 of this embodiment has three operation modes (1) to (3) corresponding to the input voltage ranges of the input signals Vin (+) and Vin (−).

  The operation mode (1) corresponds to an input voltage range in which the input signal Vin (+, Vin (−) is greater than or equal to VDD− [Vgs2 + Vds2 (sat)] and less than or equal to VDD. In this input voltage range, the P receiving differential amplifier 12 Since the P-channel constant current MOS transistor 121 is out of the allowable input voltage range, it cannot operate normally, but at this time, the N-channel constant current MOS transistor 111 of the N receiving differential amplifier 11 is in the allowable input range. Therefore, a signal is transmitted from the N receiving differential amplifier 11 to the class AB output circuit 13, and the differential class AB amplifier circuit operates normally.

  The operation mode (2) corresponds to an input voltage range in which the input signals Vin (+) and Vin (−) are not less than [Vgs1 + Vds1 (sat)] and not more than VDD− [Vgs2 + Vds2 (sat)]. In this input voltage range, N Since both the N and P channel constant current MOS transistors 111 and 121 of the P receiving differential amplifiers 11 and 12 are within the allowable input voltage range, both the N and P receiving differential amplifiers 11 and 12 operate normally. A signal is transmitted from the P receiving differential amplifiers 11 and 12 to the class AB output circuit 13 and operates normally as a differential class AB amplifier circuit.

  The operation mode (3) corresponds to an input voltage range in which the input signals Vin (+) and Vin (−) are not less than the ground voltage VSS and not more than [Vgs1 + Vds1 (sat)], and in this input voltage range, the N receiving differential amplifier 11 Since the N-channel constant current MOS transistor 111 is outside the allowable input voltage range, it cannot operate normally. However, at this time, since the P channel constant current MOS transistor 121 of the P receiving differential amplifier 12 is within the allowable input voltage range, the input signal is transmitted to the class AB output circuit 13 by the differential amplifier 12, and the differential class AB It operates normally as an amplifier circuit.

  As described above, in the differential class AB amplifier circuit in this embodiment, the other differential amplifier operates normally even in a range where either one of the N and P receiving differential amplifiers 11 and 12 does not operate normally. Therefore, as in the prior art, signals can be transmitted to the AB class output circuit 13 in any input voltage range from the power supply terminal VDD to the ground terminal VSS, that is, Rail-to-rail input is possible.

  Further, for example, the folding mirror circuit required in the differential amplifier section of the differential class AB amplifier circuit of the conventional example 1 in FIG. 6 becomes unnecessary, and the class AB amplifier circuit of the differential class AB amplifier circuit of the conventional example 2 in FIG. The four mirror output MOS transistors required for controlling the gate voltages of the pair of P and N channel shift MOS transistors in the output circuit are unnecessary in the present invention, and the number of elements of the differential class AB amplifier circuit is reduced. The current paths of the currents I4 to I7 shown in FIGS. 6 and 7 are not provided, the circuit area and power consumption are reduced, and the drive circuit is highly integrated and has low power consumption.

  Particularly, in the data line driving circuit of the driving circuit of the display device, 300 to 500 differential class AB amplifier circuits are used per chip, and the circuit area and power consumption of the driving circuit of the display device are significantly reduced. .

  Next, the operation of the common bias circuit 2 in the drive circuit of this embodiment will be described. The common bias circuit 2 in the driving circuit of the present embodiment includes a pair of N and P channel differential bias voltages, a pair of P and N channel constant current bias voltages, and a pair of P and N channels in the test mode. Switch control is performed to switch and output the shift bias voltage to the power supply level or the ground level.

  FIG. 3 is an explanatory diagram for explaining the switch control of the common bias circuit 2 in the drive circuit of the present embodiment, and shows the on / off states of the switches in the normal time and the test mode. Note that the on / off state of each switch in the common bias circuit 2 of FIG. 1B indicates the normal on / off state.

  In the common bias circuit 2 of FIG. 1B, in normal times, the three switches 22, 33, 34 are turned on, the other switches are turned off, and the pair of P and N channel current mirror circuits 23, 24 are fixed. A plurality of mirror currents are output from a plurality of output terminals corresponding to the current source 21, respectively.

  A pair of P and N channel MOS transistors 27 and 28, together with a pair of P and N channel constant current MOS transistors 121 and 111 of a pair of P and N receiving differential amplifiers 12 and 11, provide a current mirror circuit for each channel. A pair of P and N channel differential bias voltages BP1 and BN1 which are threshold voltages for one stage of the diode-connected MOS transistor are generated and output to the pair of P and N channel constant current MOS transistors 121 and 111. The pair of P and N channel constant current MOS transistors 121 and 111 pass bias currents I2 and I1.

  A pair of P and N channel MOS transistors 31 and 32 together with a pair of P and N channel constant current MOS transistors 133 and 134 of class AB output circuit 13 constitute a current mirror circuit for each channel, A pair of P and N channel constant current bias voltages BP2 and BN2 which are threshold voltages for one stage are generated and output to a pair of P and N channel constant current MOS transistors 133 and 134. N-channel constant current MOS transistors 133 and 134 pass a bias current I3.

  A pair of two P-channel MOS transistors 37 and 38 and two N-channel MOS transistors 39 and 40 are a pair of P and N-channel shift bias voltages BP3, which are threshold voltages corresponding to two stages of diode-connected MOS transistors in series. BN3 is generated and output to a pair of P and N channel shift MOS transistors 135 and 136 of the class AB output circuit 13, and the pair of P and N channel shift MOS transistors 135 and 136 function as a level shifter.

  In the common bias circuit 2 of FIG. 1B, in the test mode, the three switches 22, 33, and 34 are turned off, and the other switches are turned on. As a result, all circuit current paths of the common bias circuit 2 are cut off, and a pair of N and P channel differential bias voltages BN1 and BP1 are switched and output to the ground level and the power supply level, respectively. N-channel constant current bias voltages BP2 and BN2 are switched and output to the ground level and the power supply level, respectively, and a pair of P and N-channel shift bias voltages BP3 and BN3 are switched and output to the power supply level and the ground level, respectively.

  For this reason, in the differential class AB amplifier circuit 1, the pair of P and N channel constant current MOS transistors 121 and 111 of the pair of P and N receiving differential amplifiers 12 and 11 are turned off, respectively. Also, the pair of P and N channel constant current MOS transistors 133 and 134 of the class AB output circuit 13 are turned on, and the pair of P and N channel shift MOS transistors 135 and 136 of the class AB output circuit 13 are turned off. The gates of the pair of P and N channel output stage MOS transistors 131 and 132 are fixed at the power supply level and the ground level, and the pair of P and N channel output stage MOS transistors 131 and 132 are completely turned off. All the circuit current paths of the class amplifier circuit 1 are turned off.

  For this reason, in the test mode, the circuit current of the drive circuit becomes zero, and the leakage current of the drive circuit can be measured.

  Conventionally, when a differential class AB amplifier circuit is used as an output circuit of a data line driving circuit, a pair of P and N channel output stage MOS transistors 131 and 132 are turned off in order to turn off all circuit current paths in the test mode. A pair of P and N channel test MOS transistors are added between the gate and power supply terminals and between the gate and ground terminals, and the gate voltages of the pair of P and N channel output stage MOS transistors 131 and 132 are set to the power supply level and the ground level. In the differential class AB amplifier circuit of the present invention, the pair of P and N channel shift MOS transistors 135 and 136 are turned off, and the pair of P and N channel constant current MOS transistors 133 and 134 are turned on. The gate voltages of a pair of P and N channel output stage MOS transistors 131 and 132 Power levels and can be fixed to the ground level, additional P and N-channel testing MOS transistor of a conventional pair is not required, the number of elements of the differential class AB amplifier circuit is reduced two, which reduces the circuit area.

  In particular, since the display device drive circuit uses 300 to 500 differential class AB amplifier circuits per chip, the circuit area of the display device drive circuit is significantly reduced, and the display device drive circuit is highly integrated. Is done.

  Note that the common bias circuit in this embodiment shown in FIG. 1B is a control circuit using a large number of switches, and various modifications can be considered.

  For example, FIG. 4 is a circuit diagram showing a modification of the common bias circuit 2 in the drive circuit of the present invention. Compared with the common bias circuit shown in FIG. 1B, the common bias circuit 2 of the present modification has a pair of P and N channel MOS transistors 27 and 28, a pair of switches 29 and 30, and a pair. The two mirror output MOS transistors of the P and N channel current mirror circuits are deleted, and the input terminals of the pair of P and N channel current mirror circuits are connected to the pair of P and N channel differential bias voltages BP1 and BN1. It is an output node.

  The common bias circuit 2 of this modification includes a pair of P and N channel differential bias voltages BP1 and BN1, a pair of P and N channel constant current bias voltages BP2 and BN2, and a pair of P and N channel shift biases. Although it is necessary to design the voltages BP3 and BN3 in order, the circuit area is further reduced as compared with the common bias circuit shown in FIG.

  In the above-described embodiments, the drive circuit including a plurality of differential class AB amplifier circuits and a common bias circuit has been described. However, the present invention is not limited to this description. For example, a plurality of differential class AB amplifier circuits that input and amplify a plurality of analog signals in parallel, and a common supply of a bias voltage to the plurality of differential class AB amplifier circuits. It will be apparent that the processing circuit including the bias circuit can achieve the same effect as the driving circuit.

  In the above-described embodiments, the driving circuit having a plurality of differential class AB amplifier circuits has been described. However, without being limited to this description, it will be apparent that the differential class AB amplifier circuit is controlled by each pair of P and N channel bias voltages and can be used alone in a variety of circuits.

FIG. 3 is a circuit diagram showing a configuration example of a differential class AB amplifier circuit 1 and a common bias circuit 2 in Embodiment 1 of the drive circuit of the present invention. FIG. 2 is an explanatory diagram for explaining an operation mode of the differential class AB amplifier circuit 1 of FIG. FIG. 3 is an explanatory diagram for explaining switch control of the common bias circuit 2 of FIG. FIG. 6 is a circuit diagram illustrating a modification of the common bias circuit 2 of FIG. It is a block diagram which shows the structural example of the drive circuit of the conventional display apparatus, and a display panel. FIG. 6 is a circuit diagram showing a conventional example 1 of a differential class AB amplifier circuit 1; It is a circuit diagram which shows the prior art example 2 of the differential class AB amplifier circuit 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Differential class AB amplifier circuit 2 Common bias circuit 4 Control circuit 5 Gradation power supply 6 Scan line drive circuit 7 Data line drive circuit 8 Display panel 11 N receiving differential amplifier 12 P receiving differential amplifier 13 AB class output circuit 17 Difference Dynamic amplifier 21, 116, 126, 137 to 138 Constant current source 22, 25 to 26, 29 to 30, 33 to 36, 41 to 42 Switch 23 P channel current mirror circuit 24 N channel current mirror circuit 27 to 28, 31 to 32, 37 to 40, 111 to 136, 141 to 144 MOS transistor 71 D / A conversion circuit 72 Output circuit 139 to 140 Constant voltage source 145 to 146 Miller capacitance 171 N receiving differential amplification mirror output unit 172 P receiving differential amplification Part

Claims (10)

A plurality of differential class AB amplifier circuits that are each connected to a voltage follower and input a plurality of analog signals in parallel and drive a plurality of data lines in parallel, and a common bias that supplies a common bias voltage to the plurality of differential class AB amplifier circuits In a drive circuit comprising a circuit,
The differential class AB amplifier circuit is connected to a pair of normal and inverting input terminals, respectively, and a pair of N and P receiving differentials each controlled at a constant current by a pair of N and P channel differential bias voltages. An amplifier;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connecting the output lines of the pair of N and P receiving differential amplifiers to the gates; ,
Connected between the output line of the N receiving differential amplifier and the power supply terminal and between the output line of the P receiving differential amplifier and the ground terminal, respectively, and a pair of P and N channel constant current bias voltages are respectively input to the gates. A pair of P and N channel constant current MOS transistors;
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which function as level shifters by inputting a pair of P and N channel shift bias voltages to the gates, respectively. And
The common bias circuit switches and outputs the pair of N and P channel differential bias voltages to a ground level and a power supply level, respectively, and the pair of P and N channel constant current bias voltages to a ground level and a power supply level, respectively. By switching and outputting the pair of P and N channel shift bias voltages to the power supply level and the ground level, a bias voltage for setting the circuit currents of the plurality of differential class AB amplifier circuits to zero is set. A drive circuit comprising a switch group. The common bias circuit includes:
A constant current source;
A pair of P and N channel current mirror circuits for outputting a plurality of mirror currents for each channel from a plurality of output terminals corresponding to the current flowing through the constant current source;
A pair of P and a gate and a drain connected in common between one output terminal of the N-channel current mirror circuit and the power supply terminal and between one output terminal of the P-channel current mirror circuit and the ground terminal, respectively. An N-channel MOS transistor,
A first switch group connected by channel between the input terminal of the pair of P and N channel current mirror circuits and the power supply terminal and between the input terminal and the ground terminal;
For each gate of the P and N-channel constant current MOS transistors of said pair, said pair of P and N-channel MOS transistor gates of, or be connected to one of said power supply terminal and the ground terminal 2. A drive circuit according to claim 1 , further comprising: a second switch group for setting a bias voltage for setting the current of the pair of P and N-channel constant current MOS transistors to zero . The common bias circuit further includes:
A pair of load circuits for generating the shift bias voltage are connected to each channel between one output terminal of the N-channel current mirror circuit and the power supply terminal and between one output terminal of the P-channel current mirror circuit and the ground terminal. Prepared,
By connecting each connection point of one output terminal of the N-channel current mirror circuit and one output terminal of the P-channel current mirror circuit and the pair of load circuits to the power supply terminal and the ground terminal, respectively . 3. A drive circuit according to claim 1, further comprising: a third switch group for setting a bias voltage for setting the current of the pair of P and N channel shift MOS transistors to zero . The common bias circuit further includes:
A pair of N and N-channel current mirror circuits are connected to each other between one output terminal and the power supply terminal and between one output terminal of the P-channel current mirror circuit and the ground terminal, and have a gate and a drain connected in common. A P-channel MOS transistor,
The pair of N and P channel MOS transistors generate the pair of N and P channel differential bias voltages;
Bias voltage that makes the circuit current of the pair of N and P receiving differential amplifiers zero by connecting the gates of the pair of N and P channel MOS transistors to the ground terminal and the power supply terminal, respectively. 4. The drive circuit according to claim 1, further comprising a fourth switch group for setting   In the pair of load circuits, a gate and a drain are commonly connected between the power supply terminal and one output terminal of the N-channel current mirror circuit and between the ground terminal and one output terminal of the P-channel current mirror circuit, respectively. 5. The drive circuit according to claim 3, wherein the two P-channel MOS transistors and the two N-channel MOS transistors are connected in the forward direction. 6. In a processing circuit comprising a plurality of differential class AB amplifier circuits that input a plurality of analog signals in parallel and amplify the analog signals in common, and a common bias circuit that supplies a common bias voltage to the plurality of differential class AB amplifier circuits,
The differential class AB amplifier circuit comprises:
A pair of N and P receiving differential amplifiers, each of which is connected to a pair of normal and inverting input terminals and is controlled in constant current by a pair of N and P channel differential bias voltages;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connecting the output lines of the pair of N and P receiving differential amplifiers to the gates; ,
1 connected between the output line of the N receiving differential amplifier and the power supply terminal and between the output line of the P receiving differential amplifier and the ground terminal , and a pair of P and N channel constant current bias voltages respectively input to the gates A pair of P and N channel constant current MOS transistors;
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which function as level shifters by inputting a pair of P and N channel shift bias voltages to the gates, respectively. And
The common bias circuit, the respectively switched outputs a pair of N and P-channel differential bias voltage to the ground level and the power supply level, respectively the P and N-channel constant current bias voltage of the pair to the ground level and the power level and switching output, by respectively switching outputs P and N-channel shift bias voltage of the pair to the power supply level and the ground level, setting the bias voltage to zero the circuit current of the plurality of differential AB class amplifier circuit A processing circuit having a switch group . The common bias circuit includes:
A constant current source;
A pair of P and N channel current mirror circuits for outputting a plurality of mirror currents for each channel from a plurality of output terminals corresponding to the current flowing through the constant current source;
A pair of P and a gate and a drain connected in common between one output terminal of the N-channel current mirror circuit and the power supply terminal and between one output terminal of the P-channel current mirror circuit and the ground terminal, respectively. An N-channel MOS transistor,
A first switch group connected by channel between the input terminal of the pair of P and N channel current mirror circuits and the power supply terminal and between the input terminal and the ground terminal;
For each gate of the P and N-channel constant current MOS transistors of said pair, said pair of P and N-channel MOS transistor gates of, or be connected to one of said power supply terminal and the ground terminal 7. A processing circuit according to claim 6 , further comprising: a second switch group for setting a bias voltage for setting a current of the pair of P and N channel constant current MOS transistors to zero . The common bias circuit further includes:
A pair of load circuits for generating the shift bias voltage are connected to each channel between one output terminal of the N-channel current mirror circuit and the power supply terminal and between one output terminal of the P-channel current mirror circuit and the ground terminal. Prepared,
By connecting each connection point of one output terminal of the N-channel current mirror circuit and one output terminal of the P-channel current mirror circuit and the pair of load circuits to the power supply terminal and the ground terminal, respectively . 8. A processing circuit according to claim 6, further comprising: a third switch group that sets a bias voltage that sets a current of the pair of P and N channel shift MOS transistors to zero . 9. The common bias circuit further includes:
A pair of N and N-channel current mirror circuits are connected to each other between one output terminal and the power supply terminal and between one output terminal of the P-channel current mirror circuit and the ground terminal, and have a gate and a drain connected in common. A P-channel MOS transistor,
The pair of N and P channel MOS transistors generate the pair of N and P channel differential bias voltages;
Bias voltage that makes the circuit current of the pair of N and P receiving differential amplifiers zero by connecting the gates of the pair of N and P channel MOS transistors to the ground terminal and the power supply terminal, respectively. The processing circuit according to claim 6, further comprising a fourth switch group for setting In the pair of load circuits, a gate and a drain are commonly connected between the power supply terminal and one output terminal of the N-channel current mirror circuit and between the ground terminal and one output terminal of the P-channel current mirror circuit, respectively. 10. The processing circuit according to claim 8, wherein the two P-channel MOS transistors and the two N-channel MOS transistors are connected in the forward direction.

Images