KR20020028117A - Semiconductor device having structure for down stress caused by laser fusing pattern and for preventing damage of neghbouring pattern and method thereof - Google Patents
Semiconductor device having structure for down stress caused by laser fusing pattern and for preventing damage of neghbouring pattern and method thereof Download PDFInfo
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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Abstract
Description
본 발명은 반도체 소자의 레이저 퓨징 패턴 형성 방법에 관한 것으로, 특히 레이저 퓨징에 의해 형성된 패턴과 그 하부의 막에 가해지는 스트레스를 완화하고 인접 패턴의 손상을 방지하는 구조체를 구비하는 반도체 소자 및 그의 제조 방법에관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a laser fusing pattern of a semiconductor device, and more particularly, to a semiconductor device having a structure formed by laser fusing and a structure for relieving stress applied to a film below and preventing damage to adjacent patterns. It's about how.
반도체 소자가 고집적화됨에 반도체 소자의 도전층 사이의 간격이 점점 줄어들고 있다. 그리고 도전층은 레이저를 이용하여 퓨징하고 있다. 그런데, 레이저의 스폿(spot) 크기는 고집적화에 대응하여 축소되지 않고 있다. 즉, 기판 또는 도전층의 좁은 영역에 많은 레이저 에너지가 불균일하게 가해지게 되어 도전층 패턴을 절단할때, 도전성 물질의 파편이 발생되어 기판 또는 인접 도전층에 놓이게 되어 기판 또는 인접 도전층에 손상을 입히게 된다. 또한, 패터닝되는 막의 하부에 위치하는 막에 레이저 퓨징에 의한 물리적 충격이 가해져서 하부막에 스트레스가 가해져 파괴되며, 이로 인해 반도체 소자의 신뢰성이 저하되는 문제가 있다.As semiconductor devices are highly integrated, gaps between conductive layers of semiconductor devices are gradually decreasing. The conductive layer is fused using a laser. By the way, the spot size of the laser is not reduced corresponding to the high integration. That is, a large amount of laser energy is unevenly applied to a narrow area of the substrate or the conductive layer, so that when the conductive layer pattern is cut, fragments of the conductive material are generated and placed on the substrate or the adjacent conductive layer to damage the substrate or the adjacent conductive layer. Coated. In addition, a physical impact caused by laser fusing is applied to a film positioned below the patterned film, and a stress is applied to the lower film, thereby destroying it, thereby deteriorating reliability of the semiconductor device.
한편, 종래의 레이저 리페어 시스템은 빔 위치기(beam positioner)에 응용되는 간섭계에서, HeNe 레이저의 떨림 현상에 의한 레이저 절단 위치가 변동되게 되어, 원하는 패턴을 형성할 수 없게 되고 인접 도전층 또는 그의 하부막을 포함한 기판에 레이저 빔이 가해져서 이들에게 손상을 입히게 된다.On the other hand, in the conventional laser repair system, in the interferometer applied to the beam positioner, the laser cutting position due to the shaking phenomenon of the HeNe laser is changed, so that the desired pattern cannot be formed and the adjacent conductive layer or the lower portion thereof. Laser beams are applied to the substrate, including the film, to damage them.
따라서, 본 발명이 이루고자 하는 기술적 과제는 도전층을 레이저로 이용하여 패턴형성 할 경우 도전층 패턴 뿐만아니라 도전층의 인접 막 또는 하부 막의 손상을 및 스트레스를 억제할 수 있는 구조체를 가지는 반도체 소자 및 그의 제조 방법을 제공하는 것이다.Accordingly, a technical object of the present invention is to provide a semiconductor device having a structure capable of suppressing damage and stress of adjacent layers or lower layers of the conductive layer as well as the conductive layer pattern when the conductive layer is used as a laser to form a pattern. It is to provide a manufacturing method.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 레이저 퓨징 패턴의 스트레스 완화 및 손상 방지 적층물을 구비한 반도체 소자의 제조 공정 단면도들이다.1A through 1D are cross-sectional views illustrating a manufacturing process of a semiconductor device having a stress mitigating and damage preventing laminate of a laser fusing pattern according to an exemplary embodiment of the present invention.
도 2a 내지 도 2d는 본 발명의 다른 실시예에 따른 레이저 퓨징 패턴의 스트레스 완화 및 손상 방지 적층물을 구비한 반도체 소자의 제조 공정 단면도들이다.2A through 2D are cross-sectional views illustrating a manufacturing process of a semiconductor device having a stress mitigating and damage preventing laminate of a laser fusing pattern according to another exemplary embodiment of the present invention.
도 3a는 종래 기술에 따라 레이저 퓨징된 패턴을 보여주는 사진이다.3A is a photograph showing a laser fused pattern according to the prior art.
도 3b는 본 발명에 따른 스트레스 완화 및 방지 적층물을 구비한 레이저 퓨징 패턴을 보여주는 사진이다.3B is a photograph showing a laser fusing pattern with a stress relief and prevention stack in accordance with the present invention.
본 발명이 이루고자 하는 기술적 과제를 달성하기 위한 반도체 소자는, 반도체 기판, 도전층 패턴 및 스트레스완화 및 손상방지막을 포함한 절연막을 구비한다. 도전층 패턴은 반도체 기판 상에 형성되고 레이저 빔을 이용한 퓨징에 의해 형성된다. 절연막은 반도체 기판과 도전층 패턴 사이에 형성되고, 도전성 패턴과 연결되는 도전성 물질로 이루어지는 스트레스 완화 및 손상 방지 구조체를 포함하여, 레이져 퓨징을 이용하여 도전층 패턴을 형성할 때 구조체를 통해 절연막에 가해지는 스트레스를 완화하고 인접 도전층 패턴의 손상을 방지한다.A semiconductor device for achieving the technical problem to be achieved by the present invention comprises a semiconductor substrate, an insulating layer including a conductive layer pattern and a stress relaxation and damage prevention film. The conductive layer pattern is formed on a semiconductor substrate and formed by fusing using a laser beam. The insulating film is formed between the semiconductor substrate and the conductive layer pattern, and includes a stress relaxation and damage prevention structure made of a conductive material connected to the conductive pattern, and is applied to the insulating film through the structure when forming the conductive layer pattern using laser fusing. Losing stress relieves and prevents damage to adjacent conductive layer patterns.
여기서, 충격 완화 및 손상 방지 구조체를 포함한 상기 절연막 하부에 형성된 도전층 또는 절연막을 더 포함할 수 있다. 스트레스 완화 및 손상 방지 구조체의 모양, 크기 또는 위치는 레이저 빔의 세기, 도전성 패턴의 물질, 절연막의 물질 또는 도전성 패턴들 간의 간격에 의해 결정된다.Here, the method may further include a conductive layer or an insulating layer formed below the insulating layer including a shock absorbing and damage preventing structure. The shape, size, or location of the stress relief and damage prevention structure is determined by the intensity of the laser beam, the material of the conductive pattern, the material of the insulating film, or the spacing between the conductive patterns.
본 발명이 이루고자 하는 기술적 과제를 달성하기 위한 반도체 소자를 제조하기 위해서, 반도체 기판을 준비한다. 반도체 기판 상에 절연막을 형성하고, 절연막의 소정 부분을 식각하여 개구부를 형성한다. 도전성 물질로 개구부를 채워 스트레스완화 및 손상방지 구조물을 형성한다. 구조물을 포함한 절연막 상면에 도전층을 형성하고, 도전층을 레이저 빔을 이용하여 퓨징함으로써 구조물과 연결되는 다수의 도전층 패턴을 형성한다. 한편, 기판을 준비하는 단계와 절연막을 형성하는 단계 사이에, 기판 상에 제 2 도전층을 형성하는 단계를 더 포함한다.In order to manufacture a semiconductor device for achieving the technical problem to be achieved by the present invention, a semiconductor substrate is prepared. An insulating film is formed on the semiconductor substrate, and a predetermined portion of the insulating film is etched to form an opening. Filling the opening with a conductive material to form a stress relief and damage prevention structure. A conductive layer is formed on the upper surface of the insulating film including the structure, and a plurality of conductive layer patterns connected to the structure are formed by fusing the conductive layer using a laser beam. Meanwhile, the method may further include forming a second conductive layer on the substrate between preparing the substrate and forming the insulating film.
이하 본 발명의 사상을 이해하기 위해, 도면에 도시된 실시예를 참고로 설명한다.Hereinafter, in order to understand the spirit of the present invention, it will be described with reference to the embodiments shown in the drawings.
도 1a에서 반도체 기판(8) 상에 도전층(10)과 절연막을 순차적으로 형성한다. 절연막 상에는 포토레지스트 마스크 패턴(도시되지 않음)을 형성하고 이를 이용하여 절연막을 식각하여 콘택홀(14) 및 스트레스 완화 및 손상 방지 구조체 형성을 위한 개구부(16a, 16b)를 형성한다. 도 1b에서, 콘택홀(14) 및 개구부(16a, 16b)를 포함하는 절연막(12) 상에 도전층(18)를 형성한다.In FIG. 1A, the conductive layer 10 and the insulating film are sequentially formed on the semiconductor substrate 8. A photoresist mask pattern (not shown) is formed on the insulating layer and the insulating layer is etched using the contact resist 14 to form contact holes 14 and openings 16a and 16b for forming a stress relief and damage prevention structure. In FIG. 1B, the conductive layer 18 is formed on the insulating film 12 including the contact hole 14 and the openings 16a and 16b.
다음, 도시되지 않았으나 도전층(18)은 절연막(18)의 상면이 노출될 때 까지 에치백 또는 기계 및 화학적 연마를 받아 도 1c에 도시된 것과 같이 콘택 플러그(20) 및 스트레스 완화 및 손상 방지 구조체(22a, 22b)를 형성한다. 다음, 결과물 전면에 상부 도전층(24)을 형성한다.Next, although not shown, the conductive layer 18 is subjected to etch back or mechanical and chemical polishing until the top surface of the insulating film 18 is exposed, and the contact plug 20 and the stress relief and damage prevention structure as shown in FIG. 1C. (22a, 22b) are formed. Next, the upper conductive layer 24 is formed on the entire surface of the resultant.
도 1d에서, 상부 도전층(24)의 일부는 레이저 빔에 노출되어 절단(퓨징)됨으로써, 도전층 패턴(24a, 24b, 24c)을 형성한다. 도전층 패턴(24a)은 콘택 플러그(20)를 통해 절연막(12) 하부에 위치하는 도전층(10)에 연결되어 상부 도전층 패턴과 하부 도전층을 연결한다. 반면, 도전층 패턴(24b, 24c)은 스트레스 완화 및 손상 방지 구조체(22a,22b)와 연결되어, 레이저 퓨징 시에 절연막(12)에 가해지는 스트레스를 완화하고, 인접하는 도전층 패턴에 도전성 파편이 튀어 인접 도전층 패턴에 손상을 주는 것을 방지한다.In FIG. 1D, a portion of the upper conductive layer 24 is exposed to the laser beam and cut (fusing) to form the conductive layer patterns 24a, 24b and 24c. The conductive layer pattern 24a is connected to the conductive layer 10 under the insulating layer 12 through the contact plug 20 to connect the upper conductive layer pattern and the lower conductive layer. On the other hand, the conductive layer patterns 24b and 24c are connected to the stress relieving and damage preventing structures 22a and 22b to relieve the stress applied to the insulating film 12 during laser fusing, and to form conductive fragments in adjacent conductive layer patterns. This splashing is prevented from damaging the adjacent conductive layer pattern.
한편, 도 2a 내지 도 2 d에 나타난 스트레스 완화 및 손상 방지 구조체 형성 공정이 도 1a 내지 도 1d와 다른 점은 스트레스 완화 및 손상 방지 구조체를 형성하기 위한 개구부(56a 56b)가 하부 도전층(50)을 노출시키지 않는다는 점이다. 그러나, 개구부(56a, 56b)는 도 2b 및 도 2c에 도시된 것과 같이 도전성 물질(58)로 채워져 스트레스 완화 및 손상 방지 구조체(62a, 62b)를 형성한다. 이런구조체(62a, 62b)는 이들과 접촉하는 상부 금속층 패턴(64b, 64c)의 레이저 퓨징 시 절연막(52)에 가해지는 스트레스를 완화하고 더불어 인접 금속층 패턴의 손상을 방지한다. 도 2a 내지 도 2d에서 설명하지 않은 참조 번호 48은 반도체 기판, 50은 도전층, 64는 상부 금속층을 나타내고, 54는 콘택홀, 60은 콘택 플러그를 나타낸다.Meanwhile, the process of forming the stress relief and damage prevention structure shown in FIGS. 2A to 2D is different from that of FIGS. 1A to 1D. The opening 56a 56b for forming the stress relief and damage prevention structure has a lower conductive layer 50. Is not exposed. However, openings 56a and 56b are filled with conductive material 58 as shown in FIGS. 2B and 2C to form stress relief and damage prevention structures 62a and 62b. Such structures 62a and 62b relieve stress applied to the insulating film 52 during laser fusing of the upper metal layer patterns 64b and 64c in contact with them, and also prevent damage to adjacent metal layer patterns. Reference numerals 48, which are not described with reference to FIGS. 2A to 2D, denote semiconductor substrates, 50 denote conductive layers, 64 denote upper metal layers, 54 denote contact holes, and 60 denote contact plugs.
제 1 실시예 및 제 2 실시예의 스트레스 완화 및 손상 방지 구조체(22a, 22b; 62a, 62b)의 높이, 모양 및 위치는 레이저 퓨징 시 사용되는 레이저 빔의 세기, 도전성 패턴을 구성하는 물질, 절연막을 구성하는 물질 또는 도전성 패턴들 간의 간격에 의해 결정될 수 있다. 스트레스 완화 및 손상 방지 구조물의 모양이란, 금속층 패턴(24b, 24c;64b, 64c)과 접촉하는 면적 및 접촉 면적의 모양을 포함한다.The height, shape, and position of the stress relief and damage prevention structures 22a, 22b; 62a, 62b of the first and second embodiments are determined by the strength of the laser beam used in laser fusing, the material constituting the conductive pattern, and the insulating film. It may be determined by the gap between the constituent material or the conductive patterns. The shape of the stress relief and damage prevention structure includes the shape of the contact area and the area in contact with the metal layer patterns 24b, 24c; 64b, 64c.
도 3a는 본 발명의 사상을 적용하여 스트레스 완화 및 손상 방지 구조체를 형성한 뒤 상부 금속층을 레이저 퓨징하여 획득한 금속층 패턴의 평면도를 보여주는 사진이고 도 3b는 스트레스 완화 및 손상 방지 구조체를 형성하지 않고 상부 금속층을 레이저 퓨징으로 패터닝하여 완성된 금속층 패턴의 평면도를 보여준다.3A is a photograph showing a plan view of a metal layer pattern obtained by forming a stress relief and damage prevention structure by applying the idea of the present invention and then laser fusing the upper metal layer, and FIG. 3B is a top view without forming the stress relief and damage prevention structure. The metal layer is patterned by laser fusing to show a plan view of the completed metal layer pattern.
도 3a 및 도 3b에서 동그랗게 형성된 부분이 레이저 퓨징에 의해 절단된 면을 나타내는 것으로, 도 3b의 절단 면적에 비해 도 4a의 절단면적이 작음을 알 수 있다. 즉, 본 발명의 기술을 적용하면, 레이저 퓨징 시 인접 도전층 패턴과 연결되어 브리지를 형성할 가능성이 줄어들음을 알 수 있다.3A and 3B, the circularly shaped portion shows a surface cut by laser fusing, and it can be seen that the cutting area of FIG. 4A is smaller than that of FIG. 3B. In other words, applying the technique of the present invention, it can be seen that the possibility of forming a bridge by connecting to an adjacent conductive layer pattern during laser fusing is reduced.
또한, 도 3a의 절단면은 도 3b의 절단면이 비해 상당히 깨끗하므로, 본 발명의 기술에 따른 도전층 패턴 형성 시 레이저 퓨징 시에 발생되는 도전성 파편이 상대적으로 적음을 알 수 있다. 즉, 본 발명에 따른 반도체 소자는 인접 도전성 패턴 또는 반도체 기판에 가해지는 손상을 억제할 수 있음을 알 수 있다.In addition, since the cut surface of FIG. 3A is considerably cleaner than the cut surface of FIG. 3B, it can be seen that relatively few conductive fragments are generated during laser fusing when forming the conductive layer pattern according to the technique of the present invention. In other words, it can be seen that the semiconductor device according to the present invention can suppress damage to adjacent conductive patterns or semiconductor substrates.
본 발명의 제 1 실시예 및 제 2 실시예에서는 절연막(12, 62)의 하부에 도전층을 형성하였으나, 도전층 대신 절연층이 형성된 경우에도 본 발명은 적용될 수 있다. 이 경우에는 콘택홀을 형성하기 위한 공정이 필요하지 않게 된다.In the first and second embodiments of the present invention, a conductive layer is formed below the insulating layers 12 and 62, but the present invention can be applied even when the insulating layer is formed instead of the conductive layer. In this case, a process for forming a contact hole is not necessary.
또한, 형성하고자 하는 상부 금속층 하부에 절연막이 형성되어 있지 않은 구조를 갖는 반도체 소자에 있어서는, 다른 단위 소자의 기능에 영향을 주지 않는 범위 내에서 절연막을 더 형성한 뒤, 본 발명의 사상을 적용할 수도 있다.In addition, in a semiconductor device having a structure in which an insulating film is not formed below the upper metal layer to be formed, after the insulating film is further formed within a range that does not affect the function of other unit devices, the idea of the present invention may be applied. It may be.
전술한 바와 같이, 다층 구조물을 가지는 반도체 소자에 있어서, 레이저 퓨징에 의해 패턴을 형성하고자 하는 층 하부에 위치하는 절연막 내에 패턴 형성층과 연결되는 구조체를 형성하여, 상부 패턴 형성 시 절연막으로 전달될 수 있는 스트레스를 완화하고, 고집적 반도체 소자의 인접 도전층 패턴 또는 기판의 손상을 억제할 수 있다.As described above, in a semiconductor device having a multi-layer structure, a structure connected to the pattern forming layer is formed in an insulating film positioned under the layer to be formed by laser fusing, which may be transferred to the insulating film when the upper pattern is formed. Stress can be alleviated and damage to the adjacent conductive layer pattern or substrate of the highly integrated semiconductor element can be suppressed.
Claims (8)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592206B2 (en) | 2006-01-12 | 2009-09-22 | Samsung Electronics Co., Ltd. | Fuse region and method of fabricating the same |
| KR100967047B1 (en) * | 2008-03-13 | 2010-06-29 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7592206B2 (en) | 2006-01-12 | 2009-09-22 | Samsung Electronics Co., Ltd. | Fuse region and method of fabricating the same |
| KR100967047B1 (en) * | 2008-03-13 | 2010-06-29 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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