KR100855867B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to enhance characteristics of the semiconductor device by preventing an SAC(Self Aligned Contact) fail among a bit line contact, a storage electrode contact, and a gate. A planarized landing plug poly layer is formed on a semiconductor substrate(200) including a gate pattern(210). A photoresist layer pattern is formed on the landing plug poly layer of a bit line contact region and a storage electrode contact region. A landing plug contact(220a) is formed on the bit line contact region and the storage electrode contact region by etching the landing plug poly layer. A first interlayer dielectric(225) is formed on an entire surface including the landing plug contact. A bit line contact hole is formed by etching the first interlayer dielectric. A bit line material layer is formed on the entire surface including the bit line contact hole. A bit line is formed by patterning the bit line material layer. A second interlayer dielectric is formed on the entire surface. A storage electrode contact hole(245) is formed by etching the second interlayer dielectric and the first interlayer dielectric.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views and plan views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

100, 200: semiconductor substrate 105, 205: device isolation film

110a, 210a: gate polysilicon layer 110b, 210b: gate metal layer

110c and 210c: gate hard mask layer 110 and 210: gate pattern

115, 215: spacer 120, 220: landing plug poly layer

120a, 220a: landing plug contact 125, 240: second interlayer insulating film

130, 230: bit line contact hole 135, 235: bit line

137: third interlayer insulating layer 140, 245: storage electrode contact hole

225: first interlayer insulating film 223: photosensitive film pattern

107a and 207a: storage electrode contact region

107b and 207b: bit line contact area

The present invention relates to a method of manufacturing a semiconductor device, and includes forming a landing plug contact that rises above a predetermined height above a gate hard mask layer, and etching the landing plug contact formed on the gate hard mask layer. By forming a bit line contact hole and a storage electrode contact hole, which are subsequent processes, the gate hard mask layer is prevented from being lost, and a SAC fail between the bit line contact and the storage electrode contact and the gate is self aligned. Disclosed is a technique for preventing the occurrence of Contact Fail to improve the characteristics of the device.

As the degree of integration of semiconductor devices increases, process margins decrease. Accordingly, in order to form a contact connecting the source and the bit line, the drain and the storage electrode, a Self Aligned Contact (SAC) process is mainly used.

When the self-aligned contact process is used as described above, even if mis-alignment occurs, the nitride film acts as a buffer film to prevent the bridge phenomenon between the gate conductive layer and the contact plug.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a recess is formed by etching a semiconductor substrate 100 provided with an isolation layer 105 by a predetermined depth.

Next, a stacked structure of the gate polysilicon layer 110a, the gate metal layer 110b, and the gate hard mask layer 110c is formed on the entire surface including the recess, and then patterned to form the gate pattern 110. .

Next, nitride film spacers 115 are formed on both sides of the gate pattern 110.

Then, the first interlayer insulating layer (not shown) is formed on the entire upper portion, and the first interlayer insulating layer (not shown) is etched by SAC to form a landing plug contact hole (not shown).

Next, the landing plug poly layer 120 is formed on the entire surface including the landing plug contact hole (not shown).

Referring to FIG. 1B, the planarization process is performed until the gate hard mask layer 110c on the gate pattern 110 is exposed to form a landing plug contact 120a between the gate patterns 110.

1C and 1D, a second interlayer insulating layer 125 is formed on the semiconductor substrate 100 on which the landing plug contact 120a is formed.

Next, the second interlayer insulating layer 125 of the bit line contact region 107b is etched to form a bit line contact hole 130 exposing the landing plug contact 120.

Referring to FIG. 1E, a bit line material layer is formed and patterned on the whole including the bit line contact hole 130 to form a bit line 135.

Next, a third interlayer insulating layer 137 is formed over the entirety including the bit line 135, and the third interlayer insulating layer 137 and the second interlayer insulating layer 125 of the storage electrode contact region 107a are etched. As a result, the storage electrode contact hole 140 exposing the landing plug contact 120a is formed.

In this case, the storage electrode contact hole 140 may be formed at both sides of the bit line contact with respect to the long axis direction of the active region.

In the above-described method of manufacturing a semiconductor device, a nitride film, which is a gate hard mask layer, is lost during a planarization process for forming a landing plug contact, and thus, during a self-aligned contact process. Since the gate hard mask layer does not function as a barrier, the SAC margin is insufficient, resulting in a SAC fail in which a short is generated between the contact and the gate.

In order to solve the problem, a landing plug contact that rises above a predetermined height is formed on the gate hard mask layer, and the landing plug contact formed on the gate hard mask layer is used as an etch target. By forming the bit line contact hole and the storage electrode contact hole, which are subsequent processes, the gate hard mask layer is prevented from being lost and a SAC fail occurs between the bit line contact and the storage electrode contact and the gate. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which prevents the semiconductor device from improving.

Method for manufacturing a semiconductor device according to the present invention

Forming a planarized landing plug poly layer on the semiconductor substrate on which the gate pattern is formed;
Forming a photoresist pattern on the landing plug poly layer on the bit line contact region and the storage electrode contact region;

Etching the landing plug poly layer using the photoresist pattern as an etch mask to form a landing plug contact protruding above the gate pattern on the bit line contact region and the storage electrode contact region;

Forming a first interlayer insulating film over the entirety of the landing plug contact;

Etching the first interlayer insulating film to form a bit line contact hole exposing a landing plug contact of the bit line contact region;

Forming a bit line material layer on the whole including the bit line contact hole and patterning the bit line material layer to form a bit line;

Forming a second interlayer insulating film on the whole;

Etching the second interlayer insulating film and the first interlayer insulating film to form a storage electrode contact hole exposing a landing plug contact of the storage electrode contact region;

The gate pattern is a laminated structure of a gate polysilicon layer, a gate metal layer and a gate hard mask layer,

The bit line contact hole and the storage electrode contact hole forming process may be performed using the landing plug contact as an etch target.

delete

delete

delete

delete

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2F are cross-sectional views and plan views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, a gate pattern 210 and a landing plug contact hole (not shown) are formed on the semiconductor substrate 200 having the device isolation layer 205 defining the active region.

The gate pattern 210 may be formed as a stacked structure of the gate polysilicon layer 210a, the gate metal layer 210b, and the gate hard mask layer 210c, and the nitride layer spacer 215 may be provided on both sides of the gate pattern 210. do.

In addition, the landing plug contact hole (not shown) is preferably formed by a Self Aligned Contact (SAC) process.

Next, the landing plug poly layer 220 is formed on the entire surface including the landing plug contact hole (not shown).

Next, the landing plug poly layer 220 is planarized by performing a chemical mechanical polishing (CMP) process.

In this case, the CMP process may be performed such that the landing plug poly layer 220 has a predetermined thickness from an upper portion of the gate pattern 210.

FIG. 2B (i) is a plan view showing a photoresist pattern formed thereon, and includes an active region 203 and a gate pattern 210 having a line shape in a direction perpendicular to the active region 203.

Here, the center portion is defined as a bit line contact region 207b based on two gate patterns 210 passing through the active region 203, and both sides of the edge portion of the active region 203 are referred to as the storage electrode contact region 207a. define.

The photoresist pattern 223 is formed on the bit line contact region 207b and the storage electrode contact region 207a.

FIG. 2B (ii) shows a cut plane taken along the line AA ′ of FIG. 2B (i), wherein the photoresist film is formed over the landing plug poly layer 220 on the bit line contact region 207b and the storage electrode contact region 207a. The pattern 223 is formed.

Referring to FIG. 2C, the landing plug poly layer 220 is etched using the photoresist pattern 223 as a mask to form a landing plug contact 220a exposing the gate hard mask layer 210c.

Here, the landing plug contact 220a is formed to protrude above the gate pattern 210 on the bit line contact region 207b and the storage electrode contact region 207a.

Next, the photosensitive film pattern 223 is removed.

2D and 2E, after forming the first interlayer insulating layer 225 over the entire area including the bit line contact region 207b and the storage electrode contact region 207a, the bit line contact hole may be formed. Carry out the CMP process until the height is reached.

Next, the first interlayer insulating layer 225 is etched to form a bit line contact hole 230.

In this case, the bit line contact hole 230 may be etched only to a portion spaced apart from the top of the gate pattern 210 by a predetermined thickness using the landing plug contact 220a as an etching target.

Referring to FIG. 2F, a bit line material layer is formed on the semiconductor substrate 200 including the bit line contact hole 230 and then patterned to form a bit line 235.

Next, the second interlayer insulating film 240 is formed over the entire surface, and the second interlayer insulating film 240 and the first interlayer insulating film 225 are etched to form the storage electrode contact hole 245.

In this case, the storage electrode contact hole 245 uses the landing plug contact 220a as an etch target, and is etched only to a part spaced apart from the upper portion of the gate pattern 210 by a predetermined thickness in the same manner as the bit line contact hole 230. It is desirable to.

Therefore, since the landing plug contact 220a is formed to protrude from the upper side of the gate pattern 210, the gate hard mask layer 210c on the gate pattern 210 is not lost, and the bit line contact and the storage electrode contact are not lost. SAC fail between the gate and the gate can be prevented.

The method of manufacturing a semiconductor device according to the present invention forms a landing plug contact that rises above a predetermined height above a gate hard mask layer, and forms the landing plug contact formed on the gate hard mask layer as an etch target ( Target to form a subsequent bit line contact hole and a storage electrode contact hole, thereby preventing the gate hard mask layer from being lost, and SAC fail between the bit line contact and the storage electrode contact and the gate. There is an effect that the characteristics of the device is improved by preventing the occurrence of a failure.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

Forming a planarized landing plug poly layer on the semiconductor substrate on which the gate pattern is formed; Forming a photoresist pattern on the landing plug poly layer on a bit line contact region and a storage electrode contact region; Etching the landing plug poly layer by using the photoresist pattern as an etch mask to form a landing plug contact protruding upward from the gate pattern on the bit line contact region and the storage electrode contact region; Forming a first interlayer insulating film over the entirety of the landing plug contact; Etching the first interlayer insulating layer to form a bit line contact hole exposing a landing plug contact of the bit line contact region; Forming a bit line material layer on the whole including the bit line contact hole and patterning the bit line material layer; Forming a second interlayer insulating film on the entirety; And Etching the second interlayer insulating film and the first interlayer insulating film to form a storage electrode contact hole exposing a landing plug contact of the storage electrode contact region; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The gate pattern is a semiconductor device manufacturing method, characterized in that the laminated structure of the gate polysilicon layer, the gate metal layer and the gate hard mask layer. The method of claim 1, The bit line contact hole and the storage electrode contact hole forming process may be performed using the landing plug contact as an etch target. delete

Images