KR20020018610A - 집적 디바이스를 위한 이중 상감 콘택트 - Google Patents

집적 디바이스를 위한 이중 상감 콘택트 Download PDF

Info

Publication number
KR20020018610A
KR20020018610A KR1020010053317A KR20010053317A KR20020018610A KR 20020018610 A KR20020018610 A KR 20020018610A KR 1020010053317 A KR1020010053317 A KR 1020010053317A KR 20010053317 A KR20010053317 A KR 20010053317A KR 20020018610 A KR20020018610 A KR 20020018610A
Authority
KR
South Korea
Prior art keywords
layer
conductive member
semiconductor
conductive
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020010053317A
Other languages
English (en)
Korean (ko)
Inventor
아디반지오리카르드슨오
얀이팬지윈스톤
Original Assignee
추후기재
에이저 시스템즈 가디언 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 추후기재, 에이저 시스템즈 가디언 코포레이션 filed Critical 추후기재
Publication of KR20020018610A publication Critical patent/KR20020018610A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR1020010053317A 2000-08-31 2001-08-31 집적 디바이스를 위한 이중 상감 콘택트 Withdrawn KR20020018610A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65244900A 2000-08-31 2000-08-31
US09/652,449 2000-08-31

Publications (1)

Publication Number Publication Date
KR20020018610A true KR20020018610A (ko) 2002-03-08

Family

ID=24616872

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010053317A Withdrawn KR20020018610A (ko) 2000-08-31 2001-08-31 집적 디바이스를 위한 이중 상감 콘택트

Country Status (3)

Country Link
JP (1) JP2002164430A (https=)
KR (1) KR20020018610A (https=)
GB (1) GB2371146A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505682B1 (ko) * 2003-04-03 2005-08-03 삼성전자주식회사 금속-절연체-금속 커패시터를 포함하는 이중 다마신 배선구조 및 그 제조방법
KR101373918B1 (ko) * 2006-01-13 2014-03-12 마이크론 테크놀로지, 인크. 반도체 디바이스에서 추가의 금속 라우팅을 형성하기 위한 시스템 및 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
FR2754391B1 (fr) * 1996-10-08 1999-04-16 Sgs Thomson Microelectronics Structure de contact a facteur de forme eleve pour circuits integres
JP3228181B2 (ja) * 1997-05-12 2001-11-12 ヤマハ株式会社 平坦配線形成法
US6100190A (en) * 1998-02-19 2000-08-08 Rohm Co., Ltd. Method of fabricating semiconductor device, and semiconductor device
JP3293792B2 (ja) * 1999-01-12 2002-06-17 日本電気株式会社 半導体装置及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505682B1 (ko) * 2003-04-03 2005-08-03 삼성전자주식회사 금속-절연체-금속 커패시터를 포함하는 이중 다마신 배선구조 및 그 제조방법
US7399700B2 (en) 2003-04-03 2008-07-15 Samsung Electronics Co., Ltd. Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating
KR101373918B1 (ko) * 2006-01-13 2014-03-12 마이크론 테크놀로지, 인크. 반도체 디바이스에서 추가의 금속 라우팅을 형성하기 위한 시스템 및 방법
US8674404B2 (en) 2006-01-13 2014-03-18 Micron Technology, Inc. Additional metal routing in semiconductor devices

Also Published As

Publication number Publication date
JP2002164430A (ja) 2002-06-07
GB0121198D0 (en) 2001-10-24
GB2371146A (en) 2002-07-17

Similar Documents

Publication Publication Date Title
US5946567A (en) Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits
US5801094A (en) Dual damascene process
US6225211B1 (en) Method for making stacked and borderless via structures on semiconductor substrates for integrated circuits
US5891799A (en) Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates
US6566283B1 (en) Silane treatment of low dielectric constant materials in semiconductor device manufacturing
US6905964B2 (en) Method of fabricating self-aligned metal barriers by atomic layer deposition on the copper layer
US11164776B2 (en) Metallic interconnect structure
JP2007221161A (ja) 半導体デバイスで用いられるキャパシタとその製造方法
JPH0855913A (ja) サブミクロン相互接続の選択的空隙充填方法
US6495448B1 (en) Dual damascene process
US6888247B2 (en) Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same
US6035530A (en) Method of manufacturing interconnect
US6483142B1 (en) Dual damascene structure having capacitors
CN118943128B (zh) 金属-绝缘体-金属电容及其形成方法
EP1330842B1 (en) Low temperature hillock suppression method in integrated circuit interconnects
US5880030A (en) Unlanded via structure and method for making same
US20070264824A1 (en) Methods to eliminate contact plug sidewall slit
US11177160B2 (en) Double patterned lithography using spacer assisted cuts for patterning steps
US11189527B2 (en) Self-aligned top vias over metal lines formed by a damascene process
GB2325083A (en) A dual damascene process
US6784095B1 (en) Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing
WO2003003475A2 (en) Semiconductor device comprising a mim capacitor and an interconnect structure
US20240120369A1 (en) High density trench capacitor
KR100684905B1 (ko) 다마신 공정의 방법
JP4232215B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000