KR20020018610A - Dual damascene contact for integrated devices - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit structure and a method for fabricating the structure are provided to obviate drawbacks related to seams or voids formed in metal contacts between interconnection levels. CONSTITUTION: The structure(10) includes a semiconductor layer(14) having a top surface region(12) where a transistor(18) is formed. Metallization levels(40,50,60) formed on the semiconductor layer(14) have conductive members(62,62a,62b,62c) formed in dielectric layers(64a,64b,64c). Contacts(30,30a), which are conventionally formed, provide connections between the metallization levels(40,50,60). In particular, a capacitor(70) is formed in an upper metallization level(60), being connected to the conductive member(62a) of a lower metallization level(50) through a dual damascene contact(74). Another dual damascene contact(74a) connects the conductive members(62b,62c) of the metallization levels(50,60). Each of the dual damascene contacts(74,74a) has a narrow portion extending to the conductive member(62a,62b) of the lower metallization level(50), and a wide portion extending to the conductive member(62c) of the upper metallization level(60).

Description

Dual damascene contact for integrated devices

Field of invention

TECHNICAL FIELD The present invention relates to semiconductor devices, and more particularly to connections between conductive members in circuit structures.

background

As the semiconductor process integration level progresses, the density of multilevel interconnect schemes continues to increase, and the associated feature sizes become smaller. In fact, semiconductor interconnect requirements are considered one of the most demanding aspects of ultra-scale integration performance. Among other concerns, it is difficult to maintain acceptable levels of device reliability as devices become increasingly compact.

Typically, complex semiconductor devices require three or more interconnect levels to perform circuit connections. In these structures, a connection is made between conductive members on different interconnect levels by bias or formation of contacts. By way of example, in an aluminum metallization scheme, the structure alternatively forms dielectric layers and patterns metal conductor layers on each other. After each dielectric layer is formed and before the next metallization level is produced, the contacts are generally formed by first etching through the openings through the top dielectric layer to expose regions underlying the previous metallization level. Barrier metals (eg, a stack of Ti and TiN) are deposited in the openings, followed by deposition of a refractory metal such as tungsten, but Co and Al may also be deposited. Due to the width (or diameter) of the openings, which become smaller as the device geometries shrink, the void or seam is typically formed into via openings as the metal is deposited. Often the voids extend through the surface of the dielectric layer and are exposed as excess metal is removed from the surface, for example by chemical mechanical polishing. The resulting structure is a problem of great concern because it causes reliability problems and frequently requires reworking of semiconductor wafers during device fabrication. B. Kassab such as the "sub of using H ₂ O ₂ containing slurry-processor methodology of reducing rework and plug core ring in the quarter-micron tungsten chemical mechanical planarization (Process Methodologies to Reduce Rework and Plug Coring in Sub-Quarter Micron Tungsten Chemical Mechanical Planarization Using H ₂ O ₂ Containing Slurries), June 27-29, Proc. See VMIC Conference, pp. 189-194 (2000). In addition, "N ₂ / H ₂ of a low temperature in combination with the plasma processing CVD TiN deposition (Low Temperature CVD TiN Deposition Combined with N ₂ / H ₂ Plasma Treatment to Prevent Al Extrusion) in order to prevent Al extrusion", 6, such as YC Chang 27-29, Proc. See VMIC Conference, pages 297-301 (2000).

One particular problem associated with the formation of voids or seams in metal contacts is known as coring, where the polishing process leads to enlargement of the voids to the point where it affects the next production and causes reliability problems. A second related problem stems from the conformal nature of materials deposited on contacts. For example, when a relatively thin dielectric layer is deposited on an exposed void or seam of a contact, the thickness of the layer around the contact can be further reduced. This may create a short or provide a breakdown in the regions resulting in dielectric breakdown under electrical stress. A third problem associated with contact seams and again magnified by coring is metal movement, in particular metal movement in Al interconnect systems. Electrophoresis is known to result in the movement of Al to contact seams, creating voids in the interconnect layers, and inducing device failure.

By overcoming the problems associated with seams in metal contacts, it can contribute to the advancement of integration level and device reliability, especially for devices with metallization schemes made by subtractive metal etching processes.

According to one embodiment of the invention, the semiconductor structure comprises spatially separated metallization levels formed on a semiconductor layer each level comprising a conductive member. The contact connects the first levels of conductive member with the second levels of conductive member. The contact includes a narrow portion extending to the first level conductive member and a wide portion extending from the narrow portion toward the second level conductive member.

According to another aspect of the invention, there is also provided an integrated circuit device having a semiconductor layer surfaced along a plane. The metallization level includes a conductive member formed on the surface, and a layer of dielectric material having an upper surface is formed between the semiconductor surface and the conductive member. The electrical contact extends through the dielectric material layer along an axis of normal alignment with respect to the surface. The contact includes a wide portion extending from the top surface along the axis in the dielectric layer and a narrow portion extending from this wide portion along the axis toward the surface of the semiconductor layer.

In yet another embodiment, a method of making a semiconductor structure includes forming a dielectric material layer having a top surface on a semiconductor layer. The opening is formed in the dielectric layer. The opening includes a wide portion extending from the top surface and a narrow portion extending from the wide portion toward the semiconductor layer. Both narrow and wide portions of the opening are filled with a conductor material, and a metallization level comprising the conductive member is formed on the opening in the electrical contact with the conductor material.

1 is a cross-sectional view illustrating an exemplary embodiment of the present invention.

2-5 are cross-sectional views illustrating details relating to the manufacture of the embodiment of FIG. 1.

* Explanation of symbols for the main parts of the drawings *

10: integrated circuit structure 12: top surface area

14 semiconductor layer 18 transistor

20: source / drain region 22: gate structure

30: contact 62: conductive member

70: capacitor 88: capacitor plate

92: opening 95, 98: wide part

96, 100: narrow portion 97: deformed opening

Numerous advantages of the present invention will become apparent upon reading the following detailed description of the invention with reference to the accompanying drawings.

Although the same reference numerals represent the same elements throughout the drawings, it should be noted that the various features illustrated in the drawings are not compared with each other.

Terms

The illustrated layers and other elements can include two or more sub-layers or sub-elements. When a layer or other device is formed or disposed on another feature, the device can be a direct contact with the other feature or can be spatially separated from the other feature by, for example, an intervening device. have. Moreover, elements disclosed on other features need not necessarily be perpendicular to the features, but may be formed on the side portions of other features, for example.

The terms vertical and horizontal refer to approximately orthogonal orientation of one surface with respect to the other surface, wherein either surface may be formed in one plane, while one or all surfaces may have irregularities or semiconductor devices May have curvature of what exists along other features and layers of the same. For example, some so-called vertically etched openings are known to have tapered profiles. In general, features resulting from anisotropic etching, such as bias, are characterized in that the walls cannot follow straight lines but are perpendicular to the crystal plane, and the orientation cannot be orthogonal with respect to the reference plane.

The interconnect structures are a plurality of conductive members configured to support the implementation of one or more circuit functions. In a complex circuit design, interconnect structures comprise layers or layers of layers that are formed sequentially, which creates and electrically insulates conductive members. The metallization or interconnect level is a group of conductive members formed during the same sequence of processing, for example in the photolithography step and the associated etching step, to provide a network of conductive members, some of which are dielectrics such as silicon oxide or silicon nitride Insulated from others by materials. The conductive members may comprise polysilicon, Al or Cu may be an alloy, and may be included in the silicide to reduce sheet resistance.

details

In the illustrated embodiments, the present invention can provide semiconductor structures with a bias having improved reliability. The invention is applicable to a wide range of semiconductor designs, including complex analog circuits and so-called on-chip systems. In the embodiments provided, the invention applies to integrated circuit structures having three or more metallization levels. Several or more levels may be used for the sake of brevity of indication, but the illustrated embodiments represent three metallization levels. For example, when fabricated in typical ultra-scale integrated (ULSI) processes to produce feature sizes less than 0.25 μ, integrated circuit structures may require the use of the present invention to ensure device reliability. And electrical performance requirements.

Referring to FIG. 1, the present invention describes the formation and connection of interconnect level metal oxide metal capacitor structures on a semiconductor substrate as well as the formation of contacts between two interconnect levels. Integrated circuit structure 10 shown in partial cross section includes a semiconductor layer 14 having a top surface region 12 formed along a horizontal crystal plane. Metal oxide semiconductor (MOS) field effect transistors 18 are formed in region 12. Other devices, including diodes and other types of transistors (eg, bipolar devices or MESFETs) can be formed in the surface region 12, but they need not be illustrated for the purpose of describing the present invention. .

An example of the transistors 18 is shown to include source / drain regions 20 and gate structure 22. Although the gate structure 22 has not been described in detail, the figure shows a gate dielectric, a gate conductor (typically deposited by a silicide formed thereon to reduce sheet resistance) to insulate the gate structure from adjacent conductive elements. Silicon MOSFETs and common MOSFET components including sidewall filaments formed on conductive portions. For the sake of brevity of display, other features generally formed around the top surface area 12 (eg, insulating structures) are not shown in the figures.

An initial level 28 of dielectric insulator is deposited on the transistors, and typically formed contacts 30 comprising contacts 30a are provided with metallization levels (overlapping from various transistor regions and other features). 40, 50, and 60) and between the metallization levels. Each metallization level includes multiple conductive members 62, some of which are shown in the figures. 1 is taken along a plane parallel to the direction in which the member 62a of the interconnect level 50 extends. This figure also shows the member 62b of the level 50 extending in a direction orthogonal to the direction in which the member 62a extends. Multiple members 62 formed of levels 40 and 60 extend in a direction parallel to member 62b. Generally, each level of member 62 is formed in insulating layer 64a or 64b. In this example, the members are assumed to be formed of Al.

In accordance with the illustrated embodiment, capacitor 70 is formed at metallization level 60 by connection of metallization level 50 to conductive member 62a via double damascene contact 74. Most preferably, the contact 74 has a planar top surface 78 that provides an interface, on which a first metal layer is formed to provide the first capacitor plate 80, and an insulating layer is formed on the plate 80. Patterned to provide a capacitor dielectric 84, and a second metal layer is formed on dielectric layer 84 to provide second capacitor plate 88. Conventional contact 30 provides a connection from the second capacitor plate 88 to another metallization level or to a bond pad (not illustrated). For purposes of illustrating the general utility of the present invention, another dual damascene contact 74a is illustrated as connecting the conductive member 62b of level 50 to member 60c of overlapping level 60.

Details of selective fabrication for integrated circuit structure 10 are described below. However, the choice of dielectric and conductive materials may vary depending on the application. A brief discussion useful for forming suitable dielectric materials is first provided in connection with the preferred embodiment.

There are generally a number of methods useful for forming silicon oxide that electrically insulates conductors from each other within a multilevel interconnect structure, as shown in FIG. Often, the interlevel dielectric will include sublayers to optimize the desired set of attributes, such as gap fill and planarity. The first interconnect level generally deposited on transistor structures and polysilicon conductors is often phosphorus and boron-doped deposition. The presence of phosphorus allows recirculation at about 1000 ° C., while the use of boron and phosphorus further reduces the flow temperature. Dielectric materials that provide insulation between different levels of metal conductors of an interconnect structure (intermetallic dielectric) may be silicon oxide deposited by a chemical vapor deposition (CVD) process. These include atmospheric CVD, low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD), all of which may be based on the decomposition of silanes. Adding phosphorus to the reaction is common and results in phosphosilicate glass (PSG), which improves resistance to moisture and gettering.

Tetraethyl orthosilicate, or TEOS, Si (OC ₂ H ₅ ) _4, is widely used as a precursor in the formation of silicon oxide for all interlevel dielectrics. Decomposition of the vaporized liquid TEOS to form a silicon oxide film (TEOS-deposited oxide) typically occurs by CVD at 650 ° C. to 750 ° C. in an oxygen environment. Such TEOS depositions are known to provide good uniformity and step coverage. In general, a deposited film is understood to be the nonstoichiometric oxide of silicon, although it is often referred to as silicon dioxide. Inclusion of ozone (O ₃ ), for example up to 10% of the reacting oxygen, promotes low temperature depositions by good morphological properties, low viscosity and improved gap-filling properties. Typical reaction environments are 400 ° C. and 300 Torr with 4 standard liters of oxygen per minute and oxygen includes 6% ozone, 1.5 slm He and 300 standard cubic centimeters per minute (sccm) TEOS. The resulting deposit has gap-filling properties appropriate for regions between individual metal lines on the same metallization level. The TEOS-deposition film can be doped with phosphorus.

Alternatively, the silicon oxide layer may be formed by high density plasma deposition (HDP). Deposits referred to as HDP oxides may include undoped silicate glass (USG) or fluoro-doped silicate glass (FSG).

Detailed descriptions of such dielectric materials and other variants are well known. For example, Wolf's Silicon Processing for the Vlsi Era. See Volume 2, Process Integration, Lattice Press 1990.

Optional exemplary details of fabrication of integrated circuit structure 10 are shown in FIGS. 2 and 3 for an exemplary subtracted metal etching technique. An initial layer 28 of dielectric insulator is formed on the transistor 18 and exposes portions of the surface region 12. Insulator layer 28 may be formed by first depositing HDP oxide (200 nm ± 20 nm) from silane at 350 ° C. to 550 ° C. and plasma enhanced deposition of silicon oxide from TEOS by densification at 700 ° C. for 120 minutes. The resulting thickness of the insulating layer can range from 28 up to 9500 nm.

Contacts designated 30a are formed in insulator layer 28 to provide a connection, for example, between the various transistor regions and the first metallization level 40 still to be formed. Contact formation at insulator level 28 begins by patterning the deposited photoresist to limit the bias and then by anisotropic etching, for example CHF ₃ / C ₂ F ₆ . The contact typically includes refractory metals. Optional materials include W, Ti and Ta. Preferably, all the contacts are formed of W.

After the bias is etched, the contacts 30a first deposit a Ti barrier sublayer (about 60 nm at 400 ° C., not illustrated) by successive sputtering, followed by depositing the TiN sublayer (also about 75 nm at 400 ° C., Not illustrated) and then formed inside by depositing and annealing. Next, 400 nm of W is deposited (at 425 ° C.), and the structure is polished to remove metal from the insulator surface level 28, providing sufficient planarity before formation of the first metallization level. The resulting contact is about 0.32μ wide and extends from 650nm to 950nm.

After defining the set underneath the contacts 30a, the first metallization level 40 is generally widely used, such as a 400 ° C. continuous sputter to form a Ti / TiN stack (Ti at 37 nm, TiN at 60 nm). It is formed by a known sequence and then by depositing an Al / Cu alloy of 400-700 nm and TiN of 25 nm. Conductive members 62 of metallization level 40 are defined by standard patterns and etching processes. On the metallization level 40 (as well as sequentially formed levels 50 and 60), an insulating layer 64, for example 600 nm HDP oxide and 1500 nm TEOS-deposited silicon oxide, is deposited. The insulating layer on level 40 is designated as layer 64a in the figures. The structure is planarized by metal topography followed by chemical mechanical polishing. The second level of contact 30 is then formed in dielectric layer 64a to provide an electrical connection between the completed metallization level 40 and the next metallization level 50. As described for the first level of contacts, the second level of conventional contacts 30 are formed by first depositing a Ti barrier, then depositing TiN, then annealing and depositing W. The exposed surface is then polished back to fully define the contacts 30, removing the metal that overlaps the dielectric layer 64, and providing sufficient planarity before the formation of the next metallization level. The resulting contacts are about 36μ wide.

The above description of forming the first interconnect level with the insulator layer 64a overlapping the contacts 30 can be applied to each subsequent interconnect level. Except for the features associated with capacitor 70 (FIG. 1), contact 74 and contact 74a, the fabrication of the following metallization levels is not disclosed in detail.

As metallization level 50 is deposited, patterned and etched, another layer of dielectric material 64 (designated 64b in FIG. 2) is deposited on structure 10. The formation of the dual inlay contacts 74 and 74a begins by etching the two through the openings 92 in the dielectric layer 64b between the metallization level 50 and the level 60 not yet formed. If conventional contacts 30 must also be formed between levels 50 and 60, additional openings 92 (not shown) are etched simultaneously. The openings 92 are lithographically patterned to about 0.36 micron wide and etched to about 600 nm anisotropic (CHF ₃ / C ₂ F ₆ / N ₂ ) to expose the conductive members 62 of the level 50. . The openings 92 are cylindrical and oriented perpendicular to the surface area 12. See FIG. 2 again.

Next, see FIG. 3. After standard purification, the area on the two openings 92 is lithographically patterned to about 1.2 micron wide and anisotropically etched to about 250 nm deep (CHF ₃ / C ₂ F ₆ / N ₂ ) so that the original opening 92 Create a wide portion 95 on the remaining narrow portion 96 of the. This results in the modified opening 97 illustrated in FIG. 3. The wide portion 95 of each deformed opening 97 is cylindrical and axially symmetric with the entire opening 92 within the lithographic alignment tolerance. In a preferred embodiment, the narrow portion 96 extends the opening from the wide portion 95 toward the semiconductor layer 14 and through the dielectric layer. However, the narrow portion 96 can enlarge as the opening extends through the layer 64.

The conductor is deformed by first depositing a Ti barrier layer (about 60 nm at 400 ° C., not illustrated), followed by annealing after depositing about 75 nm of TiN (also not at 400 ° C., not illustrated). It is formed within. Next, 400 nm of W is continuously deposited by CVD (at 425 ° C.) to fill both the narrow portion 96 and the wide portion 95 of the opening 97. The structure is polished to remove metal from the insulator level surface 28 and provide sufficient planarity before the formation of the next metallization level. See FIG. 4. The resulting contact 74 includes an upper wide portion 98 on the lower narrow portion 100. The wide portion 98 has a planar top surface 102 about 1.2 microns wide, with an associated depth of about 250 nm. The narrow portion 100 has a width of about 0.36 μ and a depth of 350 nm. Narrow portion 100 may include void 104 as an artificial product of W deposition. A feature of numerous embodiments of the present invention is that it does not exceed surface 102 until such voids 104 are formed in contacts 74 and 74a. It is contemplated that such voids can be suppressed from surface 102 by enlarging the width of the opening in the surface associated with the narrow portion.

Referring to FIG. 5, the capacitor 70 of FIG. 1 is formed on the contact surface 102 in connection with the formation of the conductive members 62 of the metallization level 60. The metal layer 110 (which forms the lower layer of the first capacitor plate 80 and the conductive members 62) is deposited as a whole. This is followed by the deposition of an insulating layer 112 (which provides a capacitor dielectric 84) on the metal layer 110.

Metal layer 110 is typically formed by a continuous sputter to form a Ti / TiN stack, such as 30 nm Ti and 60 nm TiN. The insulating layer may be composed of silicon oxide or tantalum peroxide deposited on the metal layer 110 by CVD. In addition, other insulator materials having a relatively large dielectric constant are desirable.

Prior to the formation of the conductor members 62 of the metallization level 60, the capacitor dielectric layer 84 is defined by patterning and etching steps to remove the insulating layer 112 from other regions of the structure 10. do. The remaining portion of layer 112 is surface area 12 and is rectangular in parallel planes and covers a predetermined area that matches the desired capacitance. In this embodiment of the present invention, second capacitor plate 88 (FIG. 1) is formed, patterned, and etched as the remainder of metallization level 60 is deposited. Metallization level 60 may be completed by depositing an Al / Cu alloy of 400-700 nm and TiN of 25 nm. When the conductive members 62 of the metallization level 60 are defined by a standard pattern and an etching process, the second capacitor plate 88 is also defined on the layer 84. See FIG. 1. Contact 30 is formed on second plate 88 to make a connection to a higher interconnect level or bond pad.

Structures useful for various shapes within the circuit structures, for example, contact areas such as cylindrical rectangles, tapered, and the like, have been disclosed. The use of this design according to the disclosed embodiment ensures the formation of a planar surface at the interface of electrical contacts and avoids the problems associated with the formation of overlapping layers with morphological deposition properties. Specifically, when metal layers and insulator material are deposited on metal contacts made in accordance with a preferred embodiment of the present invention, the contacts do not have exposed seams with overlapping layers along seam contours. Thus, for example, reliability problems associated with the integration of the capacitor dielectric around the contact seam are avoided. Also, for example, when interconnecting members comprising Al are deposited on contacts formed in accordance with a preferred embodiment of the present invention, the Al metal is not exposed to contact seams which may cause Al metal migration leading to device failure. Do not.

Although specific uses of the invention have been illustrated, the principles disclosed herein provide the basis for practicing the invention in a variety of ways on various circuit structures, including structures formed by III-V compounds and other semiconductor materials. Numerous variations will be apparent. Accordingly, other elements that are not specifically described herein do not depart from the scope of the present invention, which is solely limited by the following claims.

Claims (20)

In an integrated circuit device, A semiconductor layer having a surface along a plane, A metallization level comprising a conductive member and formed on the surface, A dielectric material layer having a top surface formed between the semiconductor surface and the conductive member, and An electrical contact extending through the layer of dielectric material, the contact including the electrical contact having a wide portion extending from the top surface into the dielectric layer and a narrow portion extending along the axis from the wide portion to the semiconductor layer. device. The method of claim 1, Wherein the narrow and wide portions are each cylindrical in shape and symmetrically oriented along an axis. The method of claim 1, And the wide portion of the electrical contact comprises a planar surface along the top surface of the dielectric layer. The method of claim 1, A second insulating layer formed between the electrical contact and the conductive member, and A conductive layer formed between the second insulating layer and the electrical contact; Wherein the combination of the conductive member, the second insulating layer and the conductive layer forms a capacitor. The method of claim 1, And the conductive member is an interconnect member. The method of claim 1, A second dielectric material layer having a top surface formed between the semiconductor layer and the electrical contact, and A second metallization level comprising a second conductive member, formed on an upper surface of the second dielectric material layer; And the electrical contact is in physical contact with the first conductive member and the second conductive member. The method of claim 6, The electrical contact comprises tungsten, titanium, and titanium nitride. The method of claim 1, And the electrical contact comprises tungsten. The method of claim 1, And the conductive member comprises Al. The method of claim 1, And said metallization level comprises a plurality of interconnecting members for performing circuit functions. The method of claim 1, And the narrow portion extends the opening through the semiconductor layer. In the method of manufacturing a semiconductor product, Providing a layer of semiconductor material, Forming a dielectric material layer having a top surface on the semiconductor layer, Forming an opening in the dielectric layer having a wide portion extending from the top surface and a narrow portion extending from the wide portion toward the semiconductor layer, and Filling both narrow and wide portions of the opening with a conductor material. The method of claim 12, Forming the narrow portion includes extending the opening through the layer of dielectric material, further comprising forming a metallization level on the top surface that includes a conductive member in electrical contact with the conductor material. , A method of manufacturing a semiconductor product. The method of claim 12, Providing a conductive region on the semiconductor layer; Forming the opening comprises disposing an opening on a conductive region, wherein the conductive region is electrically connected to a conductive member of a metallization level. The method of claim 12, Forming a conductor in the opening is by successive deposition of metal to fill both the narrow and wide portions. The method of claim 13, Prior to forming the metallization level, forming a conductive layer on a wide portion of the opening in electrical communication with the conductor in the opening, and Forming an insulating layer between the conductive layer and the conductive member, wherein the combination of the conductive layer, the insulating layer, and the conductive member further forms a capacitor. In a semiconductor structure, A semiconductor material layer having an upper surface formed along a crystal plane, A plurality of spatially separated metallization levels each formed on a semiconductor layer comprising a conductive member, A contact formed along an axis orthogonal to the plane, the contact electrically connecting first levels of conductive member with second levels of conductive member and extending from the narrow portion and the narrow portion extending to the first level conductive member And the contact having a wide portion extending toward a second level of conductive member. The method of claim 17, And the narrow portion extends to the second level of conductive member. The method of claim 17, And the wide portion is formed on the narrow portion. The method of claim 17, And the first conductive member is formed on the second conductive member.