KR20020017815A - A method for forming metal wire in semiconductor device using copper - Google Patents

A method for forming metal wire in semiconductor device using copper Download PDF

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KR20020017815A
KR20020017815A KR1020000051329A KR20000051329A KR20020017815A KR 20020017815 A KR20020017815 A KR 20020017815A KR 1020000051329 A KR1020000051329 A KR 1020000051329A KR 20000051329 A KR20000051329 A KR 20000051329A KR 20020017815 A KR20020017815 A KR 20020017815A
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forming
copper
semiconductor device
solution
metal wiring
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KR1020000051329A
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Korean (ko)
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최중일
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemically Coating (AREA)

Abstract

PURPOSE: A method for forming metal interconnection of a semiconductor device using copper is provided to simplify the manufacturing processes and to reduce manufacturing costs by using an electroless copper plating. CONSTITUTION: After forming an interlayer dielectric(11) on a silicon substrate(10) having a lower conductive layer, a contact hole is formed by selectively etching the interlayer dielectric(11). A Pd buffer layer(12) is formed at a metal wire formation region by using mixed solutions of Pd and HF. A copper metal wire(13) is formed on the Pd buffer layer(12) by an electroless copper plating using mixed solutions of a first solution composed of CuSO4·5H2O, HCHO, and CH3OH and a second solution composed of NaOH, KNa2H4O8·4H2O.

Description

구리를 이용한 반도체 소자의 금속배선 형성방법{A method for forming metal wire in semiconductor device using copper}A method for forming metal wire in semiconductor device using copper}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 금속배선 형성 공정에 관한 것이며, 더 자세히는 구리 무전해 도금법을 이용한 금속배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal wiring forming process in a semiconductor device manufacturing process, and more particularly, to a metal wiring forming process using a copper electroless plating method.

금속 콘택 형성 공정은 다층화된 반도체 소자를 제조하기 위해서는 필수적으로 도입되는 기술로, 상/하부 전도층 간의 수직배선의 근간이 된다. 한편, 반도체 소자의 고집적화에 따른 디자인 룰(design rule)의 축소에 따라 콘택홀의 에스펙트 비(aspect ratio)는 점차 증가하고 있으며, 이에 따라 금속 콘택 형성 공정의 난이도와 중요성이 증대되고 있다.The metal contact forming process is an essential technique for manufacturing a multilayered semiconductor device, and is a basis of vertical wiring between upper and lower conductive layers. On the other hand, the aspect ratio of the contact hole is gradually increasing as the design rule is reduced due to the higher integration of the semiconductor device, thereby increasing the difficulty and importance of the metal contact forming process.

알루미늄(Al)은 콘택 매립 특성이 우수하지 못함에도 불구하고 비저항이 낮고 공정이 비교적 용이하기 때문에 금속 배선 물질로서 가장 널리 사용되어 왔다. 그러나, 디자인 룰이 0.25㎛ 급으로 축소되면서 알루미늄으로 충분한 콘택 매립을 이룰 수 없게 되었다.Aluminum (Al) has been most widely used as a metal wiring material because of its low resistivity and relatively easy process despite the poor contact embedding characteristics. However, as design rules were reduced to 0.25 µm, sufficient contact filling with aluminum was not achieved.

이러한 알루미늄 금속배선의 한계를 고려하여 알루미늄에 비해 콘택 매립 특성이 우수한 구리를 금속배선 재료로 사용하는 기술에 대한 관심이 높아가고 있다. 통상적으로 구리를 사용하여 금속배선을 형성할 때 화학기상증착법(CVD)을 사용하고 있다.Considering the limitations of the aluminum metal wiring, there is a growing interest in the technology of using copper as a metal wiring material, which has better contact embedding properties than aluminum. In general, chemical vapor deposition (CVD) is used to form metal wiring using copper.

그런데, 구리는 식각 특성이 매우 불량한 단점을 가지고 있어 일반적인 금속배선 형성 공정에 적용하기 어렵다. 이러한 구리의 단점을 극복하기 위하여 대머신 금속배선 공정이 사용되고 있다.By the way, copper has a disadvantage that the etching characteristics are very poor, it is difficult to apply to the general metal wiring forming process. In order to overcome the drawbacks of copper, a metallization process is used.

통상적인 대머신 금속배선 공정은 층간절연막에 라인용 트렌치 및 콘택홀을 형성하고, 베리어 금속과 구리를 증착한 후 화학·기계적 평탄화(chemical mechanical planarization, CMP) 기술을 이용하여 층간절연막 상부에 있는 베리어 금속 및 배선 금속을 제거하는 과정을 거치고 있다.Conventional damascene metallization processes form trenches and contact holes for interlayer dielectrics, deposit barrier metals and copper, and then use chemical mechanical planarization (CMP) technology to form barriers on top of interlayer dielectrics. It is in the process of removing metal and wiring metal.

상기와 같은 종래의 구리 금속배선 공정은 공정이 다소 복잡한 단점이 있으며, 고가의 장비와 재료를 필요로 하는 CMP 공정을 적용해야 하는 비용 상의 문제점을 가지고 있다.The conventional copper metallization process as described above has a disadvantage in that the process is rather complicated, and has a cost problem of applying a CMP process requiring expensive equipment and materials.

상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 구리를 금속배선 재료로 적용함에 있어서, 공정을 단순화하고 제조 단가를 낮출 수 있는 반도체 소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the above problems of the prior art, in the application of copper as a metal wiring material, to provide a method for forming a metal wiring of a semiconductor device that can simplify the process and lower the manufacturing cost. have.

도 1 내지 도 3은 본 발명의 일 실시예에 따른 금속배선 형성 공정도.1 to 3 is a metal wiring formation process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 실리콘 기판10: silicon substrate

11 : 층간절연막11: interlayer insulating film

12 : Pd 버퍼층12: Pd buffer layer

13 : 구리층13: copper layer

상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 반도체 소자의 금속배선 형성방법은, 소정의 층간절연막을 관통하여 소정의 하부 도전층을 노출시키는 콘택홀을 형성하는 제1 단계; Pd-HF 혼합용액을 사용하여 금속배선이 형성될 영역에 Pd 버퍼층을 형성하는 제2 단계; 및 구리 무전해 도금법을 사용하여 상기 Pd 버퍼층 상에 구리층을 형성하는 제3 단계를 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: forming a contact hole through a predetermined interlayer insulating film to expose a predetermined lower conductive layer; A second step of forming a Pd buffer layer in a region where a metal wiring is to be formed using a Pd-HF mixed solution; And a third step of forming a copper layer on the Pd buffer layer using a copper electroless plating method.

바람직하게 본 발명은, 상기 제1 단계 수행 후, N2플라즈마 처리를 실시하여 상기 하부 도전층 상에 형성된 산화물을 제거하는 제4 단계를 더 포함하여 이루어진다.Preferably, the present invention further includes a fourth step of removing an oxide formed on the lower conductive layer by performing an N 2 plasma treatment after performing the first step.

바람직하게, 상기 Pd-HF 혼합용액은 PdCl2, HF, HCl, 빙초산, 순수의 혼합용액이다.Preferably, the mixed solution of Pd-HF is a mixed solution of PdCl 2 , HF, HCl, glacial acetic acid, pure water.

바람직하게, 상기 무전해 도금법은 CuSO4·5H2O, HCHO, CH3OH가 소정의 비율로 혼합된 제1 용액과, NaOH, KNa2H4O8·4H2O가 소정의 비율로 혼합된 제2 용액을 혼합한 용액을 사용한다.Preferably, in the electroless plating method, a first solution in which CuSO 4 · 5H 2 O, HCHO, CH 3 OH is mixed at a predetermined ratio, and NaOH, KNa 2 H 4 O 8 · 4H 2 O are mixed at a predetermined ratio. The mixed solution of the prepared second solution is used.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 1 내지 도 3은 본 발명의 일 실시예에 따른 금속배선 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1 to 3 illustrate a metallization process according to an embodiment of the present invention, which will be described below with reference to the drawings.

본 실시예에 따른 공정은 우선, 도 1에 도시된 바와 같이 실리콘 기판(10)에 대해 소정의 하부층 공정을 수행하고 평탄화된 층간절연막(11)이 형성된 상태에서, 층간절연막(11)을 선택적으로 식각하여 콘택홀(도시되지 않음)을 형성한다.In the process according to the present embodiment, first, as shown in FIG. 1, a predetermined lower layer process is performed on the silicon substrate 10 and the planarized interlayer insulating film 11 is selectively formed. Etching is performed to form contact holes (not shown).

다음으로, 도 2에 도시된 바와 같이 구리의 시드층으로 작용할 Pd 버퍼층(12)을 형성한다. Pd(palladium) 버퍼층(12)의 형성은 포토레지스트 패턴 등을 사용하여 배선 지역만을 노출시킨 상태에서 Pd-HF 혼합용액을 처리함으로써 형성할 수 있으며, 인쇄법을 사용할 수도 있다.Next, as shown in FIG. 2, a Pd buffer layer 12 that serves as a seed layer of copper is formed. The Pd (palladium) buffer layer 12 can be formed by treating the Pd-HF mixed solution in a state where only the wiring region is exposed by using a photoresist pattern or the like, and a printing method can also be used.

Pd-HF 혼합용액은 예컨대, 다음과 같이 구성한다.The Pd-HF mixed solution is constituted as follows, for example.

PdCl20.02gPdCl 2 0.02 g

HF 4mlHF 4ml

HCl 0.1mlHCl 0.1ml

빙초산(glacial acetic acid) 50ml50 ml of glacial acetic acid

순수(DI water) 4ml.4 ml of DI water.

한편, Pb 버퍼층(12) 형성에 앞서 콘택 영역의 실리콘 기판(10) 상에 형성된 산화물을 제거하여 구리의 부착 특성을 향상시키기 위하여 N2플라즈마 처리를 실시할 수도 있다.Meanwhile, before forming the Pb buffer layer 12, an N 2 plasma treatment may be performed to remove oxides formed on the silicon substrate 10 in the contact region to improve adhesion properties of copper.

계속하여, 도 3에 도시된 바와 같이 구리 무전해 도금법을 사용하여 Pd 버퍼층(12) 상에 구리층(13)을 증착한다. 이때, 구리층(13)은 Pd 버퍼층(12)을 시드층으로 하여 Pd 버퍼층(12) 상에만 선택적으로 증착된다.Subsequently, a copper layer 13 is deposited on the Pd buffer layer 12 using a copper electroless plating method as shown in FIG. At this time, the copper layer 13 is selectively deposited only on the Pd buffer layer 12 using the Pd buffer layer 12 as a seed layer.

구리 무전해 도금법을 수행하기 위한 용액은 다음과 같으며, 두 용액을 실질적인 60℃에서 실질적인 20분 동안 섞는다.The solution for carrying out the copper electroless plating method is as follows and the two solutions are mixed at substantially 60 ° C. for substantially 20 minutes.

A 용액A solution

CuSO4·5H2O 10g/lCuSO 4 5H 2 O 10 g / l

HCHO(37%) 60ml/lHCHO (37%) 60ml / l

CH3OH 30ml/lCH 3 OH 30ml / l

B 용액B solution

NaOH 40g/lNaOH 40g / l

KNa2H4O8·4H2O 28g/l KNa 2 H 4 O 8 · 4H 2 O 28g / l

일반적으로, 무전해 도금법에 의해 구리를 증착하고자 할 때, 실리콘산화막이나 다른 산화막에서서는 증착이 불가능하다. 뿐만 아니라 일부 장벽 금속, 실리사이드의 경우에도 이들 막이 열처리를 통해 그 상부가 산화되면 증착이 불가능해진다. 본 발명은 이러한 문제점을 기판 전처리 과정을 통해 해결하였으며, 그 결과 높은 증착 속도, 낮은 공정 비용, 증착의 편리성과 같은 무전해 도금법의 장점을 살릴 수 있게 되었다.In general, when copper is to be deposited by electroless plating, it is impossible to deposit from silicon oxide film or other oxide film. In addition, even in the case of some barrier metals and silicides, if these films are oxidized at the top through heat treatment, deposition becomes impossible. The present invention solved this problem through a substrate pretreatment process, and as a result, it is possible to take advantage of the electroless plating method such as high deposition rate, low process cost, and convenience of deposition.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 실리콘 기판에 콘택되는 하부 금속배선을 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 하부 금속배선에 콘택되는 상부 금속배선을 형성하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the case of forming the lower metal interconnection contacted to the silicon substrate has been described as an example, but the present invention can be applied to the case of forming the upper metal interconnection contacted to the lower metal interconnection.

또한, 전술한 실시예에서 사용된 Pd-HF 혼합용액과 구리 무전해 도금을 위한 A 용액 및 B 용액의 구성 물질 및 그 혼합비는 최적의 실시예를 나타낸 것으로, 그에 대한 치환 및 구성비의 변경이 가능하다.In addition, the constituent materials and the mixing ratios of the P solution and the B solution for the electroless plating of Pd-HF mixed solution used in the above-described embodiment and the mixing ratios are the best examples, and the substitution and composition ratio thereof can be changed. Do.

전술한 본 발명은 무전해 도금법을 통해 구리를 사용한 금속배선 공정을 단순화하는 효과가 있으며, CMP 공정을 사용하지 않기 때문에 제조 단가를 크게 낮출 수 있는 효과가 있다.The present invention described above has the effect of simplifying the metallization process using copper through the electroless plating method, there is an effect that can significantly reduce the manufacturing cost because the CMP process is not used.

Claims (4)

소정의 층간절연막을 관통하여 소정의 하부 도전층을 노출시키는 콘택홀을 형성하는 제1 단계;A first step of forming a contact hole penetrating a predetermined interlayer insulating film to expose a predetermined lower conductive layer; Pd-HF 혼합용액을 사용하여 금속배선이 형성될 영역에 Pd 버퍼층을 형성하는 제2 단계; 및A second step of forming a Pd buffer layer in a region where a metal wiring is to be formed using a Pd-HF mixed solution; And 구리 무전해 도금법을 사용하여 상기 Pd 버퍼층 상에 구리층을 형성하는 제3 단계A third step of forming a copper layer on the Pd buffer layer using a copper electroless plating method 를 포함하여 이루어진 반도체 소자의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 단계 수행 후,After performing the first step, N2플라즈마 처리를 실시하여 상기 하부 도전층 상에 형성된 산화물을 제거하는 제4 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And performing a N 2 plasma treatment to remove the oxide formed on the lower conductive layer. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 Pd-HF 혼합용액은 PdCl2, HF, HCl, 빙초산, 순수의 혼합용액인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The Pd-HF mixed solution is a method of forming a metal wiring of the semiconductor device, characterized in that the mixed solution of PdCl 2 , HF, HCl, glacial acetic acid, pure water. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 무전해 도금법은 CuSO4·5H2O, HCHO, CH3OH가 소정의 비율로 혼합된 제1 용액과, NaOH, KNa2H4O8·4H2O가 소정의 비율로 혼합된 제2 용액을 혼합한 용액을 사용하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The electroless plating method includes a first solution in which CuSO 4 · 5H 2 O, HCHO, CH 3 OH is mixed at a predetermined ratio, and a second in which NaOH, KNa 2 H 4 O 8 · 4H 2 O is mixed at a predetermined ratio. A method for forming metal wiring in a semiconductor device, comprising using a solution mixed with a solution.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100807948B1 (en) * 2007-02-28 2008-02-28 삼성전자주식회사 Method of preparing low resistance metal pattern, patterned metal wire structure, and display devices using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100807948B1 (en) * 2007-02-28 2008-02-28 삼성전자주식회사 Method of preparing low resistance metal pattern, patterned metal wire structure, and display devices using the same

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